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mips32, add option to avoid check in last instruction
[openocd.git] / src / target / armv4_5.c
blob2029ca92a35dbf23ae62dd64286cf75e0190c34c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm.h"
30 #include "armv4_5.h"
31 #include "arm_jtag.h"
32 #include "breakpoints.h"
33 #include "arm_disassembler.h"
34 #include <helper/binarybuffer.h>
35 #include "algorithm.h"
36 #include "register.h"
37
38 /* offsets into armv4_5 core register cache */
39 enum {
40 /* ARMV4_5_CPSR = 31, */
41 ARMV4_5_SPSR_FIQ = 32,
42 ARMV4_5_SPSR_IRQ = 33,
43 ARMV4_5_SPSR_SVC = 34,
44 ARMV4_5_SPSR_ABT = 35,
45 ARMV4_5_SPSR_UND = 36,
46 ARM_SPSR_MON = 41,
47 };
48
49 static const uint8_t arm_usr_indices[17] = {
50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
51 };
52
53 static const uint8_t arm_fiq_indices[8] = {
54 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
55 };
56
57 static const uint8_t arm_irq_indices[3] = {
58 23, 24, ARMV4_5_SPSR_IRQ,
59 };
60
61 static const uint8_t arm_svc_indices[3] = {
62 25, 26, ARMV4_5_SPSR_SVC,
63 };
64
65 static const uint8_t arm_abt_indices[3] = {
66 27, 28, ARMV4_5_SPSR_ABT,
67 };
68
69 static const uint8_t arm_und_indices[3] = {
70 29, 30, ARMV4_5_SPSR_UND,
71 };
72
73 static const uint8_t arm_mon_indices[3] = {
74 39, 40, ARM_SPSR_MON,
75 };
76
77 static const struct {
78 const char *name;
79 unsigned short psr;
80 /* For user and system modes, these list indices for all registers.
81 * otherwise they're just indices for the shadow registers and SPSR.
82 */
83 unsigned short n_indices;
84 const uint8_t *indices;
85 } arm_mode_data[] = {
86 /* Seven modes are standard from ARM7 on. "System" and "User" share
87 * the same registers; other modes shadow from 3 to 8 registers.
88 */
89 {
90 .name = "User",
91 .psr = ARM_MODE_USR,
92 .n_indices = ARRAY_SIZE(arm_usr_indices),
93 .indices = arm_usr_indices,
94 },
95 {
96 .name = "FIQ",
97 .psr = ARM_MODE_FIQ,
98 .n_indices = ARRAY_SIZE(arm_fiq_indices),
99 .indices = arm_fiq_indices,
100 },
101 {
102 .name = "Supervisor",
103 .psr = ARM_MODE_SVC,
104 .n_indices = ARRAY_SIZE(arm_svc_indices),
105 .indices = arm_svc_indices,
106 },
107 {
108 .name = "Abort",
109 .psr = ARM_MODE_ABT,
110 .n_indices = ARRAY_SIZE(arm_abt_indices),
111 .indices = arm_abt_indices,
112 },
113 {
114 .name = "IRQ",
115 .psr = ARM_MODE_IRQ,
116 .n_indices = ARRAY_SIZE(arm_irq_indices),
117 .indices = arm_irq_indices,
118 },
119 {
120 .name = "Undefined instruction",
121 .psr = ARM_MODE_UND,
122 .n_indices = ARRAY_SIZE(arm_und_indices),
123 .indices = arm_und_indices,
124 },
125 {
126 .name = "System",
127 .psr = ARM_MODE_SYS,
128 .n_indices = ARRAY_SIZE(arm_usr_indices),
129 .indices = arm_usr_indices,
130 },
131 /* TrustZone "Security Extensions" add a secure monitor mode.
132 * This is distinct from a "debug monitor" which can support
133 * non-halting debug, in conjunction with some debuggers.
134 */
135 {
136 .name = "Secure Monitor",
137 .psr = ARM_MODE_MON,
138 .n_indices = ARRAY_SIZE(arm_mon_indices),
139 .indices = arm_mon_indices,
140 },
141 {
142 .name = "Secure Monitor ARM1176JZF-S",
143 .psr = ARM_MODE_1176_MON,
144 .n_indices = ARRAY_SIZE(arm_mon_indices),
145 .indices = arm_mon_indices,
146 },
147
148 /* These special modes are currently only supported
149 * by ARMv6M and ARMv7M profiles */
150 {
151 .name = "Thread",
152 .psr = ARM_MODE_THREAD,
153 },
154 {
155 .name = "Thread (User)",
156 .psr = ARM_MODE_USER_THREAD,
157 },
158 {
159 .name = "Handler",
160 .psr = ARM_MODE_HANDLER,
161 },
162 };
163
164 /** Map PSR mode bits to the name of an ARM processor operating mode. */
165 const char *arm_mode_name(unsigned psr_mode)
166 {
167 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
168 if (arm_mode_data[i].psr == psr_mode)
169 return arm_mode_data[i].name;
170 }
171 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
172 return "UNRECOGNIZED";
173 }
174
175 /** Return true iff the parameter denotes a valid ARM processor mode. */
176 bool is_arm_mode(unsigned psr_mode)
177 {
178 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
179 if (arm_mode_data[i].psr == psr_mode)
180 return true;
181 }
182 return false;
183 }
184
185 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
186 int arm_mode_to_number(enum arm_mode mode)
187 {
188 switch (mode) {
189 case ARM_MODE_ANY:
190 /* map MODE_ANY to user mode */
191 case ARM_MODE_USR:
192 return 0;
193 case ARM_MODE_FIQ:
194 return 1;
195 case ARM_MODE_IRQ:
196 return 2;
197 case ARM_MODE_SVC:
198 return 3;
199 case ARM_MODE_ABT:
200 return 4;
201 case ARM_MODE_UND:
202 return 5;
203 case ARM_MODE_SYS:
204 return 6;
205 case ARM_MODE_MON:
206 case ARM_MODE_1176_MON:
207 return 7;
208 default:
209 LOG_ERROR("invalid mode value encountered %d", mode);
210 return -1;
211 }
212 }
213
214 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
215 enum arm_mode armv4_5_number_to_mode(int number)
216 {
217 switch (number) {
218 case 0:
219 return ARM_MODE_USR;
220 case 1:
221 return ARM_MODE_FIQ;
222 case 2:
223 return ARM_MODE_IRQ;
224 case 3:
225 return ARM_MODE_SVC;
226 case 4:
227 return ARM_MODE_ABT;
228 case 5:
229 return ARM_MODE_UND;
230 case 6:
231 return ARM_MODE_SYS;
232 case 7:
233 return ARM_MODE_MON;
234 default:
235 LOG_ERROR("mode index out of bounds %d", number);
236 return ARM_MODE_ANY;
237 }
238 }
239
240 static const char *arm_state_strings[] = {
241 "ARM", "Thumb", "Jazelle", "ThumbEE",
242 };
243
244 /* Templates for ARM core registers.
245 *
246 * NOTE: offsets in this table are coupled to the arm_mode_data
247 * table above, the armv4_5_core_reg_map array below, and also to
248 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
249 */
250 static const struct {
251 /* The name is used for e.g. the "regs" command. */
252 const char *name;
253
254 /* The {cookie, mode} tuple uniquely identifies one register.
255 * In a given mode, cookies 0..15 map to registers R0..R15,
256 * with R13..R15 usually called SP, LR, PC.
257 *
258 * MODE_ANY is used as *input* to the mapping, and indicates
259 * various special cases (sigh) and errors.
260 *
261 * Cookie 16 is (currently) confusing, since it indicates
262 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
263 * (Exception modes have both CPSR and SPSR registers ...)
264 */
265 unsigned cookie;
266 unsigned gdb_index;
267 enum arm_mode mode;
268 } arm_core_regs[] = {
269 /* IMPORTANT: we guarantee that the first eight cached registers
270 * correspond to r0..r7, and the fifteenth to PC, so that callers
271 * don't need to map them.
272 */
273 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
274 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
275 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
276 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
277 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
278 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
279 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
280 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
281
282 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
283 * them as MODE_ANY creates special cases. (ANY means
284 * "not mapped" elsewhere; here it's "everything but FIQ".)
285 */
286 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
287 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
288 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
289 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
290 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
291
292 /* Historical GDB mapping of indices:
293 * - 13-14 are sp and lr, but banked counterparts are used
294 * - 16-24 are left for deprecated 8 FPA + 1 FPS
295 * - 25 is the cpsr
296 */
297
298 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
299 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
300 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
301
302 /* guaranteed to be at index 15 */
303 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
304 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
305 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
306 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
307 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
308 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
309
310 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
311 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
312
313 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
314 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
315
316 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
317 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
318
319 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
320 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
321
322 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
323 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
324
325 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
326 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
327 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
328 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
329 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
330 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
331
332 /* These are only used for GDB target description, banked registers are accessed instead */
333 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
334 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
335
336 /* These exist only when the Security Extension (TrustZone) is present */
337 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
338 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
339 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
340
341 };
342
343 /* map core mode (USR, FIQ, ...) and register number to
344 * indices into the register cache
345 */
346 const int armv4_5_core_reg_map[8][17] = {
347 { /* USR */
348 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
349 },
350 { /* FIQ (8 shadows of USR, vs normal 3) */
351 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
352 },
353 { /* IRQ */
354 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
355 },
356 { /* SVC */
357 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
358 },
359 { /* ABT */
360 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
361 },
362 { /* UND */
363 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
364 },
365 { /* SYS (same registers as USR) */
366 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
367 },
368 { /* MON */
369 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
370 }
371 };
372
373 /**
374 * Configures host-side ARM records to reflect the specified CPSR.
375 * Later, code can use arm_reg_current() to map register numbers
376 * according to how they are exposed by this mode.
377 */
378 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
379 {
380 enum arm_mode mode = cpsr & 0x1f;
381 int num;
382
383 /* NOTE: this may be called very early, before the register
384 * cache is set up. We can't defend against many errors, in
385 * particular against CPSRs that aren't valid *here* ...
386 */
387 if (arm->cpsr) {
388 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
389 arm->cpsr->valid = 1;
390 arm->cpsr->dirty = 0;
391 }
392
393 arm->core_mode = mode;
394
395 /* mode_to_number() warned; set up a somewhat-sane mapping */
396 num = arm_mode_to_number(mode);
397 if (num < 0) {
398 mode = ARM_MODE_USR;
399 num = 0;
400 }
401
402 arm->map = &armv4_5_core_reg_map[num][0];
403 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
404 ? NULL
405 : arm->core_cache->reg_list + arm->map[16];
406
407 /* Older ARMs won't have the J bit */
408 enum arm_state state;
409
410 if (cpsr & (1 << 5)) { /* T */
411 if (cpsr & (1 << 24)) { /* J */
412 LOG_WARNING("ThumbEE -- incomplete support");
413 state = ARM_STATE_THUMB_EE;
414 } else
415 state = ARM_STATE_THUMB;
416 } else {
417 if (cpsr & (1 << 24)) { /* J */
418 LOG_ERROR("Jazelle state handling is BROKEN!");
419 state = ARM_STATE_JAZELLE;
420 } else
421 state = ARM_STATE_ARM;
422 }
423 arm->core_state = state;
424
425 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
426 arm_mode_name(mode),
427 arm_state_strings[arm->core_state]);
428 }
429
430 /**
431 * Returns handle to the register currently mapped to a given number.
432 * Someone must have called arm_set_cpsr() before.
433 *
434 * \param arm This core's state and registers are used.
435 * \param regnum From 0..15 corresponding to R0..R14 and PC.
436 * Note that R0..R7 don't require mapping; you may access those
437 * as the first eight entries in the register cache. Likewise
438 * R15 (PC) doesn't need mapping; you may also access it directly.
439 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
440 * CPSR (arm->cpsr) is also not mapped.
441 */
442 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
443 {
444 struct reg *r;
445
446 if (regnum > 16)
447 return NULL;
448
449 if (!arm->map) {
450 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
451 r = arm->core_cache->reg_list + regnum;
452 } else
453 r = arm->core_cache->reg_list + arm->map[regnum];
454
455 /* e.g. invalid CPSR said "secure monitor" mode on a core
456 * that doesn't support it...
457 */
458 if (!r) {
459 LOG_ERROR("Invalid CPSR mode");
460 r = arm->core_cache->reg_list + regnum;
461 }
462
463 return r;
464 }
465
466 static const uint8_t arm_gdb_dummy_fp_value[12];
467
468 static struct reg_feature arm_gdb_dummy_fp_features = {
469 .name = "net.sourceforge.openocd.fake_fpa"
470 };
471
472 /**
473 * Dummy FPA registers are required to support GDB on ARM.
474 * Register packets require eight obsolete FPA register values.
475 * Modern ARM cores use Vector Floating Point (VFP), if they
476 * have any floating point support. VFP is not FPA-compatible.
477 */
478 struct reg arm_gdb_dummy_fp_reg = {
479 .name = "GDB dummy FPA register",
480 .value = (uint8_t *) arm_gdb_dummy_fp_value,
481 .valid = 1,
482 .size = 96,
483 .exist = false,
484 .number = 16,
485 .feature = &arm_gdb_dummy_fp_features,
486 .group = "fake_fpa",
487 };
488
489 static const uint8_t arm_gdb_dummy_fps_value[4];
490
491 /**
492 * Dummy FPA status registers are required to support GDB on ARM.
493 * Register packets require an obsolete FPA status register.
494 */
495 struct reg arm_gdb_dummy_fps_reg = {
496 .name = "GDB dummy FPA status register",
497 .value = (uint8_t *) arm_gdb_dummy_fps_value,
498 .valid = 1,
499 .size = 32,
500 .exist = false,
501 .number = 24,
502 .feature = &arm_gdb_dummy_fp_features,
503 .group = "fake_fpa",
504 };
505
506 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
507
508 static void arm_gdb_dummy_init(void)
509 {
510 register_init_dummy(&arm_gdb_dummy_fp_reg);
511 register_init_dummy(&arm_gdb_dummy_fps_reg);
512 }
513
514 static int armv4_5_get_core_reg(struct reg *reg)
515 {
516 int retval;
517 struct arm_reg *reg_arch_info = reg->arch_info;
518 struct target *target = reg_arch_info->target;
519
520 if (target->state != TARGET_HALTED) {
521 LOG_ERROR("Target not halted");
522 return ERROR_TARGET_NOT_HALTED;
523 }
524
525 retval = reg_arch_info->arm->read_core_reg(target, reg,
526 reg_arch_info->num, reg_arch_info->mode);
527 if (retval == ERROR_OK) {
528 reg->valid = 1;
529 reg->dirty = 0;
530 }
531
532 return retval;
533 }
534
535 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
536 {
537 struct arm_reg *reg_arch_info = reg->arch_info;
538 struct target *target = reg_arch_info->target;
539 struct arm *armv4_5_target = target_to_arm(target);
540 uint32_t value = buf_get_u32(buf, 0, 32);
541
542 if (target->state != TARGET_HALTED) {
543 LOG_ERROR("Target not halted");
544 return ERROR_TARGET_NOT_HALTED;
545 }
546
547 /* Except for CPSR, the "reg" command exposes a writeback model
548 * for the register cache.
549 */
550 if (reg == armv4_5_target->cpsr) {
551 arm_set_cpsr(armv4_5_target, value);
552
553 /* Older cores need help to be in ARM mode during halt
554 * mode debug, so we clear the J and T bits if we flush.
555 * For newer cores (v6/v7a/v7r) we don't need that, but
556 * it won't hurt since CPSR is always flushed anyway.
557 */
558 if (armv4_5_target->core_mode !=
559 (enum arm_mode)(value & 0x1f)) {
560 LOG_DEBUG("changing ARM core mode to '%s'",
561 arm_mode_name(value & 0x1f));
562 value &= ~((1 << 24) | (1 << 5));
563 uint8_t t[4];
564 buf_set_u32(t, 0, 32, value);
565 armv4_5_target->write_core_reg(target, reg,
566 16, ARM_MODE_ANY, t);
567 }
568 } else {
569 buf_set_u32(reg->value, 0, 32, value);
570 reg->valid = 1;
571 }
572 reg->dirty = 1;
573
574 return ERROR_OK;
575 }
576
577 static const struct reg_arch_type arm_reg_type = {
578 .get = armv4_5_get_core_reg,
579 .set = armv4_5_set_core_reg,
580 };
581
582 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
583 {
584 int num_regs = ARRAY_SIZE(arm_core_regs);
585 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
586 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
587 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
588 int i;
589
590 if (!cache || !reg_list || !reg_arch_info) {
591 free(cache);
592 free(reg_list);
593 free(reg_arch_info);
594 return NULL;
595 }
596
597 cache->name = "ARM registers";
598 cache->next = NULL;
599 cache->reg_list = reg_list;
600 cache->num_regs = 0;
601
602 for (i = 0; i < num_regs; i++) {
603 /* Skip registers this core doesn't expose */
604 if (arm_core_regs[i].mode == ARM_MODE_MON
605 && arm->core_type != ARM_MODE_MON)
606 continue;
607
608 /* REVISIT handle Cortex-M, which only shadows R13/SP */
609
610 reg_arch_info[i].num = arm_core_regs[i].cookie;
611 reg_arch_info[i].mode = arm_core_regs[i].mode;
612 reg_arch_info[i].target = target;
613 reg_arch_info[i].arm = arm;
614
615 reg_list[i].name = arm_core_regs[i].name;
616 reg_list[i].number = arm_core_regs[i].gdb_index;
617 reg_list[i].size = 32;
618 reg_list[i].value = reg_arch_info[i].value;
619 reg_list[i].type = &arm_reg_type;
620 reg_list[i].arch_info = &reg_arch_info[i];
621 reg_list[i].exist = true;
622
623 /* This really depends on the calling convention in use */
624 reg_list[i].caller_save = false;
625
626 /* Registers data type, as used by GDB target description */
627 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
628 switch (arm_core_regs[i].cookie) {
629 case 13:
630 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
631 break;
632 case 14:
633 case 15:
634 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
635 break;
636 default:
637 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
638 break;
639 }
640
641 /* let GDB shows banked registers only in "info all-reg" */
642 reg_list[i].feature = malloc(sizeof(struct reg_feature));
643 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
644 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
645 reg_list[i].group = "general";
646 } else {
647 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
648 reg_list[i].group = "banked";
649 }
650
651 cache->num_regs++;
652 }
653
654 arm->pc = reg_list + 15;
655 arm->cpsr = reg_list + ARMV4_5_CPSR;
656 arm->core_cache = cache;
657 return cache;
658 }
659
660 int arm_arch_state(struct target *target)
661 {
662 struct arm *arm = target_to_arm(target);
663
664 if (arm->common_magic != ARM_COMMON_MAGIC) {
665 LOG_ERROR("BUG: called for a non-ARM target");
666 return ERROR_FAIL;
667 }
668
669 /* avoid filling log waiting for fileio reply */
670 if (arm->semihosting_hit_fileio)
671 return ERROR_OK;
672
673 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
674 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
675 arm_state_strings[arm->core_state],
676 debug_reason_name(target),
677 arm_mode_name(arm->core_mode),
678 buf_get_u32(arm->cpsr->value, 0, 32),
679 buf_get_u32(arm->pc->value, 0, 32),
680 arm->is_semihosting ? ", semihosting" : "",
681 arm->is_semihosting_fileio ? " fileio" : "");
682
683 return ERROR_OK;
684 }
685
686 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
687 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
688
689 COMMAND_HANDLER(handle_armv4_5_reg_command)
690 {
691 struct target *target = get_current_target(CMD_CTX);
692 struct arm *arm = target_to_arm(target);
693 struct reg *regs;
694
695 if (!is_arm(arm)) {
696 command_print(CMD_CTX, "current target isn't an ARM");
697 return ERROR_FAIL;
698 }
699
700 if (target->state != TARGET_HALTED) {
701 command_print(CMD_CTX, "error: target must be halted for register accesses");
702 return ERROR_FAIL;
703 }
704
705 if (arm->core_type != ARM_MODE_ANY) {
706 command_print(CMD_CTX,
707 "Microcontroller Profile not supported - use standard reg cmd");
708 return ERROR_OK;
709 }
710
711 if (!is_arm_mode(arm->core_mode)) {
712 LOG_ERROR("not a valid arm core mode - communication failure?");
713 return ERROR_FAIL;
714 }
715
716 if (!arm->full_context) {
717 command_print(CMD_CTX, "error: target doesn't support %s",
718 CMD_NAME);
719 return ERROR_FAIL;
720 }
721
722 regs = arm->core_cache->reg_list;
723
724 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
725 const char *name;
726 char *sep = "\n";
727 char *shadow = "";
728
729 /* label this bank of registers (or shadows) */
730 switch (arm_mode_data[mode].psr) {
731 case ARM_MODE_SYS:
732 continue;
733 case ARM_MODE_USR:
734 name = "System and User";
735 sep = "";
736 break;
737 case ARM_MODE_MON:
738 if (arm->core_type != ARM_MODE_MON)
739 continue;
740 /* FALLTHROUGH */
741 default:
742 name = arm_mode_data[mode].name;
743 shadow = "shadow ";
744 break;
745 }
746 command_print(CMD_CTX, "%s%s mode %sregisters",
747 sep, name, shadow);
748
749 /* display N rows of up to 4 registers each */
750 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
751 char output[80];
752 int output_len = 0;
753
754 for (unsigned j = 0; j < 4; j++, i++) {
755 uint32_t value;
756 struct reg *reg = regs;
757
758 if (i >= arm_mode_data[mode].n_indices)
759 break;
760
761 reg += arm_mode_data[mode].indices[i];
762
763 /* REVISIT be smarter about faults... */
764 if (!reg->valid)
765 arm->full_context(target);
766
767 value = buf_get_u32(reg->value, 0, 32);
768 output_len += snprintf(output + output_len,
769 sizeof(output) - output_len,
770 "%8s: %8.8" PRIx32 " ",
771 reg->name, value);
772 }
773 command_print(CMD_CTX, "%s", output);
774 }
775 }
776
777 return ERROR_OK;
778 }
779
780 COMMAND_HANDLER(handle_armv4_5_core_state_command)
781 {
782 struct target *target = get_current_target(CMD_CTX);
783 struct arm *arm = target_to_arm(target);
784
785 if (!is_arm(arm)) {
786 command_print(CMD_CTX, "current target isn't an ARM");
787 return ERROR_FAIL;
788 }
789
790 if (arm->core_type == ARM_MODE_THREAD) {
791 /* armv7m not supported */
792 command_print(CMD_CTX, "Unsupported Command");
793 return ERROR_OK;
794 }
795
796 if (CMD_ARGC > 0) {
797 if (strcmp(CMD_ARGV[0], "arm") == 0)
798 arm->core_state = ARM_STATE_ARM;
799 if (strcmp(CMD_ARGV[0], "thumb") == 0)
800 arm->core_state = ARM_STATE_THUMB;
801 }
802
803 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
804
805 return ERROR_OK;
806 }
807
808 COMMAND_HANDLER(handle_arm_disassemble_command)
809 {
810 int retval = ERROR_OK;
811 struct target *target = get_current_target(CMD_CTX);
812
813 if (target == NULL) {
814 LOG_ERROR("No target selected");
815 return ERROR_FAIL;
816 }
817
818 struct arm *arm = target_to_arm(target);
819 target_addr_t address;
820 int count = 1;
821 int thumb = 0;
822
823 if (!is_arm(arm)) {
824 command_print(CMD_CTX, "current target isn't an ARM");
825 return ERROR_FAIL;
826 }
827
828 if (arm->core_type == ARM_MODE_THREAD) {
829 /* armv7m is always thumb mode */
830 thumb = 1;
831 }
832
833 switch (CMD_ARGC) {
834 case 3:
835 if (strcmp(CMD_ARGV[2], "thumb") != 0)
836 goto usage;
837 thumb = 1;
838 /* FALL THROUGH */
839 case 2:
840 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
841 /* FALL THROUGH */
842 case 1:
843 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
844 if (address & 0x01) {
845 if (!thumb) {
846 command_print(CMD_CTX, "Disassemble as Thumb");
847 thumb = 1;
848 }
849 address &= ~1;
850 }
851 break;
852 default:
853 usage:
854 count = 0;
855 retval = ERROR_COMMAND_SYNTAX_ERROR;
856 }
857
858 while (count-- > 0) {
859 struct arm_instruction cur_instruction;
860
861 if (thumb) {
862 /* Always use Thumb2 disassembly for best handling
863 * of 32-bit BL/BLX, and to work with newer cores
864 * (some ARMv6, all ARMv7) that use Thumb2.
865 */
866 retval = thumb2_opcode(target, address,
867 &cur_instruction);
868 if (retval != ERROR_OK)
869 break;
870 } else {
871 uint32_t opcode;
872
873 retval = target_read_u32(target, address, &opcode);
874 if (retval != ERROR_OK)
875 break;
876 retval = arm_evaluate_opcode(opcode, address,
877 &cur_instruction) != ERROR_OK;
878 if (retval != ERROR_OK)
879 break;
880 }
881 command_print(CMD_CTX, "%s", cur_instruction.text);
882 address += cur_instruction.instruction_size;
883 }
884
885 return retval;
886 }
887
888 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
889 {
890 struct command_context *context;
891 struct target *target;
892 struct arm *arm;
893 int retval;
894
895 context = current_command_context(interp);
896 assert(context != NULL);
897
898 target = get_current_target(context);
899 if (target == NULL) {
900 LOG_ERROR("%s: no current target", __func__);
901 return JIM_ERR;
902 }
903 if (!target_was_examined(target)) {
904 LOG_ERROR("%s: not yet examined", target_name(target));
905 return JIM_ERR;
906 }
907 arm = target_to_arm(target);
908 if (!is_arm(arm)) {
909 LOG_ERROR("%s: not an ARM", target_name(target));
910 return JIM_ERR;
911 }
912
913 if ((argc < 6) || (argc > 7)) {
914 /* FIXME use the command name to verify # params... */
915 LOG_ERROR("%s: wrong number of arguments", __func__);
916 return JIM_ERR;
917 }
918
919 int cpnum;
920 uint32_t op1;
921 uint32_t op2;
922 uint32_t CRn;
923 uint32_t CRm;
924 uint32_t value;
925 long l;
926
927 /* NOTE: parameter sequence matches ARM instruction set usage:
928 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
929 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
930 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
931 */
932 retval = Jim_GetLong(interp, argv[1], &l);
933 if (retval != JIM_OK)
934 return retval;
935 if (l & ~0xf) {
936 LOG_ERROR("%s: %s %d out of range", __func__,
937 "coprocessor", (int) l);
938 return JIM_ERR;
939 }
940 cpnum = l;
941
942 retval = Jim_GetLong(interp, argv[2], &l);
943 if (retval != JIM_OK)
944 return retval;
945 if (l & ~0x7) {
946 LOG_ERROR("%s: %s %d out of range", __func__,
947 "op1", (int) l);
948 return JIM_ERR;
949 }
950 op1 = l;
951
952 retval = Jim_GetLong(interp, argv[3], &l);
953 if (retval != JIM_OK)
954 return retval;
955 if (l & ~0xf) {
956 LOG_ERROR("%s: %s %d out of range", __func__,
957 "CRn", (int) l);
958 return JIM_ERR;
959 }
960 CRn = l;
961
962 retval = Jim_GetLong(interp, argv[4], &l);
963 if (retval != JIM_OK)
964 return retval;
965 if (l & ~0xf) {
966 LOG_ERROR("%s: %s %d out of range", __func__,
967 "CRm", (int) l);
968 return JIM_ERR;
969 }
970 CRm = l;
971
972 retval = Jim_GetLong(interp, argv[5], &l);
973 if (retval != JIM_OK)
974 return retval;
975 if (l & ~0x7) {
976 LOG_ERROR("%s: %s %d out of range", __func__,
977 "op2", (int) l);
978 return JIM_ERR;
979 }
980 op2 = l;
981
982 value = 0;
983
984 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
985 * that could easily be a typo! Check both...
986 *
987 * FIXME change the call syntax here ... simplest to just pass
988 * the MRC() or MCR() instruction to be executed. That will also
989 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
990 * if that's ever needed.
991 */
992 if (argc == 7) {
993 retval = Jim_GetLong(interp, argv[6], &l);
994 if (retval != JIM_OK)
995 return retval;
996 value = l;
997
998 /* NOTE: parameters reordered! */
999 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
1000 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
1001 if (retval != ERROR_OK)
1002 return JIM_ERR;
1003 } else {
1004 /* NOTE: parameters reordered! */
1005 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1006 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
1007 if (retval != ERROR_OK)
1008 return JIM_ERR;
1009
1010 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1011 }
1012
1013 return JIM_OK;
1014 }
1015
1016 COMMAND_HANDLER(handle_arm_semihosting_command)
1017 {
1018 struct target *target = get_current_target(CMD_CTX);
1019
1020 if (target == NULL) {
1021 LOG_ERROR("No target selected");
1022 return ERROR_FAIL;
1023 }
1024
1025 struct arm *arm = target_to_arm(target);
1026
1027 if (!is_arm(arm)) {
1028 command_print(CMD_CTX, "current target isn't an ARM");
1029 return ERROR_FAIL;
1030 }
1031
1032 if (!arm->setup_semihosting) {
1033 command_print(CMD_CTX, "semihosting not supported for current target");
1034 return ERROR_FAIL;
1035 }
1036
1037 if (CMD_ARGC > 0) {
1038 int semihosting;
1039
1040 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
1041
1042 if (!target_was_examined(target)) {
1043 LOG_ERROR("Target not examined yet");
1044 return ERROR_FAIL;
1045 }
1046
1047 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
1048 LOG_ERROR("Failed to Configure semihosting");
1049 return ERROR_FAIL;
1050 }
1051
1052 /* FIXME never let that "catch" be dropped! */
1053 arm->is_semihosting = semihosting;
1054 }
1055
1056 command_print(CMD_CTX, "semihosting is %s",
1057 arm->is_semihosting
1058 ? "enabled" : "disabled");
1059
1060 return ERROR_OK;
1061 }
1062
1063 COMMAND_HANDLER(handle_arm_semihosting_fileio_command)
1064 {
1065 struct target *target = get_current_target(CMD_CTX);
1066
1067 if (target == NULL) {
1068 LOG_ERROR("No target selected");
1069 return ERROR_FAIL;
1070 }
1071
1072 struct arm *arm = target_to_arm(target);
1073
1074 if (!is_arm(arm)) {
1075 command_print(CMD_CTX, "current target isn't an ARM");
1076 return ERROR_FAIL;
1077 }
1078
1079 if (!arm->is_semihosting) {
1080 command_print(CMD_CTX, "semihosting is not enabled");
1081 return ERROR_FAIL;
1082 }
1083
1084 if (CMD_ARGC > 0)
1085 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm->is_semihosting_fileio);
1086
1087 command_print(CMD_CTX, "semihosting fileio is %s",
1088 arm->is_semihosting_fileio
1089 ? "enabled" : "disabled");
1090
1091 return ERROR_OK;
1092 }
1093
1094 static const struct command_registration arm_exec_command_handlers[] = {
1095 {
1096 .name = "reg",
1097 .handler = handle_armv4_5_reg_command,
1098 .mode = COMMAND_EXEC,
1099 .help = "display ARM core registers",
1100 .usage = "",
1101 },
1102 {
1103 .name = "core_state",
1104 .handler = handle_armv4_5_core_state_command,
1105 .mode = COMMAND_EXEC,
1106 .usage = "['arm'|'thumb']",
1107 .help = "display/change ARM core state",
1108 },
1109 {
1110 .name = "disassemble",
1111 .handler = handle_arm_disassemble_command,
1112 .mode = COMMAND_EXEC,
1113 .usage = "address [count ['thumb']]",
1114 .help = "disassemble instructions ",
1115 },
1116 {
1117 .name = "mcr",
1118 .mode = COMMAND_EXEC,
1119 .jim_handler = &jim_mcrmrc,
1120 .help = "write coprocessor register",
1121 .usage = "cpnum op1 CRn CRm op2 value",
1122 },
1123 {
1124 .name = "mrc",
1125 .jim_handler = &jim_mcrmrc,
1126 .help = "read coprocessor register",
1127 .usage = "cpnum op1 CRn CRm op2",
1128 },
1129 {
1130 "semihosting",
1131 .handler = handle_arm_semihosting_command,
1132 .mode = COMMAND_EXEC,
1133 .usage = "['enable'|'disable']",
1134 .help = "activate support for semihosting operations",
1135 },
1136 {
1137 "semihosting_fileio",
1138 .handler = handle_arm_semihosting_fileio_command,
1139 .mode = COMMAND_EXEC,
1140 .usage = "['enable'|'disable']",
1141 .help = "activate support for semihosting fileio operations",
1142 },
1143
1144 COMMAND_REGISTRATION_DONE
1145 };
1146 const struct command_registration arm_command_handlers[] = {
1147 {
1148 .name = "arm",
1149 .mode = COMMAND_ANY,
1150 .help = "ARM command group",
1151 .usage = "",
1152 .chain = arm_exec_command_handlers,
1153 },
1154 COMMAND_REGISTRATION_DONE
1155 };
1156
1157 int arm_get_gdb_reg_list(struct target *target,
1158 struct reg **reg_list[], int *reg_list_size,
1159 enum target_register_class reg_class)
1160 {
1161 struct arm *arm = target_to_arm(target);
1162 unsigned int i;
1163
1164 if (!is_arm_mode(arm->core_mode)) {
1165 LOG_ERROR("not a valid arm core mode - communication failure?");
1166 return ERROR_FAIL;
1167 }
1168
1169 switch (reg_class) {
1170 case REG_CLASS_GENERAL:
1171 *reg_list_size = 26;
1172 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1173
1174 for (i = 0; i < 16; i++)
1175 (*reg_list)[i] = arm_reg_current(arm, i);
1176
1177 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1178 for (i = 16; i < 24; i++)
1179 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1180 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1181
1182 (*reg_list)[25] = arm->cpsr;
1183
1184 return ERROR_OK;
1185 break;
1186
1187 case REG_CLASS_ALL:
1188 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1189 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1190
1191 for (i = 0; i < 16; i++)
1192 (*reg_list)[i] = arm_reg_current(arm, i);
1193
1194 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1195 int reg_index = arm->core_cache->reg_list[i].number;
1196 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1197 && arm->core_type != ARM_MODE_MON))
1198 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1199 }
1200
1201 /* When we supply the target description, there is no need for fake FPA */
1202 for (i = 16; i < 24; i++) {
1203 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1204 (*reg_list)[i]->size = 0;
1205 }
1206 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1207 (*reg_list)[24]->size = 0;
1208
1209 return ERROR_OK;
1210 break;
1211
1212 default:
1213 LOG_ERROR("not a valid register class type in query.");
1214 return ERROR_FAIL;
1215 break;
1216 }
1217 }
1218
1219 /* wait for execution to complete and check exit point */
1220 static int armv4_5_run_algorithm_completion(struct target *target,
1221 uint32_t exit_point,
1222 int timeout_ms,
1223 void *arch_info)
1224 {
1225 int retval;
1226 struct arm *arm = target_to_arm(target);
1227
1228 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1229 if (retval != ERROR_OK)
1230 return retval;
1231 if (target->state != TARGET_HALTED) {
1232 retval = target_halt(target);
1233 if (retval != ERROR_OK)
1234 return retval;
1235 retval = target_wait_state(target, TARGET_HALTED, 500);
1236 if (retval != ERROR_OK)
1237 return retval;
1238 return ERROR_TARGET_TIMEOUT;
1239 }
1240
1241 /* fast exit: ARMv5+ code can use BKPT */
1242 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1243 LOG_WARNING(
1244 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1245 buf_get_u32(arm->pc->value, 0, 32));
1246 return ERROR_TARGET_TIMEOUT;
1247 }
1248
1249 return ERROR_OK;
1250 }
1251
1252 int armv4_5_run_algorithm_inner(struct target *target,
1253 int num_mem_params, struct mem_param *mem_params,
1254 int num_reg_params, struct reg_param *reg_params,
1255 uint32_t entry_point, uint32_t exit_point,
1256 int timeout_ms, void *arch_info,
1257 int (*run_it)(struct target *target, uint32_t exit_point,
1258 int timeout_ms, void *arch_info))
1259 {
1260 struct arm *arm = target_to_arm(target);
1261 struct arm_algorithm *arm_algorithm_info = arch_info;
1262 enum arm_state core_state = arm->core_state;
1263 uint32_t context[17];
1264 uint32_t cpsr;
1265 int exit_breakpoint_size = 0;
1266 int i;
1267 int retval = ERROR_OK;
1268
1269 LOG_DEBUG("Running algorithm");
1270
1271 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1272 LOG_ERROR("current target isn't an ARMV4/5 target");
1273 return ERROR_TARGET_INVALID;
1274 }
1275
1276 if (target->state != TARGET_HALTED) {
1277 LOG_WARNING("target not halted");
1278 return ERROR_TARGET_NOT_HALTED;
1279 }
1280
1281 if (!is_arm_mode(arm->core_mode)) {
1282 LOG_ERROR("not a valid arm core mode - communication failure?");
1283 return ERROR_FAIL;
1284 }
1285
1286 /* armv5 and later can terminate with BKPT instruction; less overhead */
1287 if (!exit_point && arm->is_armv4) {
1288 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1289 return ERROR_FAIL;
1290 }
1291
1292 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1293 * they'll be restored later.
1294 */
1295 for (i = 0; i <= 16; i++) {
1296 struct reg *r;
1297
1298 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1299 arm_algorithm_info->core_mode, i);
1300 if (!r->valid)
1301 arm->read_core_reg(target, r, i,
1302 arm_algorithm_info->core_mode);
1303 context[i] = buf_get_u32(r->value, 0, 32);
1304 }
1305 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1306
1307 for (i = 0; i < num_mem_params; i++) {
1308 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1309 mem_params[i].value);
1310 if (retval != ERROR_OK)
1311 return retval;
1312 }
1313
1314 for (i = 0; i < num_reg_params; i++) {
1315 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1316 if (!reg) {
1317 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1318 return ERROR_COMMAND_SYNTAX_ERROR;
1319 }
1320
1321 if (reg->size != reg_params[i].size) {
1322 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1323 reg_params[i].reg_name);
1324 return ERROR_COMMAND_SYNTAX_ERROR;
1325 }
1326
1327 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1328 if (retval != ERROR_OK)
1329 return retval;
1330 }
1331
1332 arm->core_state = arm_algorithm_info->core_state;
1333 if (arm->core_state == ARM_STATE_ARM)
1334 exit_breakpoint_size = 4;
1335 else if (arm->core_state == ARM_STATE_THUMB)
1336 exit_breakpoint_size = 2;
1337 else {
1338 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1339 return ERROR_COMMAND_SYNTAX_ERROR;
1340 }
1341
1342 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1343 LOG_DEBUG("setting core_mode: 0x%2.2x",
1344 arm_algorithm_info->core_mode);
1345 buf_set_u32(arm->cpsr->value, 0, 5,
1346 arm_algorithm_info->core_mode);
1347 arm->cpsr->dirty = 1;
1348 arm->cpsr->valid = 1;
1349 }
1350
1351 /* terminate using a hardware or (ARMv5+) software breakpoint */
1352 if (exit_point) {
1353 retval = breakpoint_add(target, exit_point,
1354 exit_breakpoint_size, BKPT_HARD);
1355 if (retval != ERROR_OK) {
1356 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1357 return ERROR_TARGET_FAILURE;
1358 }
1359 }
1360
1361 retval = target_resume(target, 0, entry_point, 1, 1);
1362 if (retval != ERROR_OK)
1363 return retval;
1364 retval = run_it(target, exit_point, timeout_ms, arch_info);
1365
1366 if (exit_point)
1367 breakpoint_remove(target, exit_point);
1368
1369 if (retval != ERROR_OK)
1370 return retval;
1371
1372 for (i = 0; i < num_mem_params; i++) {
1373 if (mem_params[i].direction != PARAM_OUT) {
1374 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1375 mem_params[i].size,
1376 mem_params[i].value);
1377 if (retvaltemp != ERROR_OK)
1378 retval = retvaltemp;
1379 }
1380 }
1381
1382 for (i = 0; i < num_reg_params; i++) {
1383 if (reg_params[i].direction != PARAM_OUT) {
1384
1385 struct reg *reg = register_get_by_name(arm->core_cache,
1386 reg_params[i].reg_name,
1387 0);
1388 if (!reg) {
1389 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1390 retval = ERROR_COMMAND_SYNTAX_ERROR;
1391 continue;
1392 }
1393
1394 if (reg->size != reg_params[i].size) {
1395 LOG_ERROR(
1396 "BUG: register '%s' size doesn't match reg_params[i].size",
1397 reg_params[i].reg_name);
1398 retval = ERROR_COMMAND_SYNTAX_ERROR;
1399 continue;
1400 }
1401
1402 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1403 }
1404 }
1405
1406 /* restore everything we saved before (17 or 18 registers) */
1407 for (i = 0; i <= 16; i++) {
1408 uint32_t regvalue;
1409 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1410 arm_algorithm_info->core_mode, i).value, 0, 32);
1411 if (regvalue != context[i]) {
1412 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1413 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1414 arm_algorithm_info->core_mode, i).name, context[i]);
1415 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1416 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1417 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1418 i).valid = 1;
1419 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1420 i).dirty = 1;
1421 }
1422 }
1423
1424 arm_set_cpsr(arm, cpsr);
1425 arm->cpsr->dirty = 1;
1426
1427 arm->core_state = core_state;
1428
1429 return retval;
1430 }
1431
1432 int armv4_5_run_algorithm(struct target *target,
1433 int num_mem_params,
1434 struct mem_param *mem_params,
1435 int num_reg_params,
1436 struct reg_param *reg_params,
1437 target_addr_t entry_point,
1438 target_addr_t exit_point,
1439 int timeout_ms,
1440 void *arch_info)
1441 {
1442 return armv4_5_run_algorithm_inner(target,
1443 num_mem_params,
1444 mem_params,
1445 num_reg_params,
1446 reg_params,
1447 (uint32_t)entry_point,
1448 (uint32_t)exit_point,
1449 timeout_ms,
1450 arch_info,
1451 armv4_5_run_algorithm_completion);
1452 }
1453
1454 /**
1455 * Runs ARM code in the target to calculate a CRC32 checksum.
1456 *
1457 */
1458 int arm_checksum_memory(struct target *target,
1459 target_addr_t address, uint32_t count, uint32_t *checksum)
1460 {
1461 struct working_area *crc_algorithm;
1462 struct arm_algorithm arm_algo;
1463 struct arm *arm = target_to_arm(target);
1464 struct reg_param reg_params[2];
1465 int retval;
1466 uint32_t i;
1467 uint32_t exit_var = 0;
1468
1469 static const uint8_t arm_crc_code_le[] = {
1470 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1471 };
1472
1473 assert(sizeof(arm_crc_code_le) % 4 == 0);
1474
1475 retval = target_alloc_working_area(target,
1476 sizeof(arm_crc_code_le), &crc_algorithm);
1477 if (retval != ERROR_OK)
1478 return retval;
1479
1480 /* convert code into a buffer in target endianness */
1481 for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1482 retval = target_write_u32(target,
1483 crc_algorithm->address + i * sizeof(uint32_t),
1484 le_to_h_u32(&arm_crc_code_le[i * 4]));
1485 if (retval != ERROR_OK)
1486 goto cleanup;
1487 }
1488
1489 arm_algo.common_magic = ARM_COMMON_MAGIC;
1490 arm_algo.core_mode = ARM_MODE_SVC;
1491 arm_algo.core_state = ARM_STATE_ARM;
1492
1493 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1494 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1495
1496 buf_set_u32(reg_params[0].value, 0, 32, address);
1497 buf_set_u32(reg_params[1].value, 0, 32, count);
1498
1499 /* 20 second timeout/megabyte */
1500 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1501
1502 /* armv4 must exit using a hardware breakpoint */
1503 if (arm->is_armv4)
1504 exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
1505
1506 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1507 crc_algorithm->address,
1508 exit_var,
1509 timeout, &arm_algo);
1510
1511 if (retval == ERROR_OK)
1512 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1513 else
1514 LOG_ERROR("error executing ARM crc algorithm");
1515
1516 destroy_reg_param(&reg_params[0]);
1517 destroy_reg_param(&reg_params[1]);
1518
1519 cleanup:
1520 target_free_working_area(target, crc_algorithm);
1521
1522 return retval;
1523 }
1524
1525 /**
1526 * Runs ARM code in the target to check whether a memory block holds
1527 * all ones. NOR flash which has been erased, and thus may be written,
1528 * holds all ones.
1529 *
1530 */
1531 int arm_blank_check_memory(struct target *target,
1532 target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
1533 {
1534 struct working_area *check_algorithm;
1535 struct reg_param reg_params[3];
1536 struct arm_algorithm arm_algo;
1537 struct arm *arm = target_to_arm(target);
1538 int retval;
1539 uint32_t i;
1540 uint32_t exit_var = 0;
1541
1542 static const uint8_t check_code_le[] = {
1543 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1544 };
1545
1546 assert(sizeof(check_code_le) % 4 == 0);
1547
1548 if (erased_value != 0xff) {
1549 LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
1550 erased_value);
1551 return ERROR_FAIL;
1552 }
1553
1554 /* make sure we have a working area */
1555 retval = target_alloc_working_area(target,
1556 sizeof(check_code_le), &check_algorithm);
1557 if (retval != ERROR_OK)
1558 return retval;
1559
1560 /* convert code into a buffer in target endianness */
1561 for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
1562 retval = target_write_u32(target,
1563 check_algorithm->address
1564 + i * sizeof(uint32_t),
1565 le_to_h_u32(&check_code_le[i * 4]));
1566 if (retval != ERROR_OK)
1567 goto cleanup;
1568 }
1569
1570 arm_algo.common_magic = ARM_COMMON_MAGIC;
1571 arm_algo.core_mode = ARM_MODE_SVC;
1572 arm_algo.core_state = ARM_STATE_ARM;
1573
1574 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1575 buf_set_u32(reg_params[0].value, 0, 32, address);
1576
1577 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1578 buf_set_u32(reg_params[1].value, 0, 32, count);
1579
1580 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1581 buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1582
1583 /* armv4 must exit using a hardware breakpoint */
1584 if (arm->is_armv4)
1585 exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
1586
1587 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1588 check_algorithm->address,
1589 exit_var,
1590 10000, &arm_algo);
1591
1592 if (retval == ERROR_OK)
1593 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1594
1595 destroy_reg_param(&reg_params[0]);
1596 destroy_reg_param(&reg_params[1]);
1597 destroy_reg_param(&reg_params[2]);
1598
1599 cleanup:
1600 target_free_working_area(target, check_algorithm);
1601
1602 return retval;
1603 }
1604
1605 static int arm_full_context(struct target *target)
1606 {
1607 struct arm *arm = target_to_arm(target);
1608 unsigned num_regs = arm->core_cache->num_regs;
1609 struct reg *reg = arm->core_cache->reg_list;
1610 int retval = ERROR_OK;
1611
1612 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1613 if (reg->valid)
1614 continue;
1615 retval = armv4_5_get_core_reg(reg);
1616 }
1617 return retval;
1618 }
1619
1620 static int arm_default_mrc(struct target *target, int cpnum,
1621 uint32_t op1, uint32_t op2,
1622 uint32_t CRn, uint32_t CRm,
1623 uint32_t *value)
1624 {
1625 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1626 return ERROR_FAIL;
1627 }
1628
1629 static int arm_default_mcr(struct target *target, int cpnum,
1630 uint32_t op1, uint32_t op2,
1631 uint32_t CRn, uint32_t CRm,
1632 uint32_t value)
1633 {
1634 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1635 return ERROR_FAIL;
1636 }
1637
1638 int arm_init_arch_info(struct target *target, struct arm *arm)
1639 {
1640 target->arch_info = arm;
1641 arm->target = target;
1642
1643 arm->common_magic = ARM_COMMON_MAGIC;
1644
1645 /* core_type may be overridden by subtype logic */
1646 if (arm->core_type != ARM_MODE_THREAD) {
1647 arm->core_type = ARM_MODE_ANY;
1648 arm_set_cpsr(arm, ARM_MODE_USR);
1649 }
1650
1651 /* default full_context() has no core-specific optimizations */
1652 if (!arm->full_context && arm->read_core_reg)
1653 arm->full_context = arm_full_context;
1654
1655 if (!arm->mrc)
1656 arm->mrc = arm_default_mrc;
1657 if (!arm->mcr)
1658 arm->mcr = arm_default_mcr;
1659
1660 return ERROR_OK;
1661 }
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