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Cortex-A8: support "reset-assert" event
[openocd.git] / src / target / cortex_a8.c
blob8402081dfc947a2b20caa2e18b7ad6c0e407a38e
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
30 * *
31 ***************************************************************************/
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "breakpoints.h"
37 #include "cortex_a8.h"
38 #include "register.h"
39 #include "target_request.h"
40 #include "target_type.h"
41
42 static int cortex_a8_poll(struct target *target);
43 static int cortex_a8_debug_entry(struct target *target);
44 static int cortex_a8_restore_context(struct target *target);
45 static int cortex_a8_set_breakpoint(struct target *target,
46 struct breakpoint *breakpoint, uint8_t matchmode);
47 static int cortex_a8_unset_breakpoint(struct target *target,
48 struct breakpoint *breakpoint);
49 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
50 uint32_t *value, int regnum);
51 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
52 uint32_t value, int regnum);
53 /*
54 * FIXME do topology discovery using the ROM; don't
55 * assume this is an OMAP3.
56 */
57 #define swjdp_memoryap 0
58 #define swjdp_debugap 1
59 #define OMAP3530_DEBUG_BASE 0x54011000
60
61 /*
62 * Cortex-A8 Basic debug access, very low level assumes state is saved
63 */
64 static int cortex_a8_init_debug_access(struct target *target)
65 {
66 struct armv7a_common *armv7a = target_to_armv7a(target);
67 struct swjdp_common *swjdp = &armv7a->swjdp_info;
68
69 int retval;
70 uint32_t dummy;
71
72 LOG_DEBUG(" ");
73
74 /* Unlocking the debug registers for modification */
75 /* The debugport might be uninitialised so try twice */
76 retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
77 if (retval != ERROR_OK)
78 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
79 /* Clear Sticky Power Down status Bit in PRSR to enable access to
80 the registers in the Core Power Domain */
81 retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
82 /* Enabling of instruction execution in debug mode is done in debug_entry code */
83
84 /* Resync breakpoint registers */
85
86 /* Since this is likley called from init or reset, update targtet state information*/
87 cortex_a8_poll(target);
88
89 return retval;
90 }
91
92 /* To reduce needless round-trips, pass in a pointer to the current
93 * DSCR value. Initialize it to zero if you just need to know the
94 * value on return from this function; or (1 << DSCR_INSTR_COMP) if
95 * you happen to know that no instruction is pending.
96 */
97 static int cortex_a8_exec_opcode(struct target *target,
98 uint32_t opcode, uint32_t *dscr_p)
99 {
100 uint32_t dscr;
101 int retval;
102 struct armv7a_common *armv7a = target_to_armv7a(target);
103 struct swjdp_common *swjdp = &armv7a->swjdp_info;
104
105 dscr = dscr_p ? *dscr_p : 0;
106
107 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
108
109 /* Wait for InstrCompl bit to be set */
110 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
111 {
112 retval = mem_ap_read_atomic_u32(swjdp,
113 armv7a->debug_base + CPUDBG_DSCR, &dscr);
114 if (retval != ERROR_OK)
115 {
116 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
117 return retval;
118 }
119 }
120
121 mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
122
123 do
124 {
125 retval = mem_ap_read_atomic_u32(swjdp,
126 armv7a->debug_base + CPUDBG_DSCR, &dscr);
127 if (retval != ERROR_OK)
128 {
129 LOG_ERROR("Could not read DSCR register");
130 return retval;
131 }
132 }
133 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
134
135 if (dscr_p)
136 *dscr_p = dscr;
137
138 return retval;
139 }
140
141 /**************************************************************************
142 Read core register with very few exec_opcode, fast but needs work_area.
143 This can cause problems with MMU active.
144 **************************************************************************/
145 static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
146 uint32_t * regfile)
147 {
148 int retval = ERROR_OK;
149 struct armv7a_common *armv7a = target_to_armv7a(target);
150 struct swjdp_common *swjdp = &armv7a->swjdp_info;
151
152 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
153 cortex_a8_dap_write_coreregister_u32(target, address, 0);
154 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
155 dap_ap_select(swjdp, swjdp_memoryap);
156 mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
157 dap_ap_select(swjdp, swjdp_debugap);
158
159 return retval;
160 }
161
162 static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
163 uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
164 {
165 int retval;
166 struct armv7a_common *armv7a = target_to_armv7a(target);
167 struct swjdp_common *swjdp = &armv7a->swjdp_info;
168 uint32_t dscr = 0;
169
170 /* MRC(...) to read coprocessor register into r0 */
171 cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2),
172 &dscr);
173
174 /* Move R0 to DTRTX */
175 cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
176 &dscr);
177
178 /* Read DCCTX */
179 retval = mem_ap_read_atomic_u32(swjdp,
180 armv7a->debug_base + CPUDBG_DTRTX, value);
181
182 return retval;
183 }
184
185 static int cortex_a8_write_cp(struct target *target, uint32_t value,
186 uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
187 {
188 int retval;
189 uint32_t dscr;
190 struct armv7a_common *armv7a = target_to_armv7a(target);
191 struct swjdp_common *swjdp = &armv7a->swjdp_info;
192
193 LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
194
195 /* Check that DCCRX is not full */
196 retval = mem_ap_read_atomic_u32(swjdp,
197 armv7a->debug_base + CPUDBG_DSCR, &dscr);
198 if (dscr & (1 << DSCR_DTR_RX_FULL))
199 {
200 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
201 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
202 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
203 &dscr);
204 }
205
206 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
207 retval = mem_ap_write_u32(swjdp,
208 armv7a->debug_base + CPUDBG_DTRRX, value);
209
210 /* Move DTRRX to r0 */
211 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
212
213 /* MCR(...) to write r0 to coprocessor */
214 return cortex_a8_exec_opcode(target,
215 ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2),
216 &dscr);
217 }
218
219 static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
220 uint32_t CRn, uint32_t CRm, uint32_t *value)
221 {
222 return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
223 }
224
225 static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
226 uint32_t CRn, uint32_t CRm, uint32_t value)
227 {
228 return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
229 }
230
231 static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
232 {
233 if (cpnum!=15)
234 {
235 LOG_ERROR("Only cp15 is supported");
236 return ERROR_FAIL;
237 }
238 return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
239 }
240
241 static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
242 {
243 if (cpnum!=15)
244 {
245 LOG_ERROR("Only cp15 is supported");
246 return ERROR_FAIL;
247 }
248 return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value);
249 }
250
251
252
253 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
254 uint32_t *value, int regnum)
255 {
256 int retval = ERROR_OK;
257 uint8_t reg = regnum&0xFF;
258 uint32_t dscr = 0;
259 struct armv7a_common *armv7a = target_to_armv7a(target);
260 struct swjdp_common *swjdp = &armv7a->swjdp_info;
261
262 if (reg > 17)
263 return retval;
264
265 if (reg < 15)
266 {
267 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
268 cortex_a8_exec_opcode(target,
269 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
270 &dscr);
271 }
272 else if (reg == 15)
273 {
274 /* "MOV r0, r15"; then move r0 to DCCTX */
275 cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
276 cortex_a8_exec_opcode(target,
277 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
278 &dscr);
279 }
280 else
281 {
282 /* "MRS r0, CPSR" or "MRS r0, SPSR"
283 * then move r0 to DCCTX
284 */
285 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
286 cortex_a8_exec_opcode(target,
287 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
288 &dscr);
289 }
290
291 /* Wait for DTRRXfull then read DTRRTX */
292 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
293 {
294 retval = mem_ap_read_atomic_u32(swjdp,
295 armv7a->debug_base + CPUDBG_DSCR, &dscr);
296 }
297
298 retval = mem_ap_read_atomic_u32(swjdp,
299 armv7a->debug_base + CPUDBG_DTRTX, value);
300 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
301
302 return retval;
303 }
304
305 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
306 uint32_t value, int regnum)
307 {
308 int retval = ERROR_OK;
309 uint8_t Rd = regnum&0xFF;
310 uint32_t dscr;
311 struct armv7a_common *armv7a = target_to_armv7a(target);
312 struct swjdp_common *swjdp = &armv7a->swjdp_info;
313
314 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
315
316 /* Check that DCCRX is not full */
317 retval = mem_ap_read_atomic_u32(swjdp,
318 armv7a->debug_base + CPUDBG_DSCR, &dscr);
319 if (dscr & (1 << DSCR_DTR_RX_FULL))
320 {
321 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
322 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
323 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
324 &dscr);
325 }
326
327 if (Rd > 17)
328 return retval;
329
330 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
331 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
332 retval = mem_ap_write_u32(swjdp,
333 armv7a->debug_base + CPUDBG_DTRRX, value);
334
335 if (Rd < 15)
336 {
337 /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
338 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
339 &dscr);
340 }
341 else if (Rd == 15)
342 {
343 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
344 * then "mov r15, r0"
345 */
346 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
347 &dscr);
348 cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
349 }
350 else
351 {
352 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
353 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
354 */
355 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
356 &dscr);
357 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
358 &dscr);
359
360 /* "Prefetch flush" after modifying execution status in CPSR */
361 if (Rd == 16)
362 cortex_a8_exec_opcode(target,
363 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
364 &dscr);
365 }
366
367 return retval;
368 }
369
370 /* Write to memory mapped registers directly with no cache or mmu handling */
371 static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
372 {
373 int retval;
374 struct armv7a_common *armv7a = target_to_armv7a(target);
375 struct swjdp_common *swjdp = &armv7a->swjdp_info;
376
377 retval = mem_ap_write_atomic_u32(swjdp, address, value);
378
379 return retval;
380 }
381
382 /*
383 * Cortex-A8 implementation of Debug Programmer's Model
384 *
385 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
386 * so there's no need to poll for it before executing an instruction.
387 *
388 * NOTE that in several of these cases the "stall" mode might be useful.
389 * It'd let us queue a few operations together... prepare/finish might
390 * be the places to enable/disable that mode.
391 */
392
393 static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
394 {
395 return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
396 }
397
398 static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
399 {
400 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
401 return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
402 a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
403 }
404
405 static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
406 uint32_t *dscr_p)
407 {
408 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
409 uint32_t dscr = 1 << DSCR_INSTR_COMP;
410 int retval;
411
412 if (dscr_p)
413 dscr = *dscr_p;
414
415 /* Wait for DTRRXfull */
416 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
417 retval = mem_ap_read_atomic_u32(swjdp,
418 a8->armv7a_common.debug_base + CPUDBG_DSCR,
419 &dscr);
420 }
421
422 retval = mem_ap_read_atomic_u32(swjdp,
423 a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
424 LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
425
426 if (dscr_p)
427 *dscr_p = dscr;
428
429 return retval;
430 }
431
432 static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
433 {
434 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
435 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
436 uint32_t dscr;
437 int retval;
438
439 /* set up invariant: INSTR_COMP is set after ever DPM operation */
440 do {
441 retval = mem_ap_read_atomic_u32(swjdp,
442 a8->armv7a_common.debug_base + CPUDBG_DSCR,
443 &dscr);
444 } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
445
446 /* this "should never happen" ... */
447 if (dscr & (1 << DSCR_DTR_RX_FULL)) {
448 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
449 /* Clear DCCRX */
450 retval = cortex_a8_exec_opcode(
451 a8->armv7a_common.armv4_5_common.target,
452 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
453 &dscr);
454 }
455
456 return retval;
457 }
458
459 static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
460 {
461 /* REVISIT what could be done here? */
462 return ERROR_OK;
463 }
464
465 static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
466 uint32_t opcode, uint32_t data)
467 {
468 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
469 int retval;
470 uint32_t dscr = 1 << DSCR_INSTR_COMP;
471
472 retval = cortex_a8_write_dcc(a8, data);
473
474 return cortex_a8_exec_opcode(
475 a8->armv7a_common.armv4_5_common.target,
476 opcode,
477 &dscr);
478 }
479
480 static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
481 uint32_t opcode, uint32_t data)
482 {
483 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
484 uint32_t dscr = 1 << DSCR_INSTR_COMP;
485 int retval;
486
487 retval = cortex_a8_write_dcc(a8, data);
488
489 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
490 retval = cortex_a8_exec_opcode(
491 a8->armv7a_common.armv4_5_common.target,
492 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
493 &dscr);
494
495 /* then the opcode, taking data from R0 */
496 retval = cortex_a8_exec_opcode(
497 a8->armv7a_common.armv4_5_common.target,
498 opcode,
499 &dscr);
500
501 return retval;
502 }
503
504 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
505 {
506 struct target *target = dpm->arm->target;
507 uint32_t dscr = 1 << DSCR_INSTR_COMP;
508
509 /* "Prefetch flush" after modifying execution status in CPSR */
510 return cortex_a8_exec_opcode(target,
511 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
512 &dscr);
513 }
514
515 static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
516 uint32_t opcode, uint32_t *data)
517 {
518 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
519 int retval;
520 uint32_t dscr = 1 << DSCR_INSTR_COMP;
521
522 /* the opcode, writing data to DCC */
523 retval = cortex_a8_exec_opcode(
524 a8->armv7a_common.armv4_5_common.target,
525 opcode,
526 &dscr);
527
528 return cortex_a8_read_dcc(a8, data, &dscr);
529 }
530
531
532 static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
533 uint32_t opcode, uint32_t *data)
534 {
535 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
536 uint32_t dscr = 1 << DSCR_INSTR_COMP;
537 int retval;
538
539 /* the opcode, writing data to R0 */
540 retval = cortex_a8_exec_opcode(
541 a8->armv7a_common.armv4_5_common.target,
542 opcode,
543 &dscr);
544
545 /* write R0 to DCC */
546 retval = cortex_a8_exec_opcode(
547 a8->armv7a_common.armv4_5_common.target,
548 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
549 &dscr);
550
551 return cortex_a8_read_dcc(a8, data, &dscr);
552 }
553
554 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
555 {
556 struct arm_dpm *dpm = &a8->armv7a_common.dpm;
557
558 dpm->arm = &a8->armv7a_common.armv4_5_common;
559 dpm->didr = didr;
560
561 dpm->prepare = cortex_a8_dpm_prepare;
562 dpm->finish = cortex_a8_dpm_finish;
563
564 dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
565 dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
566 dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
567
568 dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
569 dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
570
571 return arm_dpm_setup(dpm);
572 }
573
574
575 /*
576 * Cortex-A8 Run control
577 */
578
579 static int cortex_a8_poll(struct target *target)
580 {
581 int retval = ERROR_OK;
582 uint32_t dscr;
583 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
584 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
585 struct swjdp_common *swjdp = &armv7a->swjdp_info;
586 enum target_state prev_target_state = target->state;
587 uint8_t saved_apsel = dap_ap_get_select(swjdp);
588
589 dap_ap_select(swjdp, swjdp_debugap);
590 retval = mem_ap_read_atomic_u32(swjdp,
591 armv7a->debug_base + CPUDBG_DSCR, &dscr);
592 if (retval != ERROR_OK)
593 {
594 dap_ap_select(swjdp, saved_apsel);
595 return retval;
596 }
597 cortex_a8->cpudbg_dscr = dscr;
598
599 if ((dscr & 0x3) == 0x3)
600 {
601 if (prev_target_state != TARGET_HALTED)
602 {
603 /* We have a halting debug event */
604 LOG_DEBUG("Target halted");
605 target->state = TARGET_HALTED;
606 if ((prev_target_state == TARGET_RUNNING)
607 || (prev_target_state == TARGET_RESET))
608 {
609 retval = cortex_a8_debug_entry(target);
610 if (retval != ERROR_OK)
611 return retval;
612
613 target_call_event_callbacks(target,
614 TARGET_EVENT_HALTED);
615 }
616 if (prev_target_state == TARGET_DEBUG_RUNNING)
617 {
618 LOG_DEBUG(" ");
619
620 retval = cortex_a8_debug_entry(target);
621 if (retval != ERROR_OK)
622 return retval;
623
624 target_call_event_callbacks(target,
625 TARGET_EVENT_DEBUG_HALTED);
626 }
627 }
628 }
629 else if ((dscr & 0x3) == 0x2)
630 {
631 target->state = TARGET_RUNNING;
632 }
633 else
634 {
635 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
636 target->state = TARGET_UNKNOWN;
637 }
638
639 dap_ap_select(swjdp, saved_apsel);
640
641 return retval;
642 }
643
644 static int cortex_a8_halt(struct target *target)
645 {
646 int retval = ERROR_OK;
647 uint32_t dscr;
648 struct armv7a_common *armv7a = target_to_armv7a(target);
649 struct swjdp_common *swjdp = &armv7a->swjdp_info;
650 uint8_t saved_apsel = dap_ap_get_select(swjdp);
651 dap_ap_select(swjdp, swjdp_debugap);
652
653 /*
654 * Tell the core to be halted by writing DRCR with 0x1
655 * and then wait for the core to be halted.
656 */
657 retval = mem_ap_write_atomic_u32(swjdp,
658 armv7a->debug_base + CPUDBG_DRCR, 0x1);
659
660 /*
661 * enter halting debug mode
662 */
663 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
664 retval = mem_ap_write_atomic_u32(swjdp,
665 armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
666
667 if (retval != ERROR_OK)
668 goto out;
669
670 do {
671 mem_ap_read_atomic_u32(swjdp,
672 armv7a->debug_base + CPUDBG_DSCR, &dscr);
673 } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
674
675 target->debug_reason = DBG_REASON_DBGRQ;
676
677 out:
678 dap_ap_select(swjdp, saved_apsel);
679 return retval;
680 }
681
682 static int cortex_a8_resume(struct target *target, int current,
683 uint32_t address, int handle_breakpoints, int debug_execution)
684 {
685 struct armv7a_common *armv7a = target_to_armv7a(target);
686 struct arm *armv4_5 = &armv7a->armv4_5_common;
687 struct swjdp_common *swjdp = &armv7a->swjdp_info;
688
689 // struct breakpoint *breakpoint = NULL;
690 uint32_t resume_pc, dscr;
691
692 uint8_t saved_apsel = dap_ap_get_select(swjdp);
693 dap_ap_select(swjdp, swjdp_debugap);
694
695 if (!debug_execution)
696 {
697 target_free_all_working_areas(target);
698 // cortex_m3_enable_breakpoints(target);
699 // cortex_m3_enable_watchpoints(target);
700 }
701
702 #if 0
703 if (debug_execution)
704 {
705 /* Disable interrupts */
706 /* We disable interrupts in the PRIMASK register instead of
707 * masking with C_MASKINTS,
708 * This is probably the same issue as Cortex-M3 Errata 377493:
709 * C_MASKINTS in parallel with disabled interrupts can cause
710 * local faults to not be taken. */
711 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
712 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
713 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
714
715 /* Make sure we are in Thumb mode */
716 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
717 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
718 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
719 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
720 }
721 #endif
722
723 /* current = 1: continue on current pc, otherwise continue at <address> */
724 resume_pc = buf_get_u32(
725 armv4_5->core_cache->reg_list[15].value,
726 0, 32);
727 if (!current)
728 resume_pc = address;
729
730 /* Make sure that the Armv7 gdb thumb fixups does not
731 * kill the return address
732 */
733 switch (armv4_5->core_state)
734 {
735 case ARMV4_5_STATE_ARM:
736 resume_pc &= 0xFFFFFFFC;
737 break;
738 case ARMV4_5_STATE_THUMB:
739 case ARM_STATE_THUMB_EE:
740 /* When the return address is loaded into PC
741 * bit 0 must be 1 to stay in Thumb state
742 */
743 resume_pc |= 0x1;
744 break;
745 case ARMV4_5_STATE_JAZELLE:
746 LOG_ERROR("How do I resume into Jazelle state??");
747 return ERROR_FAIL;
748 }
749 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
750 buf_set_u32(armv4_5->core_cache->reg_list[15].value,
751 0, 32, resume_pc);
752 armv4_5->core_cache->reg_list[15].dirty = 1;
753 armv4_5->core_cache->reg_list[15].valid = 1;
754
755 cortex_a8_restore_context(target);
756
757 #if 0
758 /* the front-end may request us not to handle breakpoints */
759 if (handle_breakpoints)
760 {
761 /* Single step past breakpoint at current address */
762 if ((breakpoint = breakpoint_find(target, resume_pc)))
763 {
764 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
765 cortex_m3_unset_breakpoint(target, breakpoint);
766 cortex_m3_single_step_core(target);
767 cortex_m3_set_breakpoint(target, breakpoint);
768 }
769 }
770
771 #endif
772 /* Restart core and wait for it to be started */
773 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
774
775 do {
776 mem_ap_read_atomic_u32(swjdp,
777 armv7a->debug_base + CPUDBG_DSCR, &dscr);
778 } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
779
780 target->debug_reason = DBG_REASON_NOTHALTED;
781 target->state = TARGET_RUNNING;
782
783 /* registers are now invalid */
784 register_cache_invalidate(armv4_5->core_cache);
785
786 if (!debug_execution)
787 {
788 target->state = TARGET_RUNNING;
789 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
790 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
791 }
792 else
793 {
794 target->state = TARGET_DEBUG_RUNNING;
795 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
796 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
797 }
798
799 dap_ap_select(swjdp, saved_apsel);
800
801 return ERROR_OK;
802 }
803
804 static int cortex_a8_debug_entry(struct target *target)
805 {
806 int i;
807 uint32_t regfile[16], pc, cpsr, dscr;
808 int retval = ERROR_OK;
809 struct working_area *regfile_working_area = NULL;
810 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
811 struct armv7a_common *armv7a = target_to_armv7a(target);
812 struct arm *armv4_5 = &armv7a->armv4_5_common;
813 struct swjdp_common *swjdp = &armv7a->swjdp_info;
814 struct reg *reg;
815
816 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
817
818 /* Enable the ITR execution once we are in debug mode */
819 mem_ap_read_atomic_u32(swjdp,
820 armv7a->debug_base + CPUDBG_DSCR, &dscr);
821
822 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
823 * imprecise data aborts get discarded by issuing a Data
824 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
825 */
826
827 dscr |= (1 << DSCR_EXT_INT_EN);
828 retval = mem_ap_write_atomic_u32(swjdp,
829 armv7a->debug_base + CPUDBG_DSCR, dscr);
830
831 /* Examine debug reason */
832 switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
833 {
834 case 0: /* DRCR[0] write */
835 case 4: /* EDBGRQ */
836 target->debug_reason = DBG_REASON_DBGRQ;
837 break;
838 case 1: /* HW breakpoint */
839 case 3: /* SW BKPT */
840 case 5: /* vector catch */
841 target->debug_reason = DBG_REASON_BREAKPOINT;
842 break;
843 case 10: /* precise watchpoint */
844 target->debug_reason = DBG_REASON_WATCHPOINT;
845 /* REVISIT could collect WFAR later, to see just
846 * which instruction triggered the watchpoint.
847 */
848 break;
849 default:
850 target->debug_reason = DBG_REASON_UNDEFINED;
851 break;
852 }
853
854 /* REVISIT fast_reg_read is never set ... */
855
856 /* Examine target state and mode */
857 if (cortex_a8->fast_reg_read)
858 target_alloc_working_area(target, 64, &regfile_working_area);
859
860 /* First load register acessible through core debug port*/
861 if (!regfile_working_area)
862 {
863 retval = arm_dpm_read_current_registers(&armv7a->dpm);
864 }
865 else
866 {
867 dap_ap_select(swjdp, swjdp_memoryap);
868 cortex_a8_read_regs_through_mem(target,
869 regfile_working_area->address, regfile);
870 dap_ap_select(swjdp, swjdp_memoryap);
871 target_free_working_area(target, regfile_working_area);
872
873 /* read Current PSR */
874 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
875 pc = regfile[15];
876 dap_ap_select(swjdp, swjdp_debugap);
877 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
878
879 arm_set_cpsr(armv4_5, cpsr);
880
881 /* update cache */
882 for (i = 0; i <= ARM_PC; i++)
883 {
884 reg = arm_reg_current(armv4_5, i);
885
886 buf_set_u32(reg->value, 0, 32, regfile[i]);
887 reg->valid = 1;
888 reg->dirty = 0;
889 }
890
891 /* Fixup PC Resume Address */
892 if (cpsr & (1 << 5))
893 {
894 // T bit set for Thumb or ThumbEE state
895 regfile[ARM_PC] -= 4;
896 }
897 else
898 {
899 // ARM state
900 regfile[ARM_PC] -= 8;
901 }
902
903 reg = armv4_5->core_cache->reg_list + 15;
904 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
905 reg->dirty = reg->valid;
906 }
907
908 #if 0
909 /* TODO, Move this */
910 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
911 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
912 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
913
914 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
915 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
916
917 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
918 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
919 #endif
920
921 /* Are we in an exception handler */
922 // armv4_5->exception_number = 0;
923 if (armv7a->post_debug_entry)
924 armv7a->post_debug_entry(target);
925
926
927
928 return retval;
929
930 }
931
932 static void cortex_a8_post_debug_entry(struct target *target)
933 {
934 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
935 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
936
937 // cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
938 /* examine cp15 control reg */
939 armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
940 jtag_execute_queue();
941 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
942
943 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
944 {
945 uint32_t cache_type_reg;
946 /* identify caches */
947 armv7a->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
948 jtag_execute_queue();
949 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
950 armv4_5_identify_cache(cache_type_reg,
951 &armv7a->armv4_5_mmu.armv4_5_cache);
952 }
953
954 armv7a->armv4_5_mmu.mmu_enabled =
955 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
956 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
957 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
958 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
959 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
960
961
962 }
963
964 static int cortex_a8_step(struct target *target, int current, uint32_t address,
965 int handle_breakpoints)
966 {
967 struct armv7a_common *armv7a = target_to_armv7a(target);
968 struct arm *armv4_5 = &armv7a->armv4_5_common;
969 struct breakpoint *breakpoint = NULL;
970 struct breakpoint stepbreakpoint;
971 struct reg *r;
972
973 int timeout = 100;
974
975 if (target->state != TARGET_HALTED)
976 {
977 LOG_WARNING("target not halted");
978 return ERROR_TARGET_NOT_HALTED;
979 }
980
981 /* current = 1: continue on current pc, otherwise continue at <address> */
982 r = armv4_5->core_cache->reg_list + 15;
983 if (!current)
984 {
985 buf_set_u32(r->value, 0, 32, address);
986 }
987 else
988 {
989 address = buf_get_u32(r->value, 0, 32);
990 }
991
992 /* The front-end may request us not to handle breakpoints.
993 * But since Cortex-A8 uses breakpoint for single step,
994 * we MUST handle breakpoints.
995 */
996 handle_breakpoints = 1;
997 if (handle_breakpoints) {
998 breakpoint = breakpoint_find(target, address);
999 if (breakpoint)
1000 cortex_a8_unset_breakpoint(target, breakpoint);
1001 }
1002
1003 /* Setup single step breakpoint */
1004 stepbreakpoint.address = address;
1005 stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1006 ? 2 : 4;
1007 stepbreakpoint.type = BKPT_HARD;
1008 stepbreakpoint.set = 0;
1009
1010 /* Break on IVA mismatch */
1011 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
1012
1013 target->debug_reason = DBG_REASON_SINGLESTEP;
1014
1015 cortex_a8_resume(target, 1, address, 0, 0);
1016
1017 while (target->state != TARGET_HALTED)
1018 {
1019 cortex_a8_poll(target);
1020 if (--timeout == 0)
1021 {
1022 LOG_WARNING("timeout waiting for target halt");
1023 break;
1024 }
1025 }
1026
1027 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
1028 if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
1029
1030 if (breakpoint)
1031 cortex_a8_set_breakpoint(target, breakpoint, 0);
1032
1033 if (target->state != TARGET_HALTED)
1034 LOG_DEBUG("target stepped");
1035
1036 return ERROR_OK;
1037 }
1038
1039 static int cortex_a8_restore_context(struct target *target)
1040 {
1041 struct armv7a_common *armv7a = target_to_armv7a(target);
1042
1043 LOG_DEBUG(" ");
1044
1045 if (armv7a->pre_restore_context)
1046 armv7a->pre_restore_context(target);
1047
1048 arm_dpm_write_dirty_registers(&armv7a->dpm);
1049
1050 if (armv7a->post_restore_context)
1051 armv7a->post_restore_context(target);
1052
1053 return ERROR_OK;
1054 }
1055
1056
1057 /*
1058 * Cortex-A8 Breakpoint and watchpoint fuctions
1059 */
1060
1061 /* Setup hardware Breakpoint Register Pair */
1062 static int cortex_a8_set_breakpoint(struct target *target,
1063 struct breakpoint *breakpoint, uint8_t matchmode)
1064 {
1065 int retval;
1066 int brp_i=0;
1067 uint32_t control;
1068 uint8_t byte_addr_select = 0x0F;
1069 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1070 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1071 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1072
1073 if (breakpoint->set)
1074 {
1075 LOG_WARNING("breakpoint already set");
1076 return ERROR_OK;
1077 }
1078
1079 if (breakpoint->type == BKPT_HARD)
1080 {
1081 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
1082 brp_i++ ;
1083 if (brp_i >= cortex_a8->brp_num)
1084 {
1085 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1086 return ERROR_FAIL;
1087 }
1088 breakpoint->set = brp_i + 1;
1089 if (breakpoint->length == 2)
1090 {
1091 byte_addr_select = (3 << (breakpoint->address & 0x02));
1092 }
1093 control = ((matchmode & 0x7) << 20)
1094 | (byte_addr_select << 5)
1095 | (3 << 1) | 1;
1096 brp_list[brp_i].used = 1;
1097 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1098 brp_list[brp_i].control = control;
1099 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1100 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1101 brp_list[brp_i].value);
1102 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1103 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1104 brp_list[brp_i].control);
1105 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1106 brp_list[brp_i].control,
1107 brp_list[brp_i].value);
1108 }
1109 else if (breakpoint->type == BKPT_SOFT)
1110 {
1111 uint8_t code[4];
1112 if (breakpoint->length == 2)
1113 {
1114 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1115 }
1116 else
1117 {
1118 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1119 }
1120 retval = target->type->read_memory(target,
1121 breakpoint->address & 0xFFFFFFFE,
1122 breakpoint->length, 1,
1123 breakpoint->orig_instr);
1124 if (retval != ERROR_OK)
1125 return retval;
1126 retval = target->type->write_memory(target,
1127 breakpoint->address & 0xFFFFFFFE,
1128 breakpoint->length, 1, code);
1129 if (retval != ERROR_OK)
1130 return retval;
1131 breakpoint->set = 0x11; /* Any nice value but 0 */
1132 }
1133
1134 return ERROR_OK;
1135 }
1136
1137 static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1138 {
1139 int retval;
1140 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1141 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1142 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1143
1144 if (!breakpoint->set)
1145 {
1146 LOG_WARNING("breakpoint not set");
1147 return ERROR_OK;
1148 }
1149
1150 if (breakpoint->type == BKPT_HARD)
1151 {
1152 int brp_i = breakpoint->set - 1;
1153 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1154 {
1155 LOG_DEBUG("Invalid BRP number in breakpoint");
1156 return ERROR_OK;
1157 }
1158 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1159 brp_list[brp_i].control, brp_list[brp_i].value);
1160 brp_list[brp_i].used = 0;
1161 brp_list[brp_i].value = 0;
1162 brp_list[brp_i].control = 0;
1163 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1164 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1165 brp_list[brp_i].control);
1166 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1167 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1168 brp_list[brp_i].value);
1169 }
1170 else
1171 {
1172 /* restore original instruction (kept in target endianness) */
1173 if (breakpoint->length == 4)
1174 {
1175 retval = target->type->write_memory(target,
1176 breakpoint->address & 0xFFFFFFFE,
1177 4, 1, breakpoint->orig_instr);
1178 if (retval != ERROR_OK)
1179 return retval;
1180 }
1181 else
1182 {
1183 retval = target->type->write_memory(target,
1184 breakpoint->address & 0xFFFFFFFE,
1185 2, 1, breakpoint->orig_instr);
1186 if (retval != ERROR_OK)
1187 return retval;
1188 }
1189 }
1190 breakpoint->set = 0;
1191
1192 return ERROR_OK;
1193 }
1194
1195 static int cortex_a8_add_breakpoint(struct target *target,
1196 struct breakpoint *breakpoint)
1197 {
1198 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1199
1200 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1201 {
1202 LOG_INFO("no hardware breakpoint available");
1203 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1204 }
1205
1206 if (breakpoint->type == BKPT_HARD)
1207 cortex_a8->brp_num_available--;
1208 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1209
1210 return ERROR_OK;
1211 }
1212
1213 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1214 {
1215 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1216
1217 #if 0
1218 /* It is perfectly possible to remove brakpoints while the taget is running */
1219 if (target->state != TARGET_HALTED)
1220 {
1221 LOG_WARNING("target not halted");
1222 return ERROR_TARGET_NOT_HALTED;
1223 }
1224 #endif
1225
1226 if (breakpoint->set)
1227 {
1228 cortex_a8_unset_breakpoint(target, breakpoint);
1229 if (breakpoint->type == BKPT_HARD)
1230 cortex_a8->brp_num_available++ ;
1231 }
1232
1233
1234 return ERROR_OK;
1235 }
1236
1237
1238
1239 /*
1240 * Cortex-A8 Reset fuctions
1241 */
1242
1243 static int cortex_a8_assert_reset(struct target *target)
1244 {
1245 struct armv7a_common *armv7a = target_to_armv7a(target);
1246
1247 LOG_DEBUG(" ");
1248
1249 /* FIXME when halt is requested, make it work somehow... */
1250
1251 /* Issue some kind of warm reset. */
1252 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1253 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1254 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1255 /* REVISIT handle "pulls" cases, if there's
1256 * hardware that needs them to work.
1257 */
1258 jtag_add_reset(0, 1);
1259 } else {
1260 LOG_ERROR("%s: how to reset?", target_name(target));
1261 return ERROR_FAIL;
1262 }
1263
1264 /* registers are now invalid */
1265 register_cache_invalidate(armv7a->armv4_5_common.core_cache);
1266
1267 target->state = TARGET_RESET;
1268
1269 return ERROR_OK;
1270 }
1271
1272 static int cortex_a8_deassert_reset(struct target *target)
1273 {
1274 int retval;
1275
1276 LOG_DEBUG(" ");
1277
1278 /* be certain SRST is off */
1279 jtag_add_reset(0, 0);
1280
1281 retval = cortex_a8_poll(target);
1282
1283 if (target->reset_halt) {
1284 if (target->state != TARGET_HALTED) {
1285 LOG_WARNING("%s: ran after reset and before halt ...",
1286 target_name(target));
1287 if ((retval = target_halt(target)) != ERROR_OK)
1288 return retval;
1289 }
1290 }
1291
1292 return ERROR_OK;
1293 }
1294
1295 /*
1296 * Cortex-A8 Memory access
1297 *
1298 * This is same Cortex M3 but we must also use the correct
1299 * ap number for every access.
1300 */
1301
1302 static int cortex_a8_read_memory(struct target *target, uint32_t address,
1303 uint32_t size, uint32_t count, uint8_t *buffer)
1304 {
1305 struct armv7a_common *armv7a = target_to_armv7a(target);
1306 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1307 int retval = ERROR_INVALID_ARGUMENTS;
1308
1309 /* cortex_a8 handles unaligned memory access */
1310
1311 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1312
1313 if (count && buffer) {
1314 switch (size) {
1315 case 4:
1316 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1317 break;
1318 case 2:
1319 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1320 break;
1321 case 1:
1322 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1323 break;
1324 }
1325 }
1326
1327 return retval;
1328 }
1329
1330 static int cortex_a8_write_memory(struct target *target, uint32_t address,
1331 uint32_t size, uint32_t count, uint8_t *buffer)
1332 {
1333 struct armv7a_common *armv7a = target_to_armv7a(target);
1334 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1335 int retval = ERROR_INVALID_ARGUMENTS;
1336
1337 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1338
1339 if (count && buffer) {
1340 switch (size) {
1341 case 4:
1342 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1343 break;
1344 case 2:
1345 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1346 break;
1347 case 1:
1348 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1349 break;
1350 }
1351 }
1352
1353 if (retval == ERROR_OK && target->state == TARGET_HALTED)
1354 {
1355 /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
1356 /* invalidate I-Cache */
1357 if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
1358 {
1359 /* Invalidate ICache single entry with MVA, repeat this for all cache
1360 lines in the address range, Cortex-A8 has fixed 64 byte line length */
1361 /* Invalidate Cache single entry with MVA to PoU */
1362 for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
1363 armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
1364 }
1365 /* invalidate D-Cache */
1366 if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
1367 {
1368 /* Invalidate Cache single entry with MVA to PoC */
1369 for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
1370 armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
1371 }
1372 }
1373
1374 return retval;
1375 }
1376
1377 static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
1378 uint32_t count, uint8_t *buffer)
1379 {
1380 return cortex_a8_write_memory(target, address, 4, count, buffer);
1381 }
1382
1383
1384 static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1385 {
1386 #if 0
1387 u16 dcrdr;
1388
1389 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1390 *ctrl = (uint8_t)dcrdr;
1391 *value = (uint8_t)(dcrdr >> 8);
1392
1393 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1394
1395 /* write ack back to software dcc register
1396 * signify we have read data */
1397 if (dcrdr & (1 << 0))
1398 {
1399 dcrdr = 0;
1400 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1401 }
1402 #endif
1403 return ERROR_OK;
1404 }
1405
1406
1407 static int cortex_a8_handle_target_request(void *priv)
1408 {
1409 struct target *target = priv;
1410 struct armv7a_common *armv7a = target_to_armv7a(target);
1411 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1412
1413 if (!target_was_examined(target))
1414 return ERROR_OK;
1415 if (!target->dbg_msg_enabled)
1416 return ERROR_OK;
1417
1418 if (target->state == TARGET_RUNNING)
1419 {
1420 uint8_t data = 0;
1421 uint8_t ctrl = 0;
1422
1423 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1424
1425 /* check if we have data */
1426 if (ctrl & (1 << 0))
1427 {
1428 uint32_t request;
1429
1430 /* we assume target is quick enough */
1431 request = data;
1432 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1433 request |= (data << 8);
1434 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1435 request |= (data << 16);
1436 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1437 request |= (data << 24);
1438 target_request(target, request);
1439 }
1440 }
1441
1442 return ERROR_OK;
1443 }
1444
1445 /*
1446 * Cortex-A8 target information and configuration
1447 */
1448
1449 static int cortex_a8_examine_first(struct target *target)
1450 {
1451 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1452 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1453 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1454 int i;
1455 int retval = ERROR_OK;
1456 uint32_t didr, ctypr, ttypr, cpuid;
1457
1458 LOG_DEBUG("TODO");
1459
1460 /* Here we shall insert a proper ROM Table scan */
1461 armv7a->debug_base = OMAP3530_DEBUG_BASE;
1462
1463 /* We do one extra read to ensure DAP is configured,
1464 * we call ahbap_debugport_init(swjdp) instead
1465 */
1466 ahbap_debugport_init(swjdp);
1467 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
1468 if ((retval = mem_ap_read_atomic_u32(swjdp,
1469 armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1470 {
1471 LOG_DEBUG("Examine failed");
1472 return retval;
1473 }
1474
1475 if ((retval = mem_ap_read_atomic_u32(swjdp,
1476 armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1477 {
1478 LOG_DEBUG("Examine failed");
1479 return retval;
1480 }
1481
1482 if ((retval = mem_ap_read_atomic_u32(swjdp,
1483 armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1484 {
1485 LOG_DEBUG("Examine failed");
1486 return retval;
1487 }
1488
1489 if ((retval = mem_ap_read_atomic_u32(swjdp,
1490 armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
1491 {
1492 LOG_DEBUG("Examine failed");
1493 return retval;
1494 }
1495
1496 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1497 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1498 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1499 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1500
1501 cortex_a8_dpm_setup(cortex_a8, didr);
1502
1503 /* Setup Breakpoint Register Pairs */
1504 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1505 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1506 cortex_a8->brp_num_available = cortex_a8->brp_num;
1507 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
1508 // cortex_a8->brb_enabled = ????;
1509 for (i = 0; i < cortex_a8->brp_num; i++)
1510 {
1511 cortex_a8->brp_list[i].used = 0;
1512 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1513 cortex_a8->brp_list[i].type = BRP_NORMAL;
1514 else
1515 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1516 cortex_a8->brp_list[i].value = 0;
1517 cortex_a8->brp_list[i].control = 0;
1518 cortex_a8->brp_list[i].BRPn = i;
1519 }
1520
1521 /* Setup Watchpoint Register Pairs */
1522 cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
1523 cortex_a8->wrp_num_available = cortex_a8->wrp_num;
1524 cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
1525 for (i = 0; i < cortex_a8->wrp_num; i++)
1526 {
1527 cortex_a8->wrp_list[i].used = 0;
1528 cortex_a8->wrp_list[i].type = 0;
1529 cortex_a8->wrp_list[i].value = 0;
1530 cortex_a8->wrp_list[i].control = 0;
1531 cortex_a8->wrp_list[i].WRPn = i;
1532 }
1533 LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
1534 cortex_a8->brp_num , cortex_a8->wrp_num);
1535
1536 target_set_examined(target);
1537 return ERROR_OK;
1538 }
1539
1540 static int cortex_a8_examine(struct target *target)
1541 {
1542 int retval = ERROR_OK;
1543
1544 /* don't re-probe hardware after each reset */
1545 if (!target_was_examined(target))
1546 retval = cortex_a8_examine_first(target);
1547
1548 /* Configure core debug access */
1549 if (retval == ERROR_OK)
1550 retval = cortex_a8_init_debug_access(target);
1551
1552 return retval;
1553 }
1554
1555 /*
1556 * Cortex-A8 target creation and initialization
1557 */
1558
1559 static int cortex_a8_init_target(struct command_context *cmd_ctx,
1560 struct target *target)
1561 {
1562 /* examine_first() does a bunch of this */
1563 return ERROR_OK;
1564 }
1565
1566 static int cortex_a8_init_arch_info(struct target *target,
1567 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
1568 {
1569 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1570 struct arm *armv4_5 = &armv7a->armv4_5_common;
1571 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1572
1573 /* Setup struct cortex_a8_common */
1574 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1575 armv4_5->arch_info = armv7a;
1576
1577 /* prepare JTAG information for the new target */
1578 cortex_a8->jtag_info.tap = tap;
1579 cortex_a8->jtag_info.scann_size = 4;
1580
1581 swjdp->dp_select_value = -1;
1582 swjdp->ap_csw_value = -1;
1583 swjdp->ap_tar_value = -1;
1584 swjdp->jtag_info = &cortex_a8->jtag_info;
1585 swjdp->memaccess_tck = 80;
1586
1587 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1588 swjdp->tar_autoincr_block = (1 << 10);
1589
1590 cortex_a8->fast_reg_read = 0;
1591
1592
1593 /* register arch-specific functions */
1594 armv7a->examine_debug_reason = NULL;
1595
1596 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1597
1598 armv7a->pre_restore_context = NULL;
1599 armv7a->post_restore_context = NULL;
1600 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1601 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1602 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1603 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1604 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1605 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1606 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1607 armv7a->armv4_5_mmu.mmu_enabled = 0;
1608 armv7a->read_cp15 = cortex_a8_read_cp15;
1609 armv7a->write_cp15 = cortex_a8_write_cp15;
1610
1611
1612 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1613
1614 /* REVISIT v7a setup should be in a v7a-specific routine */
1615 armv4_5_init_arch_info(target, armv4_5);
1616 armv7a->common_magic = ARMV7_COMMON_MAGIC;
1617
1618 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1619
1620 return ERROR_OK;
1621 }
1622
1623 static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
1624 {
1625 struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
1626
1627 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1628
1629 return ERROR_OK;
1630 }
1631
1632 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
1633 {
1634 struct target *target = get_current_target(CMD_CTX);
1635 struct armv7a_common *armv7a = target_to_armv7a(target);
1636
1637 return armv4_5_handle_cache_info_command(CMD_CTX,
1638 &armv7a->armv4_5_mmu.armv4_5_cache);
1639 }
1640
1641
1642 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
1643 {
1644 struct target *target = get_current_target(CMD_CTX);
1645
1646 cortex_a8_init_debug_access(target);
1647
1648 return ERROR_OK;
1649 }
1650
1651 static const struct command_registration cortex_a8_exec_command_handlers[] = {
1652 {
1653 .name = "cache_info",
1654 .handler = &cortex_a8_handle_cache_info_command,
1655 .mode = COMMAND_EXEC,
1656 .help = "display information about target caches",
1657 },
1658 {
1659 .name = "dbginit",
1660 .handler = &cortex_a8_handle_dbginit_command,
1661 .mode = COMMAND_EXEC,
1662 .help = "Initialize core debug",
1663 },
1664 COMMAND_REGISTRATION_DONE
1665 };
1666 static const struct command_registration cortex_a8_command_handlers[] = {
1667 {
1668 .chain = arm_command_handlers,
1669 },
1670 {
1671 .chain = armv7a_command_handlers,
1672 },
1673 {
1674 .name = "cortex_a8",
1675 .mode = COMMAND_ANY,
1676 .help = "Cortex-A8 command group",
1677 .chain = cortex_a8_exec_command_handlers,
1678 },
1679 COMMAND_REGISTRATION_DONE
1680 };
1681
1682 struct target_type cortexa8_target = {
1683 .name = "cortex_a8",
1684
1685 .poll = cortex_a8_poll,
1686 .arch_state = armv7a_arch_state,
1687
1688 .target_request_data = NULL,
1689
1690 .halt = cortex_a8_halt,
1691 .resume = cortex_a8_resume,
1692 .step = cortex_a8_step,
1693
1694 .assert_reset = cortex_a8_assert_reset,
1695 .deassert_reset = cortex_a8_deassert_reset,
1696 .soft_reset_halt = NULL,
1697
1698 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1699
1700 .read_memory = cortex_a8_read_memory,
1701 .write_memory = cortex_a8_write_memory,
1702 .bulk_write_memory = cortex_a8_bulk_write_memory,
1703
1704 .checksum_memory = arm_checksum_memory,
1705 .blank_check_memory = arm_blank_check_memory,
1706
1707 .run_algorithm = armv4_5_run_algorithm,
1708
1709 .add_breakpoint = cortex_a8_add_breakpoint,
1710 .remove_breakpoint = cortex_a8_remove_breakpoint,
1711 .add_watchpoint = NULL,
1712 .remove_watchpoint = NULL,
1713
1714 .commands = cortex_a8_command_handlers,
1715 .target_create = cortex_a8_target_create,
1716 .init_target = cortex_a8_init_target,
1717 .examine = cortex_a8_examine,
1718 .mrc = cortex_a8_mrc,
1719 .mcr = cortex_a8_mcr,
1720 };
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