src/target/avr32_jtag.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com>       *
   5  ***************************************************************************/
   6
   7 #ifndef OPENOCD_TARGET_AVR32_JTAG_H
   8 #define OPENOCD_TARGET_AVR32_JTAG_H
   9
  10 #define AVR32NUMCOREREGS        17
  11
  12 /* tap instructions */
  13 #define AVR32_INST_IDCODE               0x01
  14 #define AVR32_INST_NEXUS_ACCESS 0x10
  15 #define AVR32_INST_MW_ACCESS    0x11
  16 #define AVR32_INST_MB_ACCESS    0x12
  17
  18 #define SLAVE_OCD                               0x01
  19 #define SLAVE_HSB_CACHED                0x04
  20 #define SLAVE_HSB_UNCACHED              0x05
  21
  22 /*
  23  * Registers
  24  */
  25
  26 #define AVR32_OCDREG_DID                0x00
  27 #define AVR32_OCDREG_DC                 0x02
  28 #define         OCDREG_DC_SS                    (1 <<  8)
  29 #define         OCDREG_DC_DBR                   (1 << 12)
  30 #define         OCDREG_DC_DBE                   (1 << 13)
  31 #define         OCDREG_DC_SQA                   (1 << 22)
  32 #define         OCDREG_DC_RES                   (1 << 30)
  33 #define         OCDREG_DC_ABORT                 (1 << 31)
  34 #define AVR32_OCDREG_DS                 0x04
  35 #define         OCDREG_DS_SSS                   (1 <<  0)
  36 #define         OCDREG_DS_SWB                   (1 <<  1)
  37 #define         OCDREG_DS_HWB                   (1 <<  2)
  38 #define         OCDREG_DS_STP                   (1 <<  4)
  39 #define         OCDREG_DS_DBS                   (1 <<  5)
  40 #define         OCDREG_DS_BP_SHIFT              8
  41 #define         OCDREG_DS_BP_MASK               0xff
  42 #define         OCDREG_DS_INC                   (1 << 24)
  43 #define         OCDREG_DS_BOZ                   (1 << 25)
  44 #define         OCDREG_DS_DBA                   (1 << 26)
  45 #define         OCDREG_DS_EXB                   (1 << 27)
  46 #define         OCDREG_DS_NTBF                  (1 << 28)
  47
  48 #define AVR32_OCDREG_DINST              0x41
  49 #define AVR32_OCDREG_DPC                0x42
  50 #define AVR32_OCDREG_DCCPU              0x44
  51 #define AVR32_OCDREG_DCEMU              0x45
  52 #define AVR32_OCDREG_DCSR               0x46
  53 #define         OCDREG_DCSR_CPUD                (1 <<  0)
  54 #define         OCDREG_DCSR_EMUD                (1 <<  1)
  55
  56 /*
  57  * Direction bit
  58  */
  59 #define MODE_WRITE                              0x00
  60 #define MODE_READ                               0x01
  61
  62 /*
  63  * Some instructions
  64  */
  65
  66 #define RETD                                    0xd703d623
  67 #define MTDR(dreg, reg)                 (0xe7b00044 | ((reg) << 16) | dreg)
  68 #define MFDR(reg, dreg)                 (0xe5b00044 | ((reg) << 16) | dreg)
  69 #define MTSR(sysreg, reg)               (0xe3b00002 | ((reg) << 16) | sysreg)
  70 #define MFSR(reg, sysreg)               (0xe1b00002 | ((reg) << 16) | sysreg)
  71
  72 struct avr32_jtag {
  73         struct jtag_tap *tap;
  74         uint32_t dpc; /* Debug PC value */
  75 };
  76
  77 int avr32_jtag_nexus_read(struct avr32_jtag *jtag_info,
  78                 uint32_t addr, uint32_t *value);
  79 int avr32_jtag_nexus_write(struct avr32_jtag *jtag_info,
  80                 uint32_t addr, uint32_t value);
  81
  82 int avr32_jtag_mwa_read(struct avr32_jtag *jtag_info, int slave,
  83                 uint32_t addr, uint32_t *value);
  84 int avr32_jtag_mwa_write(struct avr32_jtag *jtag_info, int slave,
  85                 uint32_t addr, uint32_t value);
  86
  87 int avr32_ocd_setbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
  88 int avr32_ocd_clearbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
  89
  90 int avr32_jtag_exec(struct avr32_jtag *jtag_info, uint32_t inst);
  91
  92 #endif /* OPENOCD_TARGET_AVR32_JTAG_H */