src/jtag/swd.h

   1 /***************************************************************************
   2  *   Copyright (C) 2009-2010 by David Brownell                             *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef SWD_H
  21 #define SWD_H
  22
  23 #include <target/arm_adi_v5.h>
  24
  25 /* Bits in SWD command packets, written from host to target
  26  * first bit on the wire is START
  27  */
  28 #define SWD_CMD_START   (1 << 0)        /* always set */
  29 #define SWD_CMD_APnDP   (1 << 1)        /* set only for AP access */
  30 #define SWD_CMD_RnW     (1 << 2)                /* set only for read access */
  31 #define SWD_CMD_A32     (3 << 3)                /* bits A[3:2] of register addr */
  32 #define SWD_CMD_PARITY  (1 << 5)        /* parity of APnDP|RnW|A32 */
  33 #define SWD_CMD_STOP    (0 << 6)        /* always clear for synch SWD */
  34 #define SWD_CMD_PARK    (0 << 7)        /* not driven by host (pull high) */
  35 /* followed by TRN, 3-bits of ACK, TRN */
  36
  37 /**
  38  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  39  * and swd_driver.write_reg() methods will use directly.
  40  */
  41 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
  42 {
  43         uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
  44                 | (is_read ? SWD_CMD_RnW : 0)
  45                 | ((regnum & 0xc) << 1);
  46
  47         /* 8 cmd bits 4:1 may be set */
  48         if (parity_u32(cmd))
  49                 cmd |= SWD_CMD_PARITY;
  50
  51         /* driver handles START, STOP, and TRN */
  52
  53         return cmd;
  54 }
  55
  56 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
  57
  58 struct swd_driver {
  59         /**
  60          * Initialize the debug link so it can perform SWD operations.
  61          * @param trn value from WCR: how many clocks
  62          * to not drive the SWDIO line at certain points in
  63          * the SWD protocol (at least 1 clock).
  64          *
  65          * As an example, this would switch a dual-mode debug adapter
  66          * into SWD mode and out of JTAG mode.
  67          *
  68          * @return ERROR_OK on success, else a negative fault code.
  69          */
  70         int (*init)(uint8_t trn);
  71
  72
  73         /**
  74          * Queued read of an AP or DP register.
  75          *
  76          * @param dap The DAP controlled by the SWD link.
  77          * @param Command byte with APnDP/RnW/addr/parity bits
  78          * @param Where to store value to read from register
  79          */
  80         void (*read_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value);
  81
  82         /**
  83          * Queued write of an AP or DP register.
  84          *
  85          * @param dap The DAP controlled by the SWD link.
  86          * @param Command byte with APnDP/RnW/addr/parity bits
  87          * @param Value to be written to the register
  88          */
  89         void (*write_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t value);
  90
  91         /**
  92          * Execute any queued transactions and collect the result.
  93          *
  94          * @param dap The DAP controlled by the SWD link.
  95          * @return ERROR_OK on success, Ack response code on WAIT/FAULT
  96          * or negative error code on other kinds of failure.
  97          */
  98         int (*run)(struct adiv5_dap *dap);
  99
 100         /**
 101          * Configures data collection from the Single-wire
 102          * trace (SWO) signal.
 103          * @param swo true if SWO data collection should be routed.
 104          *
 105          * For example,  some debug adapters include a UART which
 106          * is normally connected to a microcontroller's UART TX,
 107          * but which may instead be connected to SWO for use in
 108          * collecting ITM (and possibly ETM) trace data.
 109          *
 110          * @return ERROR_OK on success, else a negative fault code.
 111          */
 112         int *(*trace)(struct adiv5_dap *dap, bool swo);
 113 };
 114
 115 int swd_init_reset(struct command_context *cmd_ctx);
 116 void swd_add_reset(int req_srst);
 117
 118 bool transport_is_swd(void);
 119 bool transport_is_cmsis_dap(void);
 120
 121 #endif /* SWD_H */