1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
30 typedef enum armv4_5_mode
32 ARMV4_5_MODE_USR
= 16,
33 ARMV4_5_MODE_FIQ
= 17,
34 ARMV4_5_MODE_IRQ
= 18,
35 ARMV4_5_MODE_SVC
= 19,
36 ARMV4_5_MODE_ABT
= 23,
37 ARMV4_5_MODE_UND
= 27,
38 ARMV4_5_MODE_SYS
= 31,
42 extern char** armv4_5_mode_strings
;
44 typedef enum armv4_5_state
48 ARMV4_5_STATE_JAZELLE
,
51 extern char* armv4_5_state_strings
[];
53 extern int armv4_5_core_reg_map
[7][17];
55 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
56 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
57 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
58 cache->reg_list[armv4_5_core_reg_map[mode][num]]
60 /* offsets into armv4_5 core register cache */
64 ARMV4_5_SPSR_FIQ
= 32,
65 ARMV4_5_SPSR_IRQ
= 33,
66 ARMV4_5_SPSR_SVC
= 34,
67 ARMV4_5_SPSR_ABT
= 35,
71 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
73 typedef struct armv4_5_common_s
76 reg_cache_t
*core_cache
;
77 enum armv4_5_mode core_mode
;
78 enum armv4_5_state core_state
;
79 int (*full_context
)(struct target_s
*target
);
80 int (*read_core_reg
)(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
81 int (*write_core_reg
)(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
85 typedef struct armv4_5_algorithm_s
89 enum armv4_5_mode core_mode
;
90 enum armv4_5_state core_state
;
91 } armv4_5_algorithm_t
;
93 typedef struct armv4_5_core_reg_s
96 enum armv4_5_mode mode
;
98 armv4_5_common_t
*armv4_5_common
;
101 extern reg_cache_t
* armv4_5_build_reg_cache(target_t
*target
, armv4_5_common_t
*armv4_5_common
);
103 /* map psr mode bits to linear number */
104 static __inline
int armv4_5_mode_to_number(enum armv4_5_mode mode
)
108 case ARMV4_5_MODE_USR
: return 0; break;
109 case ARMV4_5_MODE_FIQ
: return 1; break;
110 case ARMV4_5_MODE_IRQ
: return 2; break;
111 case ARMV4_5_MODE_SVC
: return 3; break;
112 case ARMV4_5_MODE_ABT
: return 4; break;
113 case ARMV4_5_MODE_UND
: return 5; break;
114 case ARMV4_5_MODE_SYS
: return 6; break;
115 case ARMV4_5_MODE_ANY
: return 0; break; /* map MODE_ANY to user mode */
117 LOG_ERROR("invalid mode value encountered");
122 /* map linear number to mode bits */
123 static __inline
enum armv4_5_mode
armv4_5_number_to_mode(int number
)
127 case 0: return ARMV4_5_MODE_USR
; break;
128 case 1: return ARMV4_5_MODE_FIQ
; break;
129 case 2: return ARMV4_5_MODE_IRQ
; break;
130 case 3: return ARMV4_5_MODE_SVC
; break;
131 case 4: return ARMV4_5_MODE_ABT
; break;
132 case 5: return ARMV4_5_MODE_UND
; break;
133 case 6: return ARMV4_5_MODE_SYS
; break;
135 LOG_ERROR("mode index out of bounds");
136 return ARMV4_5_MODE_ANY
;
140 extern int armv4_5_arch_state(struct target_s
*target
);
141 extern int armv4_5_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
);
143 extern int armv4_5_register_commands(struct command_context_s
*cmd_ctx
);
144 extern int armv4_5_init_arch_info(target_t
*target
, armv4_5_common_t
*armv4_5
);
146 extern int armv4_5_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
);
148 extern int armv4_5_invalidate_core_regs(target_t
*target
);
150 /* ARM mode instructions
153 /* Store multiple increment after
155 * List: for each bit in list: store register
156 * S: in priviledged mode: store user-mode registers
157 * W=1: update the base register. W=0: leave the base register untouched
159 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
161 /* Load multiple increment after
163 * List: for each bit in list: store register
164 * S: in priviledged mode: store user-mode registers
165 * W=1: update the base register. W=0: leave the base register untouched
167 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
170 #define ARMV4_5_NOP (0xe1a08008)
172 /* Move PSR to general purpose register
173 * R=1: SPSR R=0: CPSR
174 * Rn: target register
176 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
179 * Rd: register to store
182 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
185 * Rd: register to load
188 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
190 /* Move general purpose register to PSR
191 * R=1: SPSR R=0: CPSR
193 * 1: control field 2: extension field 4: status field 8: flags field
194 * Rm: source register
196 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
197 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
199 /* Load Register Halfword Immediate Post-Index
200 * Rd: register to load
203 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
205 /* Load Register Byte Immediate Post-Index
206 * Rd: register to load
209 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
211 /* Store register Halfword Immediate Post-Index
212 * Rd: register to store
215 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
217 /* Store register Byte Immediate Post-Index
218 * Rd: register to store
221 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
224 * Im: Branch target (left-shifted by 2 bits, added to PC)
225 * L: 1: branch and link 0: branch only
227 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
229 /* Branch and exchange (ARM state)
230 * Rm: register holding branch target address
232 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
234 /* Move to ARM register from coprocessor
235 * CP: Coprocessor number
236 * op1: Coprocessor opcode
237 * Rd: destination register
238 * CRn: first coprocessor operand
239 * CRm: second coprocessor operand
240 * op2: Second coprocessor opcode
242 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
244 /* Move to coprocessor from ARM register
245 * CP: Coprocessor number
246 * op1: Coprocessor opcode
247 * Rd: destination register
248 * CRn: first coprocessor operand
249 * CRm: second coprocessor operand
250 * op2: Second coprocessor opcode
252 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
254 /* Breakpoint instruction (ARMv5)
255 * Im: 16-bit immediate
257 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
260 /* Thumb mode instructions
263 /* Store register (Thumb mode)
264 * Rd: source register
267 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
269 /* Load register (Thumb state)
270 * Rd: destination register
273 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
275 /* Load multiple (Thumb state)
277 * List: for each bit in list: store register
279 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
281 /* Load register with PC relative addressing
282 * Rd: register to load
284 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
286 /* Move hi register (Thumb mode)
287 * Rd: destination register
288 * Rm: source register
290 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
292 /* No operation (Thumb mode)
294 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
296 /* Move immediate to register (Thumb state)
297 * Rd: destination register
298 * Im: 8-bit immediate value
300 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
302 /* Branch and Exchange
303 * Rm: register containing branch target
305 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
307 /* Branch (Thumb state)
310 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
312 /* Breakpoint instruction (ARMv5) (Thumb state)
313 * Im: 8-bit immediate
315 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
317 #endif /* ARMV4_5_H */