src/target/arm_dpm.c

   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation, Inc.,
  17  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "arm_dpm.h"
  26 #include <jtag/jtag.h>
  27 #include "register.h"
  28 #include "breakpoints.h"
  29 #include "target_type.h"
  30 #include "arm_opcodes.h"
  31
  32
  33 /**
  34  * @file
  35  * Implements various ARM DPM operations using architectural debug registers.
  36  * These routines layer over core-specific communication methods to cope with
  37  * implementation differences between cores like ARM1136 and Cortex-A8.
  38  *
  39  * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
  40  * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
  41  * ARMv7-A and ARMv7-R edition (ARM DDI 0406B).  In OpenOCD, DPM operations
  42  * are abstracted through internal programming interfaces to share code and
  43  * to minimize needless differences in debug behavior between cores.
  44  */
  45
  46 /*----------------------------------------------------------------------*/
  47
  48 /*
  49  * Coprocessor support
  50  */
  51
  52 /* Read coprocessor */
  53 static int dpm_mrc(struct target *target, int cpnum,
  54         uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  55         uint32_t *value)
  56 {
  57         struct arm *arm = target_to_arm(target);
  58         struct arm_dpm *dpm = arm->dpm;
  59         int retval;
  60
  61         retval = dpm->prepare(dpm);
  62         if (retval != ERROR_OK)
  63                 return retval;
  64
  65         LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
  66                 (int) op1, (int) CRn,
  67                 (int) CRm, (int) op2);
  68
  69         /* read coprocessor register into R0; return via DCC */
  70         retval = dpm->instr_read_data_r0(dpm,
  71                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  72                         value);
  73
  74         /* (void) */ dpm->finish(dpm);
  75         return retval;
  76 }
  77
  78 static int dpm_mcr(struct target *target, int cpnum,
  79         uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  80         uint32_t value)
  81 {
  82         struct arm *arm = target_to_arm(target);
  83         struct arm_dpm *dpm = arm->dpm;
  84         int retval;
  85
  86         retval = dpm->prepare(dpm);
  87         if (retval != ERROR_OK)
  88                 return retval;
  89
  90         LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
  91                 (int) op1, (int) CRn,
  92                 (int) CRm, (int) op2);
  93
  94         /* read DCC into r0; then write coprocessor register from R0 */
  95         retval = dpm->instr_write_data_r0(dpm,
  96                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  97                         value);
  98
  99         /* (void) */ dpm->finish(dpm);
 100         return retval;
 101 }
 102
 103 /*----------------------------------------------------------------------*/
 104
 105 /*
 106  * Register access utilities
 107  */
 108
 109 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
 110  * Routines *must* restore the original mode before returning!!
 111  */
 112 int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 113 {
 114         int retval;
 115         uint32_t cpsr;
 116
 117         /* restore previous mode */
 118         if (mode == ARM_MODE_ANY)
 119                 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
 120
 121         /* else force to the specified mode */
 122         else
 123                 cpsr = mode;
 124
 125         retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
 126         if (retval != ERROR_OK)
 127                 return retval;
 128
 129         if (dpm->instr_cpsr_sync)
 130                 retval = dpm->instr_cpsr_sync(dpm);
 131
 132         return retval;
 133 }
 134
 135 /* just read the register -- rely on the core mode being right */
 136 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 137 {
 138         uint32_t value;
 139         int retval;
 140
 141         switch (regnum) {
 142                 case 0 ... 14:
 143                         /* return via DCC:  "MCR p14, 0, Rnum, c0, c5, 0" */
 144                         retval = dpm->instr_read_data_dcc(dpm,
 145                                 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
 146                                 &value);
 147                         break;
 148                 case 15:/* PC
 149                          * "MOV r0, pc"; then return via DCC */
 150                         retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
 151
 152                         /* NOTE: this seems like a slightly awkward place to update
 153                          * this value ... but if the PC gets written (the only way
 154                          * to change what we compute), the arch spec says subsequent
 155                          * reads return values which are "unpredictable".  So this
 156                          * is always right except in those broken-by-intent cases.
 157                          */
 158                         switch (dpm->arm->core_state) {
 159                                 case ARM_STATE_ARM:
 160                                         value -= 8;
 161                                         break;
 162                                 case ARM_STATE_THUMB:
 163                                 case ARM_STATE_THUMB_EE:
 164                                         value -= 4;
 165                                         break;
 166                                 case ARM_STATE_JAZELLE:
 167                                         /* core-specific ... ? */
 168                                         LOG_WARNING("Jazelle PC adjustment unknown");
 169                                         break;
 170                         }
 171                         break;
 172                 default:
 173                         /* 16: "MRS r0, CPSR"; then return via DCC
 174                          * 17: "MRS r0, SPSR"; then return via DCC
 175                          */
 176                         retval = dpm->instr_read_data_r0(dpm,
 177                                 ARMV4_5_MRS(0, regnum & 1),
 178                                 &value);
 179                         break;
 180         }
 181
 182         if (retval == ERROR_OK) {
 183                 buf_set_u32(r->value, 0, 32, value);
 184                 r->valid = true;
 185                 r->dirty = false;
 186                 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
 187         }
 188
 189         return retval;
 190 }
 191
 192 /* just write the register -- rely on the core mode being right */
 193 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 194 {
 195         int retval;
 196         uint32_t value = buf_get_u32(r->value, 0, 32);
 197
 198         switch (regnum) {
 199                 case 0 ... 14:
 200                         /* load register from DCC:  "MRC p14, 0, Rnum, c0, c5, 0" */
 201                         retval = dpm->instr_write_data_dcc(dpm,
 202                                 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
 203                                 value);
 204                         break;
 205                 case 15:/* PC
 206                          * read r0 from DCC; then "MOV pc, r0" */
 207                         retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
 208                         break;
 209                 default:
 210                         /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
 211                          * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
 212                          */
 213                         retval = dpm->instr_write_data_r0(dpm,
 214                                 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 215                                 value);
 216                         if (retval != ERROR_OK)
 217                                 return retval;
 218
 219                         if (regnum == 16 && dpm->instr_cpsr_sync)
 220                                 retval = dpm->instr_cpsr_sync(dpm);
 221
 222                         break;
 223         }
 224
 225         if (retval == ERROR_OK) {
 226                 r->dirty = false;
 227                 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
 228         }
 229
 230         return retval;
 231 }
 232
 233 /**
 234  * Read basic registers of the the current context:  R0 to R15, and CPSR;
 235  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
 236  * In normal operation this is called on entry to halting debug state,
 237  * possibly after some other operations supporting restore of debug state
 238  * or making sure the CPU is fully idle (drain write buffer, etc).
 239  */
 240 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 241 {
 242         struct arm *arm = dpm->arm;
 243         uint32_t cpsr;
 244         int retval;
 245         struct reg *r;
 246
 247         retval = dpm->prepare(dpm);
 248         if (retval != ERROR_OK)
 249                 return retval;
 250
 251         /* read R0 first (it's used for scratch), then CPSR */
 252         r = arm->core_cache->reg_list + 0;
 253         if (!r->valid) {
 254                 retval = dpm_read_reg(dpm, r, 0);
 255                 if (retval != ERROR_OK)
 256                         goto fail;
 257         }
 258         r->dirty = true;
 259
 260         retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
 261         if (retval != ERROR_OK)
 262                 goto fail;
 263
 264         /* update core mode and state, plus shadow mapping for R8..R14 */
 265         arm_set_cpsr(arm, cpsr);
 266
 267         /* REVISIT we can probably avoid reading R1..R14, saving time... */
 268         for (unsigned i = 1; i < 16; i++) {
 269                 r = arm_reg_current(arm, i);
 270                 if (r->valid)
 271                         continue;
 272
 273                 retval = dpm_read_reg(dpm, r, i);
 274                 if (retval != ERROR_OK)
 275                         goto fail;
 276         }
 277
 278         /* NOTE: SPSR ignored (if it's even relevant). */
 279
 280         /* REVISIT the debugger can trigger various exceptions.  See the
 281          * ARMv7A architecture spec, section C5.7, for more info about
 282          * what defenses are needed; v6 debug has the most issues.
 283          */
 284
 285 fail:
 286         /* (void) */ dpm->finish(dpm);
 287         return retval;
 288 }
 289
 290 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
 291  * unless they're removed, or need updating because of single-stepping
 292  * or running debugger code.
 293  */
 294 static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
 295         struct dpm_bpwp *xp, int *set_p)
 296 {
 297         int retval = ERROR_OK;
 298         bool disable;
 299
 300         if (!set_p) {
 301                 if (!xp->dirty)
 302                         goto done;
 303                 xp->dirty = false;
 304                 /* removed or startup; we must disable it */
 305                 disable = true;
 306         } else if (bpwp) {
 307                 if (!xp->dirty)
 308                         goto done;
 309                 /* disabled, but we must set it */
 310                 xp->dirty = disable = false;
 311                 *set_p = true;
 312         } else {
 313                 if (!*set_p)
 314                         goto done;
 315                 /* set, but we must temporarily disable it */
 316                 xp->dirty = disable = true;
 317                 *set_p = false;
 318         }
 319
 320         if (disable)
 321                 retval = dpm->bpwp_disable(dpm, xp->number);
 322         else
 323                 retval = dpm->bpwp_enable(dpm, xp->number,
 324                                 xp->address, xp->control);
 325
 326         if (retval != ERROR_OK)
 327                 LOG_ERROR("%s: can't %s HW %spoint %d",
 328                         disable ? "disable" : "enable",
 329                         target_name(dpm->arm->target),
 330                         (xp->number < 16) ? "break" : "watch",
 331                         xp->number & 0xf);
 332 done:
 333         return retval;
 334 }
 335
 336 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp);
 337
 338 /**
 339  * Writes all modified core registers for all processor modes.  In normal
 340  * operation this is called on exit from halting debug state.
 341  *
 342  * @param dpm: represents the processor
 343  * @param bpwp: true ensures breakpoints and watchpoints are set,
 344  *      false ensures they are cleared
 345  */
 346 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 347 {
 348         struct arm *arm = dpm->arm;
 349         struct reg_cache *cache = arm->core_cache;
 350         int retval;
 351         bool did_write;
 352
 353         retval = dpm->prepare(dpm);
 354         if (retval != ERROR_OK)
 355                 goto done;
 356
 357         /* If we're managing hardware breakpoints for this core, enable
 358          * or disable them as requested.
 359          *
 360          * REVISIT We don't yet manage them for ANY cores.  Eventually
 361          * we should be able to assume we handle them; but until then,
 362          * cope with the hand-crafted breakpoint code.
 363          */
 364         if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
 365                 for (unsigned i = 0; i < dpm->nbp; i++) {
 366                         struct dpm_bp *dbp = dpm->dbp + i;
 367                         struct breakpoint *bp = dbp->bp;
 368
 369                         retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
 370                                         bp ? &bp->set : NULL);
 371                         if (retval != ERROR_OK)
 372                                 goto done;
 373                 }
 374         }
 375
 376         /* enable/disable watchpoints */
 377         for (unsigned i = 0; i < dpm->nwp; i++) {
 378                 struct dpm_wp *dwp = dpm->dwp + i;
 379                 struct watchpoint *wp = dwp->wp;
 380
 381                 retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
 382                                 wp ? &wp->set : NULL);
 383                 if (retval != ERROR_OK)
 384                         goto done;
 385         }
 386
 387         /* NOTE:  writes to breakpoint and watchpoint registers might
 388          * be queued, and need (efficient/batched) flushing later.
 389          */
 390
 391         /* Scan the registers until we find one that's both dirty and
 392          * eligible for flushing.  Flush that and everything else that
 393          * shares the same core mode setting.  Typically this won't
 394          * actually find anything to do...
 395          */
 396         do {
 397                 enum arm_mode mode = ARM_MODE_ANY;
 398
 399                 did_write = false;
 400
 401                 /* check everything except our scratch register R0 */
 402                 for (unsigned i = 1; i < cache->num_regs; i++) {
 403                         struct arm_reg *r;
 404                         unsigned regnum;
 405
 406                         /* also skip PC, CPSR, and non-dirty */
 407                         if (i == 15)
 408                                 continue;
 409                         if (arm->cpsr == cache->reg_list + i)
 410                                 continue;
 411                         if (!cache->reg_list[i].dirty)
 412                                 continue;
 413
 414                         r = cache->reg_list[i].arch_info;
 415                         regnum = r->num;
 416
 417                         /* may need to pick and set a mode */
 418                         if (!did_write) {
 419                                 enum arm_mode tmode;
 420
 421                                 did_write = true;
 422                                 mode = tmode = r->mode;
 423
 424                                 /* cope with special cases */
 425                                 switch (regnum) {
 426                                         case 8 ... 12:
 427                                                 /* r8..r12 "anything but FIQ" case;
 428                                                  * we "know" core mode is accurate
 429                                                  * since we haven't changed it yet
 430                                                  */
 431                                                 if (arm->core_mode == ARM_MODE_FIQ
 432                                                         && ARM_MODE_ANY
 433                                                         != mode)
 434                                                         tmode = ARM_MODE_USR;
 435                                                 break;
 436                                         case 16:
 437                                                 /* SPSR */
 438                                                 regnum++;
 439                                                 break;
 440                                 }
 441
 442                                 /* REVISIT error checks */
 443                                 if (tmode != ARM_MODE_ANY) {
 444                                         retval = dpm_modeswitch(dpm, tmode);
 445                                         if (retval != ERROR_OK)
 446                                                 goto done;
 447                                 }
 448                         }
 449                         if (r->mode != mode)
 450                                 continue;
 451
 452                         retval = dpm_write_reg(dpm,
 453                                         &cache->reg_list[i],
 454                                         regnum);
 455                         if (retval != ERROR_OK)
 456                                 goto done;
 457                 }
 458
 459         } while (did_write);
 460
 461         /* Restore original CPSR ... assuming either that we changed it,
 462          * or it's dirty.  Must write PC to ensure the return address is
 463          * defined, and must not write it before CPSR.
 464          */
 465         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 466         if (retval != ERROR_OK)
 467                 goto done;
 468         arm->cpsr->dirty = false;
 469
 470         retval = dpm_write_reg(dpm, arm->pc, 15);
 471         if (retval != ERROR_OK)
 472                 goto done;
 473         arm->pc->dirty = false;
 474
 475         /* flush R0 -- it's *very* dirty by now */
 476         retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
 477         if (retval != ERROR_OK)
 478                 goto done;
 479         cache->reg_list[0].dirty = false;
 480
 481         /* (void) */ dpm->finish(dpm);
 482 done:
 483         return retval;
 484 }
 485
 486 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
 487  * specified register ... works around flakiness from ARM core calls.
 488  * Caller already filtered out SPSR access; mode is never MODE_SYS
 489  * or MODE_ANY.
 490  */
 491 static enum arm_mode dpm_mapmode(struct arm *arm,
 492         unsigned num, enum arm_mode mode)
 493 {
 494         enum arm_mode amode = arm->core_mode;
 495
 496         /* don't switch if the mode is already correct */
 497         if (amode == ARM_MODE_SYS)
 498                 amode = ARM_MODE_USR;
 499         if (mode == amode)
 500                 return ARM_MODE_ANY;
 501
 502         switch (num) {
 503                 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
 504                 case 0 ... 7:
 505                 case 15:
 506                 case 16:
 507                         break;
 508                 /* r8..r12 aren't shadowed for anything except FIQ */
 509                 case 8 ... 12:
 510                         if (mode == ARM_MODE_FIQ)
 511                                 return mode;
 512                         break;
 513                 /* r13/sp, and r14/lr are always shadowed */
 514                 case 13:
 515                 case 14:
 516                         return mode;
 517                 default:
 518                         LOG_WARNING("invalid register #%u", num);
 519                         break;
 520         }
 521         return ARM_MODE_ANY;
 522 }
 523
 524
 525 /*
 526  * Standard ARM register accessors ... there are three methods
 527  * in "struct arm", to support individual read/write and bulk read
 528  * of registers.
 529  */
 530
 531 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
 532         int regnum, enum arm_mode mode)
 533 {
 534         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 535         int retval;
 536
 537         if (regnum < 0 || regnum > 16)
 538                 return ERROR_COMMAND_SYNTAX_ERROR;
 539
 540         if (regnum == 16) {
 541                 if (mode != ARM_MODE_ANY)
 542                         regnum = 17;
 543         } else
 544                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 545
 546         /* REVISIT what happens if we try to read SPSR in a core mode
 547          * which has no such register?
 548          */
 549
 550         retval = dpm->prepare(dpm);
 551         if (retval != ERROR_OK)
 552                 return retval;
 553
 554         if (mode != ARM_MODE_ANY) {
 555                 retval = dpm_modeswitch(dpm, mode);
 556                 if (retval != ERROR_OK)
 557                         goto fail;
 558         }
 559
 560         retval = dpm_read_reg(dpm, r, regnum);
 561         if (retval != ERROR_OK)
 562                 goto fail;
 563         /* always clean up, regardless of error */
 564
 565         if (mode != ARM_MODE_ANY)
 566                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 567
 568 fail:
 569         /* (void) */ dpm->finish(dpm);
 570         return retval;
 571 }
 572
 573 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
 574         int regnum, enum arm_mode mode, uint32_t value)
 575 {
 576         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 577         int retval;
 578
 579
 580         if (regnum < 0 || regnum > 16)
 581                 return ERROR_COMMAND_SYNTAX_ERROR;
 582
 583         if (regnum == 16) {
 584                 if (mode != ARM_MODE_ANY)
 585                         regnum = 17;
 586         } else
 587                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 588
 589         /* REVISIT what happens if we try to write SPSR in a core mode
 590          * which has no such register?
 591          */
 592
 593         retval = dpm->prepare(dpm);
 594         if (retval != ERROR_OK)
 595                 return retval;
 596
 597         if (mode != ARM_MODE_ANY) {
 598                 retval = dpm_modeswitch(dpm, mode);
 599                 if (retval != ERROR_OK)
 600                         goto fail;
 601         }
 602
 603         retval = dpm_write_reg(dpm, r, regnum);
 604         /* always clean up, regardless of error */
 605
 606         if (mode != ARM_MODE_ANY)
 607                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 608
 609 fail:
 610         /* (void) */ dpm->finish(dpm);
 611         return retval;
 612 }
 613
 614 static int arm_dpm_full_context(struct target *target)
 615 {
 616         struct arm *arm = target_to_arm(target);
 617         struct arm_dpm *dpm = arm->dpm;
 618         struct reg_cache *cache = arm->core_cache;
 619         int retval;
 620         bool did_read;
 621
 622         retval = dpm->prepare(dpm);
 623         if (retval != ERROR_OK)
 624                 goto done;
 625
 626         do {
 627                 enum arm_mode mode = ARM_MODE_ANY;
 628
 629                 did_read = false;
 630
 631                 /* We "know" arm_dpm_read_current_registers() was called so
 632                  * the unmapped registers (R0..R7, PC, AND CPSR) and some
 633                  * view of R8..R14 are current.  We also "know" oddities of
 634                  * register mapping: special cases for R8..R12 and SPSR.
 635                  *
 636                  * Pick some mode with unread registers and read them all.
 637                  * Repeat until done.
 638                  */
 639                 for (unsigned i = 0; i < cache->num_regs; i++) {
 640                         struct arm_reg *r;
 641
 642                         if (cache->reg_list[i].valid)
 643                                 continue;
 644                         r = cache->reg_list[i].arch_info;
 645
 646                         /* may need to pick a mode and set CPSR */
 647                         if (!did_read) {
 648                                 did_read = true;
 649                                 mode = r->mode;
 650
 651                                 /* For R8..R12 when we've entered debug
 652                                  * state in FIQ mode... patch mode.
 653                                  */
 654                                 if (mode == ARM_MODE_ANY)
 655                                         mode = ARM_MODE_USR;
 656
 657                                 /* REVISIT error checks */
 658                                 retval = dpm_modeswitch(dpm, mode);
 659                                 if (retval != ERROR_OK)
 660                                         goto done;
 661                         }
 662                         if (r->mode != mode)
 663                                 continue;
 664
 665                         /* CPSR was read, so "R16" must mean SPSR */
 666                         retval = dpm_read_reg(dpm,
 667                                         &cache->reg_list[i],
 668                                         (r->num == 16) ? 17 : r->num);
 669                         if (retval != ERROR_OK)
 670                                 goto done;
 671                 }
 672
 673         } while (did_read);
 674
 675         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 676         /* (void) */ dpm->finish(dpm);
 677 done:
 678         return retval;
 679 }
 680
 681
 682 /*----------------------------------------------------------------------*/
 683
 684 /*
 685  * Breakpoint and Watchpoint support.
 686  *
 687  * Hardware {break,watch}points are usually left active, to minimize
 688  * debug entry/exit costs.  When they are set or cleared, it's done in
 689  * batches.  Also, DPM-conformant hardware can update debug registers
 690  * regardless of whether the CPU is running or halted ... though that
 691  * fact isn't currently leveraged.
 692  */
 693
 694 static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 695         uint32_t addr, uint32_t length)
 696 {
 697         uint32_t control;
 698
 699         control = (1 << 0)      /* enable */
 700                 | (3 << 1);     /* both user and privileged access */
 701
 702         /* Match 1, 2, or all 4 byte addresses in this word.
 703          *
 704          * FIXME:  v7 hardware allows lengths up to 2 GB for BP and WP.
 705          * Support larger length, when addr is suitably aligned.  In
 706          * particular, allow watchpoints on 8 byte "double" values.
 707          *
 708          * REVISIT allow watchpoints on unaligned 2-bit values; and on
 709          * v7 hardware, unaligned 4-byte ones too.
 710          */
 711         switch (length) {
 712                 case 1:
 713                         control |= (1 << (addr & 3)) << 5;
 714                         break;
 715                 case 2:
 716                         /* require 2-byte alignment */
 717                         if (!(addr & 1)) {
 718                                 control |= (3 << (addr & 2)) << 5;
 719                                 break;
 720                         }
 721                 /* FALL THROUGH */
 722                 case 4:
 723                         /* require 4-byte alignment */
 724                         if (!(addr & 3)) {
 725                                 control |= 0xf << 5;
 726                                 break;
 727                         }
 728                 /* FALL THROUGH */
 729                 default:
 730                         LOG_ERROR("unsupported {break,watch}point length/alignment");
 731                         return ERROR_COMMAND_SYNTAX_ERROR;
 732         }
 733
 734         /* other shared control bits:
 735          * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
 736          * bit 20 == 0 ... not linked to a context ID
 737          * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
 738          */
 739
 740         xp->address = addr & ~3;
 741         xp->control = control;
 742         xp->dirty = true;
 743
 744         LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
 745                 xp->address, control, xp->number);
 746
 747         /* hardware is updated in write_dirty_registers() */
 748         return ERROR_OK;
 749 }
 750
 751 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
 752 {
 753         struct arm *arm = target_to_arm(target);
 754         struct arm_dpm *dpm = arm->dpm;
 755         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 756
 757         if (bp->length < 2)
 758                 return ERROR_COMMAND_SYNTAX_ERROR;
 759         if (!dpm->bpwp_enable)
 760                 return retval;
 761
 762         /* FIXME we need a generic solution for software breakpoints. */
 763         if (bp->type == BKPT_SOFT)
 764                 LOG_DEBUG("using HW bkpt, not SW...");
 765
 766         for (unsigned i = 0; i < dpm->nbp; i++) {
 767                 if (!dpm->dbp[i].bp) {
 768                         retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
 769                                         bp->address, bp->length);
 770                         if (retval == ERROR_OK)
 771                                 dpm->dbp[i].bp = bp;
 772                         break;
 773                 }
 774         }
 775
 776         return retval;
 777 }
 778
 779 static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
 780 {
 781         struct arm *arm = target_to_arm(target);
 782         struct arm_dpm *dpm = arm->dpm;
 783         int retval = ERROR_COMMAND_SYNTAX_ERROR;
 784
 785         for (unsigned i = 0; i < dpm->nbp; i++) {
 786                 if (dpm->dbp[i].bp == bp) {
 787                         dpm->dbp[i].bp = NULL;
 788                         dpm->dbp[i].bpwp.dirty = true;
 789
 790                         /* hardware is updated in write_dirty_registers() */
 791                         retval = ERROR_OK;
 792                         break;
 793                 }
 794         }
 795
 796         return retval;
 797 }
 798
 799 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
 800         struct watchpoint *wp)
 801 {
 802         int retval;
 803         struct dpm_wp *dwp = dpm->dwp + index_t;
 804         uint32_t control;
 805
 806         /* this hardware doesn't support data value matching or masking */
 807         if (wp->value || wp->mask != ~(uint32_t)0) {
 808                 LOG_DEBUG("watchpoint values and masking not supported");
 809                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 810         }
 811
 812         retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
 813         if (retval != ERROR_OK)
 814                 return retval;
 815
 816         control = dwp->bpwp.control;
 817         switch (wp->rw) {
 818                 case WPT_READ:
 819                         control |= 1 << 3;
 820                         break;
 821                 case WPT_WRITE:
 822                         control |= 2 << 3;
 823                         break;
 824                 case WPT_ACCESS:
 825                         control |= 3 << 3;
 826                         break;
 827         }
 828         dwp->bpwp.control = control;
 829
 830         dpm->dwp[index_t].wp = wp;
 831
 832         return retval;
 833 }
 834
 835 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
 836 {
 837         struct arm *arm = target_to_arm(target);
 838         struct arm_dpm *dpm = arm->dpm;
 839         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 840
 841         if (dpm->bpwp_enable) {
 842                 for (unsigned i = 0; i < dpm->nwp; i++) {
 843                         if (!dpm->dwp[i].wp) {
 844                                 retval = dpm_watchpoint_setup(dpm, i, wp);
 845                                 break;
 846                         }
 847                 }
 848         }
 849
 850         return retval;
 851 }
 852
 853 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
 854 {
 855         struct arm *arm = target_to_arm(target);
 856         struct arm_dpm *dpm = arm->dpm;
 857         int retval = ERROR_COMMAND_SYNTAX_ERROR;
 858
 859         for (unsigned i = 0; i < dpm->nwp; i++) {
 860                 if (dpm->dwp[i].wp == wp) {
 861                         dpm->dwp[i].wp = NULL;
 862                         dpm->dwp[i].bpwp.dirty = true;
 863
 864                         /* hardware is updated in write_dirty_registers() */
 865                         retval = ERROR_OK;
 866                         break;
 867                 }
 868         }
 869
 870         return retval;
 871 }
 872
 873 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
 874 {
 875         switch (dpm->arm->core_state) {
 876                 case ARM_STATE_ARM:
 877                         addr -= 8;
 878                         break;
 879                 case ARM_STATE_THUMB:
 880                 case ARM_STATE_THUMB_EE:
 881                         addr -= 4;
 882                         break;
 883                 case ARM_STATE_JAZELLE:
 884                         /* ?? */
 885                         break;
 886         }
 887         dpm->wp_pc = addr;
 888 }
 889
 890 /*----------------------------------------------------------------------*/
 891
 892 /*
 893  * Other debug and support utilities
 894  */
 895
 896 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
 897 {
 898         struct target *target = dpm->arm->target;
 899
 900         dpm->dscr = dscr;
 901
 902         /* Examine debug reason */
 903         switch (DSCR_ENTRY(dscr)) {
 904                 case 6: /* Data abort (v6 only) */
 905                 case 7: /* Prefetch abort (v6 only) */
 906                 /* FALL THROUGH -- assume a v6 core in abort mode */
 907                 case 0: /* HALT request from debugger */
 908                 case 4: /* EDBGRQ */
 909                         target->debug_reason = DBG_REASON_DBGRQ;
 910                         break;
 911                 case 1: /* HW breakpoint */
 912                 case 3: /* SW BKPT */
 913                 case 5: /* vector catch */
 914                         target->debug_reason = DBG_REASON_BREAKPOINT;
 915                         break;
 916                 case 2: /* asynch watchpoint */
 917                 case 10:/* precise watchpoint */
 918                         target->debug_reason = DBG_REASON_WATCHPOINT;
 919                         break;
 920                 default:
 921                         target->debug_reason = DBG_REASON_UNDEFINED;
 922                         break;
 923         }
 924 }
 925
 926 /*----------------------------------------------------------------------*/
 927
 928 /*
 929  * Setup and management support.
 930  */
 931
 932 /**
 933  * Hooks up this DPM to its associated target; call only once.
 934  * Initially this only covers the register cache.
 935  *
 936  * Oh, and watchpoints.  Yeah.
 937  */
 938 int arm_dpm_setup(struct arm_dpm *dpm)
 939 {
 940         struct arm *arm = dpm->arm;
 941         struct target *target = arm->target;
 942         struct reg_cache *cache;
 943
 944         arm->dpm = dpm;
 945
 946         /* register access setup */
 947         arm->full_context = arm_dpm_full_context;
 948         arm->read_core_reg = arm_dpm_read_core_reg;
 949         arm->write_core_reg = arm_dpm_write_core_reg;
 950
 951         cache = arm_build_reg_cache(target, arm);
 952         if (!cache)
 953                 return ERROR_FAIL;
 954
 955         *register_get_last_cache_p(&target->reg_cache) = cache;
 956
 957         /* coprocessor access setup */
 958         arm->mrc = dpm_mrc;
 959         arm->mcr = dpm_mcr;
 960
 961         /* breakpoint setup -- optional until it works everywhere */
 962         if (!target->type->add_breakpoint) {
 963                 target->type->add_breakpoint = dpm_add_breakpoint;
 964                 target->type->remove_breakpoint = dpm_remove_breakpoint;
 965         }
 966
 967         /* watchpoint setup */
 968         target->type->add_watchpoint = dpm_add_watchpoint;
 969         target->type->remove_watchpoint = dpm_remove_watchpoint;
 970
 971         /* FIXME add vector catch support */
 972
 973         dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
 974         dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
 975
 976         dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
 977         dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
 978
 979         if (!dpm->dbp || !dpm->dwp) {
 980                 free(dpm->dbp);
 981                 free(dpm->dwp);
 982                 return ERROR_FAIL;
 983         }
 984
 985         LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
 986                 target_name(target), dpm->nbp, dpm->nwp);
 987
 988         /* REVISIT ... and some of those breakpoints could match
 989          * execution context IDs...
 990          */
 991
 992         return ERROR_OK;
 993 }
 994
 995 /**
 996  * Reinitializes DPM state at the beginning of a new debug session
 997  * or after a reset which may have affected the debug module.
 998  */
 999 int arm_dpm_initialize(struct arm_dpm *dpm)
1000 {
1001         /* Disable all breakpoints and watchpoints at startup. */
1002         if (dpm->bpwp_disable) {
1003                 unsigned i;
1004
1005                 for (i = 0; i < dpm->nbp; i++) {
1006                         dpm->dbp[i].bpwp.number = i;
1007                         (void) dpm->bpwp_disable(dpm, i);
1008                 }
1009                 for (i = 0; i < dpm->nwp; i++) {
1010                         dpm->dwp[i].bpwp.number = 16 + i;
1011                         (void) dpm->bpwp_disable(dpm, 16 + i);
1012                 }
1013         } else
1014                 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1015                         target_name(dpm->arm->target));
1016
1017         return ERROR_OK;
1018 }