?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target/cortex_m: fix typo
[openocd.git] / src / target / cortex_m.c
blob07fea51374c1b2475b7810b904c4aee728bc1bd1
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if not done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* Restore proper interrupt masking setting. */
241 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
242 cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
243 else
244 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
245
246 /* Enable features controlled by ITM and DWT blocks, and catch only
247 * the vectors we were told to pay attention to.
248 *
249 * Target firmware is responsible for all fault handling policy
250 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
251 * or manual updates to the NVIC SHCSR and CCR registers.
252 */
253 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
254 if (retval != ERROR_OK)
255 return retval;
256
257 /* Paranoia: evidently some (early?) chips don't preserve all the
258 * debug state (including FPB, DWT, etc) across reset...
259 */
260
261 /* Enable FPB */
262 retval = cortex_m_enable_fpb(target);
263 if (retval != ERROR_OK) {
264 LOG_ERROR("Failed to enable the FPB");
265 return retval;
266 }
267
268 cortex_m->fpb_enabled = 1;
269
270 /* Restore FPB registers */
271 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
272 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
273 if (retval != ERROR_OK)
274 return retval;
275 }
276
277 /* Restore DWT registers */
278 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
279 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
280 dwt_list[i].comp);
281 if (retval != ERROR_OK)
282 return retval;
283 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
284 dwt_list[i].mask);
285 if (retval != ERROR_OK)
286 return retval;
287 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
288 dwt_list[i].function);
289 if (retval != ERROR_OK)
290 return retval;
291 }
292 retval = dap_run(swjdp);
293 if (retval != ERROR_OK)
294 return retval;
295
296 register_cache_invalidate(armv7m->arm.core_cache);
297
298 /* make sure we have latest dhcsr flags */
299 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
300
301 return retval;
302 }
303
304 static int cortex_m_examine_debug_reason(struct target *target)
305 {
306 struct cortex_m_common *cortex_m = target_to_cm(target);
307
308 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
309 * only check the debug reason if we don't know it already */
310
311 if ((target->debug_reason != DBG_REASON_DBGRQ)
312 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
313 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
314 target->debug_reason = DBG_REASON_BREAKPOINT;
315 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
316 target->debug_reason = DBG_REASON_WPTANDBKPT;
317 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
318 target->debug_reason = DBG_REASON_WATCHPOINT;
319 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
320 target->debug_reason = DBG_REASON_BREAKPOINT;
321 else /* EXTERNAL, HALTED */
322 target->debug_reason = DBG_REASON_UNDEFINED;
323 }
324
325 return ERROR_OK;
326 }
327
328 static int cortex_m_examine_exception_reason(struct target *target)
329 {
330 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
331 struct armv7m_common *armv7m = target_to_armv7m(target);
332 struct adiv5_dap *swjdp = armv7m->arm.dap;
333 int retval;
334
335 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
336 if (retval != ERROR_OK)
337 return retval;
338 switch (armv7m->exception_number) {
339 case 2: /* NMI */
340 break;
341 case 3: /* Hard Fault */
342 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
343 if (retval != ERROR_OK)
344 return retval;
345 if (except_sr & 0x40000000) {
346 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350 break;
351 case 4: /* Memory Management */
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
353 if (retval != ERROR_OK)
354 return retval;
355 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
356 if (retval != ERROR_OK)
357 return retval;
358 break;
359 case 5: /* Bus Fault */
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
361 if (retval != ERROR_OK)
362 return retval;
363 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
364 if (retval != ERROR_OK)
365 return retval;
366 break;
367 case 6: /* Usage Fault */
368 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
369 if (retval != ERROR_OK)
370 return retval;
371 break;
372 case 11: /* SVCall */
373 break;
374 case 12: /* Debug Monitor */
375 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
376 if (retval != ERROR_OK)
377 return retval;
378 break;
379 case 14: /* PendSV */
380 break;
381 case 15: /* SysTick */
382 break;
383 default:
384 except_sr = 0;
385 break;
386 }
387 retval = dap_run(swjdp);
388 if (retval == ERROR_OK)
389 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
390 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
391 armv7m_exception_string(armv7m->exception_number),
392 shcsr, except_sr, cfsr, except_ar);
393 return retval;
394 }
395
396 static int cortex_m_debug_entry(struct target *target)
397 {
398 int i;
399 uint32_t xPSR;
400 int retval;
401 struct cortex_m_common *cortex_m = target_to_cm(target);
402 struct armv7m_common *armv7m = &cortex_m->armv7m;
403 struct arm *arm = &armv7m->arm;
404 struct reg *r;
405
406 LOG_DEBUG(" ");
407
408 cortex_m_clear_halt(target);
409 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
410 if (retval != ERROR_OK)
411 return retval;
412
413 retval = armv7m->examine_debug_reason(target);
414 if (retval != ERROR_OK)
415 return retval;
416
417 /* Examine target state and mode
418 * First load register accessible through core debug port */
419 int num_regs = arm->core_cache->num_regs;
420
421 for (i = 0; i < num_regs; i++) {
422 r = &armv7m->arm.core_cache->reg_list[i];
423 if (!r->valid)
424 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
425 }
426
427 r = arm->cpsr;
428 xPSR = buf_get_u32(r->value, 0, 32);
429
430 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
431 if (xPSR & 0xf00) {
432 r->dirty = r->valid;
433 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
434 }
435
436 /* Are we in an exception handler */
437 if (xPSR & 0x1FF) {
438 armv7m->exception_number = (xPSR & 0x1FF);
439
440 arm->core_mode = ARM_MODE_HANDLER;
441 arm->map = armv7m_msp_reg_map;
442 } else {
443 unsigned control = buf_get_u32(arm->core_cache
444 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
445
446 /* is this thread privileged? */
447 arm->core_mode = control & 1
448 ? ARM_MODE_USER_THREAD
449 : ARM_MODE_THREAD;
450
451 /* which stack is it using? */
452 if (control & 2)
453 arm->map = armv7m_psp_reg_map;
454 else
455 arm->map = armv7m_msp_reg_map;
456
457 armv7m->exception_number = 0;
458 }
459
460 if (armv7m->exception_number)
461 cortex_m_examine_exception_reason(target);
462
463 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
464 arm_mode_name(arm->core_mode),
465 buf_get_u32(arm->pc->value, 0, 32),
466 target_state_name(target));
467
468 if (armv7m->post_debug_entry) {
469 retval = armv7m->post_debug_entry(target);
470 if (retval != ERROR_OK)
471 return retval;
472 }
473
474 return ERROR_OK;
475 }
476
477 static int cortex_m_poll(struct target *target)
478 {
479 int detected_failure = ERROR_OK;
480 int retval = ERROR_OK;
481 enum target_state prev_target_state = target->state;
482 struct cortex_m_common *cortex_m = target_to_cm(target);
483 struct armv7m_common *armv7m = &cortex_m->armv7m;
484
485 /* Read from Debug Halting Control and Status Register */
486 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
487 if (retval != ERROR_OK) {
488 target->state = TARGET_UNKNOWN;
489 return retval;
490 }
491
492 /* Recover from lockup. See ARMv7-M architecture spec,
493 * section B1.5.15 "Unrecoverable exception cases".
494 */
495 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
496 LOG_ERROR("%s -- clearing lockup after double fault",
497 target_name(target));
498 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
499 target->debug_reason = DBG_REASON_DBGRQ;
500
501 /* We have to execute the rest (the "finally" equivalent, but
502 * still throw this exception again).
503 */
504 detected_failure = ERROR_FAIL;
505
506 /* refresh status bits */
507 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
508 if (retval != ERROR_OK)
509 return retval;
510 }
511
512 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
513 target->state = TARGET_RESET;
514 return ERROR_OK;
515 }
516
517 if (target->state == TARGET_RESET) {
518 /* Cannot switch context while running so endreset is
519 * called with target->state == TARGET_RESET
520 */
521 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
522 cortex_m->dcb_dhcsr);
523 retval = cortex_m_endreset_event(target);
524 if (retval != ERROR_OK) {
525 target->state = TARGET_UNKNOWN;
526 return retval;
527 }
528 target->state = TARGET_RUNNING;
529 prev_target_state = TARGET_RUNNING;
530 }
531
532 if (cortex_m->dcb_dhcsr & S_HALT) {
533 target->state = TARGET_HALTED;
534
535 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
536 retval = cortex_m_debug_entry(target);
537 if (retval != ERROR_OK)
538 return retval;
539
540 if (arm_semihosting(target, &retval) != 0)
541 return retval;
542
543 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
544 }
545 if (prev_target_state == TARGET_DEBUG_RUNNING) {
546 LOG_DEBUG(" ");
547 retval = cortex_m_debug_entry(target);
548 if (retval != ERROR_OK)
549 return retval;
550
551 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
552 }
553 }
554
555 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
556 * How best to model low power modes?
557 */
558
559 if (target->state == TARGET_UNKNOWN) {
560 /* check if processor is retiring instructions */
561 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
562 target->state = TARGET_RUNNING;
563 retval = ERROR_OK;
564 }
565 }
566
567 /* Did we detect a failure condition that we cleared? */
568 if (detected_failure != ERROR_OK)
569 retval = detected_failure;
570 return retval;
571 }
572
573 static int cortex_m_halt(struct target *target)
574 {
575 LOG_DEBUG("target->state: %s",
576 target_state_name(target));
577
578 if (target->state == TARGET_HALTED) {
579 LOG_DEBUG("target was already halted");
580 return ERROR_OK;
581 }
582
583 if (target->state == TARGET_UNKNOWN)
584 LOG_WARNING("target was in unknown state when halt was requested");
585
586 if (target->state == TARGET_RESET) {
587 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
588 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
589 return ERROR_TARGET_FAILURE;
590 } else {
591 /* we came here in a reset_halt or reset_init sequence
592 * debug entry was already prepared in cortex_m3_assert_reset()
593 */
594 target->debug_reason = DBG_REASON_DBGRQ;
595
596 return ERROR_OK;
597 }
598 }
599
600 /* Write to Debug Halting Control and Status Register */
601 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
602
603 target->debug_reason = DBG_REASON_DBGRQ;
604
605 return ERROR_OK;
606 }
607
608 static int cortex_m_soft_reset_halt(struct target *target)
609 {
610 struct cortex_m_common *cortex_m = target_to_cm(target);
611 struct armv7m_common *armv7m = &cortex_m->armv7m;
612 uint32_t dcb_dhcsr = 0;
613 int retval, timeout = 0;
614
615 /* soft_reset_halt is deprecated on cortex_m as the same functionality
616 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
617 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
618 * core, not the peripherals */
619 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
620
621 /* Enter debug state on reset; restore DEMCR in endreset_event() */
622 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
623 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
624 if (retval != ERROR_OK)
625 return retval;
626
627 /* Request a core-only reset */
628 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
629 AIRCR_VECTKEY | AIRCR_VECTRESET);
630 if (retval != ERROR_OK)
631 return retval;
632 target->state = TARGET_RESET;
633
634 /* registers are now invalid */
635 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
636
637 while (timeout < 100) {
638 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
639 if (retval == ERROR_OK) {
640 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
641 &cortex_m->nvic_dfsr);
642 if (retval != ERROR_OK)
643 return retval;
644 if ((dcb_dhcsr & S_HALT)
645 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
646 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
647 "DFSR 0x%08x",
648 (unsigned) dcb_dhcsr,
649 (unsigned) cortex_m->nvic_dfsr);
650 cortex_m_poll(target);
651 /* FIXME restore user's vector catch config */
652 return ERROR_OK;
653 } else
654 LOG_DEBUG("waiting for system reset-halt, "
655 "DHCSR 0x%08x, %d ms",
656 (unsigned) dcb_dhcsr, timeout);
657 }
658 timeout++;
659 alive_sleep(1);
660 }
661
662 return ERROR_OK;
663 }
664
665 void cortex_m_enable_breakpoints(struct target *target)
666 {
667 struct breakpoint *breakpoint = target->breakpoints;
668
669 /* set any pending breakpoints */
670 while (breakpoint) {
671 if (!breakpoint->set)
672 cortex_m_set_breakpoint(target, breakpoint);
673 breakpoint = breakpoint->next;
674 }
675 }
676
677 static int cortex_m_resume(struct target *target, int current,
678 target_addr_t address, int handle_breakpoints, int debug_execution)
679 {
680 struct armv7m_common *armv7m = target_to_armv7m(target);
681 struct breakpoint *breakpoint = NULL;
682 uint32_t resume_pc;
683 struct reg *r;
684
685 if (target->state != TARGET_HALTED) {
686 LOG_WARNING("target not halted");
687 return ERROR_TARGET_NOT_HALTED;
688 }
689
690 if (!debug_execution) {
691 target_free_all_working_areas(target);
692 cortex_m_enable_breakpoints(target);
693 cortex_m_enable_watchpoints(target);
694 }
695
696 if (debug_execution) {
697 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
698
699 /* Disable interrupts */
700 /* We disable interrupts in the PRIMASK register instead of
701 * masking with C_MASKINTS. This is probably the same issue
702 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
703 * in parallel with disabled interrupts can cause local faults
704 * to not be taken.
705 *
706 * REVISIT this clearly breaks non-debug execution, since the
707 * PRIMASK register state isn't saved/restored... workaround
708 * by never resuming app code after debug execution.
709 */
710 buf_set_u32(r->value, 0, 1, 1);
711 r->dirty = true;
712 r->valid = true;
713
714 /* Make sure we are in Thumb mode */
715 r = armv7m->arm.cpsr;
716 buf_set_u32(r->value, 24, 1, 1);
717 r->dirty = true;
718 r->valid = true;
719 }
720
721 /* current = 1: continue on current pc, otherwise continue at <address> */
722 r = armv7m->arm.pc;
723 if (!current) {
724 buf_set_u32(r->value, 0, 32, address);
725 r->dirty = true;
726 r->valid = true;
727 }
728
729 /* if we halted last time due to a bkpt instruction
730 * then we have to manually step over it, otherwise
731 * the core will break again */
732
733 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
734 && !debug_execution)
735 armv7m_maybe_skip_bkpt_inst(target, NULL);
736
737 resume_pc = buf_get_u32(r->value, 0, 32);
738
739 armv7m_restore_context(target);
740
741 /* the front-end may request us not to handle breakpoints */
742 if (handle_breakpoints) {
743 /* Single step past breakpoint at current address */
744 breakpoint = breakpoint_find(target, resume_pc);
745 if (breakpoint) {
746 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
747 breakpoint->address,
748 breakpoint->unique_id);
749 cortex_m_unset_breakpoint(target, breakpoint);
750 cortex_m_single_step_core(target);
751 cortex_m_set_breakpoint(target, breakpoint);
752 }
753 }
754
755 /* Restart core */
756 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
757
758 target->debug_reason = DBG_REASON_NOTHALTED;
759
760 /* registers are now invalid */
761 register_cache_invalidate(armv7m->arm.core_cache);
762
763 if (!debug_execution) {
764 target->state = TARGET_RUNNING;
765 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
766 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
767 } else {
768 target->state = TARGET_DEBUG_RUNNING;
769 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
770 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
771 }
772
773 return ERROR_OK;
774 }
775
776 /* int irqstepcount = 0; */
777 static int cortex_m_step(struct target *target, int current,
778 target_addr_t address, int handle_breakpoints)
779 {
780 struct cortex_m_common *cortex_m = target_to_cm(target);
781 struct armv7m_common *armv7m = &cortex_m->armv7m;
782 struct breakpoint *breakpoint = NULL;
783 struct reg *pc = armv7m->arm.pc;
784 bool bkpt_inst_found = false;
785 int retval;
786 bool isr_timed_out = false;
787
788 if (target->state != TARGET_HALTED) {
789 LOG_WARNING("target not halted");
790 return ERROR_TARGET_NOT_HALTED;
791 }
792
793 /* current = 1: continue on current pc, otherwise continue at <address> */
794 if (!current)
795 buf_set_u32(pc->value, 0, 32, address);
796
797 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
798
799 /* the front-end may request us not to handle breakpoints */
800 if (handle_breakpoints) {
801 breakpoint = breakpoint_find(target, pc_value);
802 if (breakpoint)
803 cortex_m_unset_breakpoint(target, breakpoint);
804 }
805
806 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
807
808 target->debug_reason = DBG_REASON_SINGLESTEP;
809
810 armv7m_restore_context(target);
811
812 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
813
814 /* if no bkpt instruction is found at pc then we can perform
815 * a normal step, otherwise we have to manually step over the bkpt
816 * instruction - as such simulate a step */
817 if (bkpt_inst_found == false) {
818 /* Automatic ISR masking mode off: Just step over the next instruction */
819 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
820 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
821 else {
822 /* Process interrupts during stepping in a way they don't interfere
823 * debugging.
824 *
825 * Principle:
826 *
827 * Set a temporary break point at the current pc and let the core run
828 * with interrupts enabled. Pending interrupts get served and we run
829 * into the breakpoint again afterwards. Then we step over the next
830 * instruction with interrupts disabled.
831 *
832 * If the pending interrupts don't complete within time, we leave the
833 * core running. This may happen if the interrupts trigger faster
834 * than the core can process them or the handler doesn't return.
835 *
836 * If no more breakpoints are available we simply do a step with
837 * interrupts enabled.
838 *
839 */
840
841 /* 2012-09-29 ph
842 *
843 * If a break point is already set on the lower half word then a break point on
844 * the upper half word will not break again when the core is restarted. So we
845 * just step over the instruction with interrupts disabled.
846 *
847 * The documentation has no information about this, it was found by observation
848 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
849 * suffer from this problem.
850 *
851 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
852 * address has it always cleared. The former is done to indicate thumb mode
853 * to gdb.
854 *
855 */
856 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
857 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
858 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
859 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
860 /* Re-enable interrupts */
861 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
862 }
863 else {
864
865 /* Set a temporary break point */
866 if (breakpoint)
867 retval = cortex_m_set_breakpoint(target, breakpoint);
868 else
869 retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
870 bool tmp_bp_set = (retval == ERROR_OK);
871
872 /* No more breakpoints left, just do a step */
873 if (!tmp_bp_set)
874 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
875 else {
876 /* Start the core */
877 LOG_DEBUG("Starting core to serve pending interrupts");
878 int64_t t_start = timeval_ms();
879 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
880
881 /* Wait for pending handlers to complete or timeout */
882 do {
883 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
884 DCB_DHCSR,
885 &cortex_m->dcb_dhcsr);
886 if (retval != ERROR_OK) {
887 target->state = TARGET_UNKNOWN;
888 return retval;
889 }
890 isr_timed_out = ((timeval_ms() - t_start) > 500);
891 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
892
893 /* only remove breakpoint if we created it */
894 if (breakpoint)
895 cortex_m_unset_breakpoint(target, breakpoint);
896 else {
897 /* Remove the temporary breakpoint */
898 breakpoint_remove(target, pc_value);
899 }
900
901 if (isr_timed_out) {
902 LOG_DEBUG("Interrupt handlers didn't complete within time, "
903 "leaving target running");
904 } else {
905 /* Step over next instruction with interrupts disabled */
906 cortex_m_write_debug_halt_mask(target,
907 C_HALT | C_MASKINTS,
908 0);
909 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
910 /* Re-enable interrupts */
911 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
912 }
913 }
914 }
915 }
916 }
917
918 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
919 if (retval != ERROR_OK)
920 return retval;
921
922 /* registers are now invalid */
923 register_cache_invalidate(armv7m->arm.core_cache);
924
925 if (breakpoint)
926 cortex_m_set_breakpoint(target, breakpoint);
927
928 if (isr_timed_out) {
929 /* Leave the core running. The user has to stop execution manually. */
930 target->debug_reason = DBG_REASON_NOTHALTED;
931 target->state = TARGET_RUNNING;
932 return ERROR_OK;
933 }
934
935 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
936 " nvic_icsr = 0x%" PRIx32,
937 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
938
939 retval = cortex_m_debug_entry(target);
940 if (retval != ERROR_OK)
941 return retval;
942 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
943
944 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
945 " nvic_icsr = 0x%" PRIx32,
946 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
947
948 return ERROR_OK;
949 }
950
951 static int cortex_m_assert_reset(struct target *target)
952 {
953 struct cortex_m_common *cortex_m = target_to_cm(target);
954 struct armv7m_common *armv7m = &cortex_m->armv7m;
955 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
956
957 LOG_DEBUG("target->state: %s",
958 target_state_name(target));
959
960 enum reset_types jtag_reset_config = jtag_get_reset_config();
961
962 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
963 /* allow scripts to override the reset event */
964
965 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
966 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
967 target->state = TARGET_RESET;
968
969 return ERROR_OK;
970 }
971
972 /* some cores support connecting while srst is asserted
973 * use that mode is it has been configured */
974
975 bool srst_asserted = false;
976
977 if (!target_was_examined(target)) {
978 if (jtag_reset_config & RESET_HAS_SRST) {
979 adapter_assert_reset();
980 if (target->reset_halt)
981 LOG_ERROR("Target not examined, will not halt after reset!");
982 return ERROR_OK;
983 } else {
984 LOG_ERROR("Target not examined, reset NOT asserted!");
985 return ERROR_FAIL;
986 }
987 }
988
989 if ((jtag_reset_config & RESET_HAS_SRST) &&
990 (jtag_reset_config & RESET_SRST_NO_GATING)) {
991 adapter_assert_reset();
992 srst_asserted = true;
993 }
994
995 /* Enable debug requests */
996 int retval;
997 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
998 /* Store important errors instead of failing and proceed to reset assert */
999
1000 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1001 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1002
1003 /* If the processor is sleeping in a WFI or WFE instruction, the
1004 * C_HALT bit must be asserted to regain control */
1005 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1006 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1007
1008 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1009 /* Ignore less important errors */
1010
1011 if (!target->reset_halt) {
1012 /* Set/Clear C_MASKINTS in a separate operation */
1013 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1014 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1015
1016 /* clear any debug flags before resuming */
1017 cortex_m_clear_halt(target);
1018
1019 /* clear C_HALT in dhcsr reg */
1020 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1021 } else {
1022 /* Halt in debug on reset; endreset_event() restores DEMCR.
1023 *
1024 * REVISIT catching BUSERR presumably helps to defend against
1025 * bad vector table entries. Should this include MMERR or
1026 * other flags too?
1027 */
1028 int retval2;
1029 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1030 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1031 if (retval != ERROR_OK || retval2 != ERROR_OK)
1032 LOG_INFO("AP write error, reset will not halt");
1033 }
1034
1035 if (jtag_reset_config & RESET_HAS_SRST) {
1036 /* default to asserting srst */
1037 if (!srst_asserted)
1038 adapter_assert_reset();
1039
1040 /* srst is asserted, ignore AP access errors */
1041 retval = ERROR_OK;
1042 } else {
1043 /* Use a standard Cortex-M3 software reset mechanism.
1044 * We default to using VECRESET as it is supported on all current cores.
1045 * This has the disadvantage of not resetting the peripherals, so a
1046 * reset-init event handler is needed to perform any peripheral resets.
1047 */
1048 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1049 ? "SYSRESETREQ" : "VECTRESET");
1050
1051 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1052 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1053 "handler to reset any peripherals or configure hardware srst support.");
1054 }
1055
1056 int retval3;
1057 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1058 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1059 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1060 if (retval3 != ERROR_OK)
1061 LOG_DEBUG("Ignoring AP write error right after reset");
1062
1063 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1064 if (retval3 != ERROR_OK)
1065 LOG_ERROR("DP initialisation failed");
1066
1067 else {
1068 /* I do not know why this is necessary, but it
1069 * fixes strange effects (step/resume cause NMI
1070 * after reset) on LM3S6918 -- Michael Schwingen
1071 */
1072 uint32_t tmp;
1073 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1074 }
1075 }
1076
1077 target->state = TARGET_RESET;
1078 jtag_add_sleep(50000);
1079
1080 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1081
1082 /* now return stored error code if any */
1083 if (retval != ERROR_OK)
1084 return retval;
1085
1086 if (target->reset_halt) {
1087 retval = target_halt(target);
1088 if (retval != ERROR_OK)
1089 return retval;
1090 }
1091
1092 return ERROR_OK;
1093 }
1094
1095 static int cortex_m_deassert_reset(struct target *target)
1096 {
1097 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1098
1099 LOG_DEBUG("target->state: %s",
1100 target_state_name(target));
1101
1102 /* deassert reset lines */
1103 adapter_deassert_reset();
1104
1105 enum reset_types jtag_reset_config = jtag_get_reset_config();
1106
1107 if ((jtag_reset_config & RESET_HAS_SRST) &&
1108 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1109 target_was_examined(target)) {
1110 int retval = dap_dp_init(armv7m->debug_ap->dap);
1111 if (retval != ERROR_OK) {
1112 LOG_ERROR("DP initialisation failed");
1113 return retval;
1114 }
1115 }
1116
1117 return ERROR_OK;
1118 }
1119
1120 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1121 {
1122 int retval;
1123 int fp_num = 0;
1124 struct cortex_m_common *cortex_m = target_to_cm(target);
1125 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1126
1127 if (breakpoint->set) {
1128 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1129 return ERROR_OK;
1130 }
1131
1132 if (breakpoint->type == BKPT_HARD) {
1133 uint32_t fpcr_value;
1134 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1135 fp_num++;
1136 if (fp_num >= cortex_m->fp_num_code) {
1137 LOG_ERROR("Can not find free FPB Comparator!");
1138 return ERROR_FAIL;
1139 }
1140 breakpoint->set = fp_num + 1;
1141 fpcr_value = breakpoint->address | 1;
1142 if (cortex_m->fp_rev == 0) {
1143 if (breakpoint->address > 0x1FFFFFFF) {
1144 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1145 return ERROR_FAIL;
1146 }
1147 uint32_t hilo;
1148 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1149 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1150 } else if (cortex_m->fp_rev > 1) {
1151 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1152 return ERROR_FAIL;
1153 }
1154 comparator_list[fp_num].used = 1;
1155 comparator_list[fp_num].fpcr_value = fpcr_value;
1156 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1157 comparator_list[fp_num].fpcr_value);
1158 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1159 fp_num,
1160 comparator_list[fp_num].fpcr_value);
1161 if (!cortex_m->fpb_enabled) {
1162 LOG_DEBUG("FPB wasn't enabled, do it now");
1163 retval = cortex_m_enable_fpb(target);
1164 if (retval != ERROR_OK) {
1165 LOG_ERROR("Failed to enable the FPB");
1166 return retval;
1167 }
1168
1169 cortex_m->fpb_enabled = 1;
1170 }
1171 } else if (breakpoint->type == BKPT_SOFT) {
1172 uint8_t code[4];
1173
1174 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1175 * semihosting; don't use that. Otherwise the BKPT
1176 * parameter is arbitrary.
1177 */
1178 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1179 retval = target_read_memory(target,
1180 breakpoint->address & 0xFFFFFFFE,
1181 breakpoint->length, 1,
1182 breakpoint->orig_instr);
1183 if (retval != ERROR_OK)
1184 return retval;
1185 retval = target_write_memory(target,
1186 breakpoint->address & 0xFFFFFFFE,
1187 breakpoint->length, 1,
1188 code);
1189 if (retval != ERROR_OK)
1190 return retval;
1191 breakpoint->set = true;
1192 }
1193
1194 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1195 breakpoint->unique_id,
1196 (int)(breakpoint->type),
1197 breakpoint->address,
1198 breakpoint->length,
1199 breakpoint->set);
1200
1201 return ERROR_OK;
1202 }
1203
1204 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1205 {
1206 int retval;
1207 struct cortex_m_common *cortex_m = target_to_cm(target);
1208 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1209
1210 if (!breakpoint->set) {
1211 LOG_WARNING("breakpoint not set");
1212 return ERROR_OK;
1213 }
1214
1215 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1216 breakpoint->unique_id,
1217 (int)(breakpoint->type),
1218 breakpoint->address,
1219 breakpoint->length,
1220 breakpoint->set);
1221
1222 if (breakpoint->type == BKPT_HARD) {
1223 int fp_num = breakpoint->set - 1;
1224 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1225 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1226 return ERROR_OK;
1227 }
1228 comparator_list[fp_num].used = 0;
1229 comparator_list[fp_num].fpcr_value = 0;
1230 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1231 comparator_list[fp_num].fpcr_value);
1232 } else {
1233 /* restore original instruction (kept in target endianness) */
1234 if (breakpoint->length == 4) {
1235 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1236 breakpoint->orig_instr);
1237 if (retval != ERROR_OK)
1238 return retval;
1239 } else {
1240 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1241 breakpoint->orig_instr);
1242 if (retval != ERROR_OK)
1243 return retval;
1244 }
1245 }
1246 breakpoint->set = false;
1247
1248 return ERROR_OK;
1249 }
1250
1251 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1252 {
1253 struct cortex_m_common *cortex_m = target_to_cm(target);
1254
1255 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1256 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1257 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1258 }
1259
1260 if (breakpoint->length == 3) {
1261 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1262 breakpoint->length = 2;
1263 }
1264
1265 if ((breakpoint->length != 2)) {
1266 LOG_INFO("only breakpoints of two bytes length supported");
1267 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1268 }
1269
1270 if (breakpoint->type == BKPT_HARD)
1271 cortex_m->fp_code_available--;
1272
1273 return cortex_m_set_breakpoint(target, breakpoint);
1274 }
1275
1276 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1277 {
1278 struct cortex_m_common *cortex_m = target_to_cm(target);
1279
1280 /* REVISIT why check? FPB can be updated with core running ... */
1281 if (target->state != TARGET_HALTED) {
1282 LOG_WARNING("target not halted");
1283 return ERROR_TARGET_NOT_HALTED;
1284 }
1285
1286 if (breakpoint->set)
1287 cortex_m_unset_breakpoint(target, breakpoint);
1288
1289 if (breakpoint->type == BKPT_HARD)
1290 cortex_m->fp_code_available++;
1291
1292 return ERROR_OK;
1293 }
1294
1295 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1296 {
1297 int dwt_num = 0;
1298 uint32_t mask, temp;
1299 struct cortex_m_common *cortex_m = target_to_cm(target);
1300
1301 /* watchpoint params were validated earlier */
1302 mask = 0;
1303 temp = watchpoint->length;
1304 while (temp) {
1305 temp >>= 1;
1306 mask++;
1307 }
1308 mask--;
1309
1310 /* REVISIT Don't fully trust these "not used" records ... users
1311 * may set up breakpoints by hand, e.g. dual-address data value
1312 * watchpoint using comparator #1; comparator #0 matching cycle
1313 * count; send data trace info through ITM and TPIU; etc
1314 */
1315 struct cortex_m_dwt_comparator *comparator;
1316
1317 for (comparator = cortex_m->dwt_comparator_list;
1318 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1319 comparator++, dwt_num++)
1320 continue;
1321 if (dwt_num >= cortex_m->dwt_num_comp) {
1322 LOG_ERROR("Can not find free DWT Comparator");
1323 return ERROR_FAIL;
1324 }
1325 comparator->used = 1;
1326 watchpoint->set = dwt_num + 1;
1327
1328 comparator->comp = watchpoint->address;
1329 target_write_u32(target, comparator->dwt_comparator_address + 0,
1330 comparator->comp);
1331
1332 comparator->mask = mask;
1333 target_write_u32(target, comparator->dwt_comparator_address + 4,
1334 comparator->mask);
1335
1336 switch (watchpoint->rw) {
1337 case WPT_READ:
1338 comparator->function = 5;
1339 break;
1340 case WPT_WRITE:
1341 comparator->function = 6;
1342 break;
1343 case WPT_ACCESS:
1344 comparator->function = 7;
1345 break;
1346 }
1347 target_write_u32(target, comparator->dwt_comparator_address + 8,
1348 comparator->function);
1349
1350 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1351 watchpoint->unique_id, dwt_num,
1352 (unsigned) comparator->comp,
1353 (unsigned) comparator->mask,
1354 (unsigned) comparator->function);
1355 return ERROR_OK;
1356 }
1357
1358 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1359 {
1360 struct cortex_m_common *cortex_m = target_to_cm(target);
1361 struct cortex_m_dwt_comparator *comparator;
1362 int dwt_num;
1363
1364 if (!watchpoint->set) {
1365 LOG_WARNING("watchpoint (wpid: %d) not set",
1366 watchpoint->unique_id);
1367 return ERROR_OK;
1368 }
1369
1370 dwt_num = watchpoint->set - 1;
1371
1372 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1373 watchpoint->unique_id, dwt_num,
1374 (unsigned) watchpoint->address);
1375
1376 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1377 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1378 return ERROR_OK;
1379 }
1380
1381 comparator = cortex_m->dwt_comparator_list + dwt_num;
1382 comparator->used = 0;
1383 comparator->function = 0;
1384 target_write_u32(target, comparator->dwt_comparator_address + 8,
1385 comparator->function);
1386
1387 watchpoint->set = false;
1388
1389 return ERROR_OK;
1390 }
1391
1392 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1393 {
1394 struct cortex_m_common *cortex_m = target_to_cm(target);
1395
1396 if (cortex_m->dwt_comp_available < 1) {
1397 LOG_DEBUG("no comparators?");
1398 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1399 }
1400
1401 /* hardware doesn't support data value masking */
1402 if (watchpoint->mask != ~(uint32_t)0) {
1403 LOG_DEBUG("watchpoint value masks not supported");
1404 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1405 }
1406
1407 /* hardware allows address masks of up to 32K */
1408 unsigned mask;
1409
1410 for (mask = 0; mask < 16; mask++) {
1411 if ((1u << mask) == watchpoint->length)
1412 break;
1413 }
1414 if (mask == 16) {
1415 LOG_DEBUG("unsupported watchpoint length");
1416 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1417 }
1418 if (watchpoint->address & ((1 << mask) - 1)) {
1419 LOG_DEBUG("watchpoint address is unaligned");
1420 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1421 }
1422
1423 /* Caller doesn't seem to be able to describe watching for data
1424 * values of zero; that flags "no value".
1425 *
1426 * REVISIT This DWT may well be able to watch for specific data
1427 * values. Requires comparator #1 to set DATAVMATCH and match
1428 * the data, and another comparator (DATAVADDR0) matching addr.
1429 */
1430 if (watchpoint->value) {
1431 LOG_DEBUG("data value watchpoint not YET supported");
1432 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1433 }
1434
1435 cortex_m->dwt_comp_available--;
1436 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1437
1438 return ERROR_OK;
1439 }
1440
1441 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1442 {
1443 struct cortex_m_common *cortex_m = target_to_cm(target);
1444
1445 /* REVISIT why check? DWT can be updated with core running ... */
1446 if (target->state != TARGET_HALTED) {
1447 LOG_WARNING("target not halted");
1448 return ERROR_TARGET_NOT_HALTED;
1449 }
1450
1451 if (watchpoint->set)
1452 cortex_m_unset_watchpoint(target, watchpoint);
1453
1454 cortex_m->dwt_comp_available++;
1455 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1456
1457 return ERROR_OK;
1458 }
1459
1460 void cortex_m_enable_watchpoints(struct target *target)
1461 {
1462 struct watchpoint *watchpoint = target->watchpoints;
1463
1464 /* set any pending watchpoints */
1465 while (watchpoint) {
1466 if (!watchpoint->set)
1467 cortex_m_set_watchpoint(target, watchpoint);
1468 watchpoint = watchpoint->next;
1469 }
1470 }
1471
1472 static int cortex_m_load_core_reg_u32(struct target *target,
1473 uint32_t num, uint32_t *value)
1474 {
1475 int retval;
1476
1477 /* NOTE: we "know" here that the register identifiers used
1478 * in the v7m header match the Cortex-M3 Debug Core Register
1479 * Selector values for R0..R15, xPSR, MSP, and PSP.
1480 */
1481 switch (num) {
1482 case 0 ... 18:
1483 /* read a normal core register */
1484 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1485
1486 if (retval != ERROR_OK) {
1487 LOG_ERROR("JTAG failure %i", retval);
1488 return ERROR_JTAG_DEVICE_ERROR;
1489 }
1490 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1491 break;
1492
1493 case ARMV7M_FPSCR:
1494 /* Floating-point Status and Registers */
1495 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1496 if (retval != ERROR_OK)
1497 return retval;
1498 retval = target_read_u32(target, DCB_DCRDR, value);
1499 if (retval != ERROR_OK)
1500 return retval;
1501 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1502 break;
1503
1504 case ARMV7M_S0 ... ARMV7M_S31:
1505 /* Floating-point Status and Registers */
1506 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1507 if (retval != ERROR_OK)
1508 return retval;
1509 retval = target_read_u32(target, DCB_DCRDR, value);
1510 if (retval != ERROR_OK)
1511 return retval;
1512 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1513 (int)(num - ARMV7M_S0), *value);
1514 break;
1515
1516 case ARMV7M_PRIMASK:
1517 case ARMV7M_BASEPRI:
1518 case ARMV7M_FAULTMASK:
1519 case ARMV7M_CONTROL:
1520 /* Cortex-M3 packages these four registers as bitfields
1521 * in one Debug Core register. So say r0 and r2 docs;
1522 * it was removed from r1 docs, but still works.
1523 */
1524 cortexm_dap_read_coreregister_u32(target, value, 20);
1525
1526 switch (num) {
1527 case ARMV7M_PRIMASK:
1528 *value = buf_get_u32((uint8_t *)value, 0, 1);
1529 break;
1530
1531 case ARMV7M_BASEPRI:
1532 *value = buf_get_u32((uint8_t *)value, 8, 8);
1533 break;
1534
1535 case ARMV7M_FAULTMASK:
1536 *value = buf_get_u32((uint8_t *)value, 16, 1);
1537 break;
1538
1539 case ARMV7M_CONTROL:
1540 *value = buf_get_u32((uint8_t *)value, 24, 2);
1541 break;
1542 }
1543
1544 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1545 break;
1546
1547 default:
1548 return ERROR_COMMAND_SYNTAX_ERROR;
1549 }
1550
1551 return ERROR_OK;
1552 }
1553
1554 static int cortex_m_store_core_reg_u32(struct target *target,
1555 uint32_t num, uint32_t value)
1556 {
1557 int retval;
1558 uint32_t reg;
1559 struct armv7m_common *armv7m = target_to_armv7m(target);
1560
1561 /* NOTE: we "know" here that the register identifiers used
1562 * in the v7m header match the Cortex-M3 Debug Core Register
1563 * Selector values for R0..R15, xPSR, MSP, and PSP.
1564 */
1565 switch (num) {
1566 case 0 ... 18:
1567 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1568 if (retval != ERROR_OK) {
1569 struct reg *r;
1570
1571 LOG_ERROR("JTAG failure");
1572 r = armv7m->arm.core_cache->reg_list + num;
1573 r->dirty = r->valid;
1574 return ERROR_JTAG_DEVICE_ERROR;
1575 }
1576 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1577 break;
1578
1579 case ARMV7M_FPSCR:
1580 /* Floating-point Status and Registers */
1581 retval = target_write_u32(target, DCB_DCRDR, value);
1582 if (retval != ERROR_OK)
1583 return retval;
1584 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1585 if (retval != ERROR_OK)
1586 return retval;
1587 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1588 break;
1589
1590 case ARMV7M_S0 ... ARMV7M_S31:
1591 /* Floating-point Status and Registers */
1592 retval = target_write_u32(target, DCB_DCRDR, value);
1593 if (retval != ERROR_OK)
1594 return retval;
1595 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1596 if (retval != ERROR_OK)
1597 return retval;
1598 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1599 (int)(num - ARMV7M_S0), value);
1600 break;
1601
1602 case ARMV7M_PRIMASK:
1603 case ARMV7M_BASEPRI:
1604 case ARMV7M_FAULTMASK:
1605 case ARMV7M_CONTROL:
1606 /* Cortex-M3 packages these four registers as bitfields
1607 * in one Debug Core register. So say r0 and r2 docs;
1608 * it was removed from r1 docs, but still works.
1609 */
1610 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1611
1612 switch (num) {
1613 case ARMV7M_PRIMASK:
1614 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1615 break;
1616
1617 case ARMV7M_BASEPRI:
1618 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1619 break;
1620
1621 case ARMV7M_FAULTMASK:
1622 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1623 break;
1624
1625 case ARMV7M_CONTROL:
1626 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1627 break;
1628 }
1629
1630 cortexm_dap_write_coreregister_u32(target, reg, 20);
1631
1632 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1633 break;
1634
1635 default:
1636 return ERROR_COMMAND_SYNTAX_ERROR;
1637 }
1638
1639 return ERROR_OK;
1640 }
1641
1642 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1643 uint32_t size, uint32_t count, uint8_t *buffer)
1644 {
1645 struct armv7m_common *armv7m = target_to_armv7m(target);
1646
1647 if (armv7m->arm.is_armv6m) {
1648 /* armv6m does not handle unaligned memory access */
1649 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1650 return ERROR_TARGET_UNALIGNED_ACCESS;
1651 }
1652
1653 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1654 }
1655
1656 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1657 uint32_t size, uint32_t count, const uint8_t *buffer)
1658 {
1659 struct armv7m_common *armv7m = target_to_armv7m(target);
1660
1661 if (armv7m->arm.is_armv6m) {
1662 /* armv6m does not handle unaligned memory access */
1663 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1664 return ERROR_TARGET_UNALIGNED_ACCESS;
1665 }
1666
1667 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1668 }
1669
1670 static int cortex_m_init_target(struct command_context *cmd_ctx,
1671 struct target *target)
1672 {
1673 armv7m_build_reg_cache(target);
1674 arm_semihosting_init(target);
1675 return ERROR_OK;
1676 }
1677
1678 void cortex_m_deinit_target(struct target *target)
1679 {
1680 struct cortex_m_common *cortex_m = target_to_cm(target);
1681
1682 free(cortex_m->fp_comparator_list);
1683
1684 cortex_m_dwt_free(target);
1685 armv7m_free_reg_cache(target);
1686
1687 free(target->private_config);
1688 free(cortex_m);
1689 }
1690
1691 int cortex_m_profiling(struct target *target, uint32_t *samples,
1692 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1693 {
1694 struct timeval timeout, now;
1695 struct armv7m_common *armv7m = target_to_armv7m(target);
1696 uint32_t reg_value;
1697 bool use_pcsr = false;
1698 int retval = ERROR_OK;
1699 struct reg *reg;
1700
1701 gettimeofday(&timeout, NULL);
1702 timeval_add_time(&timeout, seconds, 0);
1703
1704 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1705 if (retval != ERROR_OK) {
1706 LOG_ERROR("Error while reading PCSR");
1707 return retval;
1708 }
1709
1710 if (reg_value != 0) {
1711 use_pcsr = true;
1712 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1713 } else {
1714 LOG_INFO("Starting profiling. Halting and resuming the"
1715 " target as often as we can...");
1716 reg = register_get_by_name(target->reg_cache, "pc", 1);
1717 }
1718
1719 /* Make sure the target is running */
1720 target_poll(target);
1721 if (target->state == TARGET_HALTED)
1722 retval = target_resume(target, 1, 0, 0, 0);
1723
1724 if (retval != ERROR_OK) {
1725 LOG_ERROR("Error while resuming target");
1726 return retval;
1727 }
1728
1729 uint32_t sample_count = 0;
1730
1731 for (;;) {
1732 if (use_pcsr) {
1733 if (armv7m && armv7m->debug_ap) {
1734 uint32_t read_count = max_num_samples - sample_count;
1735 if (read_count > 1024)
1736 read_count = 1024;
1737
1738 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1739 (void *)&samples[sample_count],
1740 4, read_count, DWT_PCSR);
1741 sample_count += read_count;
1742 } else {
1743 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1744 }
1745 } else {
1746 target_poll(target);
1747 if (target->state == TARGET_HALTED) {
1748 reg_value = buf_get_u32(reg->value, 0, 32);
1749 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1750 retval = target_resume(target, 1, 0, 0, 0);
1751 samples[sample_count++] = reg_value;
1752 target_poll(target);
1753 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1754 } else if (target->state == TARGET_RUNNING) {
1755 /* We want to quickly sample the PC. */
1756 retval = target_halt(target);
1757 } else {
1758 LOG_INFO("Target not halted or running");
1759 retval = ERROR_OK;
1760 break;
1761 }
1762 }
1763
1764 if (retval != ERROR_OK) {
1765 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1766 return retval;
1767 }
1768
1769
1770 gettimeofday(&now, NULL);
1771 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1772 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1773 break;
1774 }
1775 }
1776
1777 *num_samples = sample_count;
1778 return retval;
1779 }
1780
1781
1782 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1783 * on r/w if the core is not running, and clear on resume or reset ... or
1784 * at least, in a post_restore_context() method.
1785 */
1786
1787 struct dwt_reg_state {
1788 struct target *target;
1789 uint32_t addr;
1790 uint8_t value[4]; /* scratch/cache */
1791 };
1792
1793 static int cortex_m_dwt_get_reg(struct reg *reg)
1794 {
1795 struct dwt_reg_state *state = reg->arch_info;
1796
1797 uint32_t tmp;
1798 int retval = target_read_u32(state->target, state->addr, &tmp);
1799 if (retval != ERROR_OK)
1800 return retval;
1801
1802 buf_set_u32(state->value, 0, 32, tmp);
1803 return ERROR_OK;
1804 }
1805
1806 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1807 {
1808 struct dwt_reg_state *state = reg->arch_info;
1809
1810 return target_write_u32(state->target, state->addr,
1811 buf_get_u32(buf, 0, reg->size));
1812 }
1813
1814 struct dwt_reg {
1815 uint32_t addr;
1816 const char *name;
1817 unsigned size;
1818 };
1819
1820 static const struct dwt_reg dwt_base_regs[] = {
1821 { DWT_CTRL, "dwt_ctrl", 32, },
1822 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1823 * increments while the core is asleep.
1824 */
1825 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1826 /* plus some 8 bit counters, useful for profiling with TPIU */
1827 };
1828
1829 static const struct dwt_reg dwt_comp[] = {
1830 #define DWT_COMPARATOR(i) \
1831 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1832 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1833 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1834 DWT_COMPARATOR(0),
1835 DWT_COMPARATOR(1),
1836 DWT_COMPARATOR(2),
1837 DWT_COMPARATOR(3),
1838 DWT_COMPARATOR(4),
1839 DWT_COMPARATOR(5),
1840 DWT_COMPARATOR(6),
1841 DWT_COMPARATOR(7),
1842 DWT_COMPARATOR(8),
1843 DWT_COMPARATOR(9),
1844 DWT_COMPARATOR(10),
1845 DWT_COMPARATOR(11),
1846 DWT_COMPARATOR(12),
1847 DWT_COMPARATOR(13),
1848 DWT_COMPARATOR(14),
1849 DWT_COMPARATOR(15),
1850 #undef DWT_COMPARATOR
1851 };
1852
1853 static const struct reg_arch_type dwt_reg_type = {
1854 .get = cortex_m_dwt_get_reg,
1855 .set = cortex_m_dwt_set_reg,
1856 };
1857
1858 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1859 {
1860 struct dwt_reg_state *state;
1861
1862 state = calloc(1, sizeof *state);
1863 if (!state)
1864 return;
1865 state->addr = d->addr;
1866 state->target = t;
1867
1868 r->name = d->name;
1869 r->size = d->size;
1870 r->value = state->value;
1871 r->arch_info = state;
1872 r->type = &dwt_reg_type;
1873 }
1874
1875 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1876 {
1877 uint32_t dwtcr;
1878 struct reg_cache *cache;
1879 struct cortex_m_dwt_comparator *comparator;
1880 int reg, i;
1881
1882 target_read_u32(target, DWT_CTRL, &dwtcr);
1883 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1884 if (!dwtcr) {
1885 LOG_DEBUG("no DWT");
1886 return;
1887 }
1888
1889 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1890 cm->dwt_comp_available = cm->dwt_num_comp;
1891 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1892 sizeof(struct cortex_m_dwt_comparator));
1893 if (!cm->dwt_comparator_list) {
1894 fail0:
1895 cm->dwt_num_comp = 0;
1896 LOG_ERROR("out of mem");
1897 return;
1898 }
1899
1900 cache = calloc(1, sizeof *cache);
1901 if (!cache) {
1902 fail1:
1903 free(cm->dwt_comparator_list);
1904 goto fail0;
1905 }
1906 cache->name = "Cortex-M DWT registers";
1907 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1908 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1909 if (!cache->reg_list) {
1910 free(cache);
1911 goto fail1;
1912 }
1913
1914 for (reg = 0; reg < 2; reg++)
1915 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1916 dwt_base_regs + reg);
1917
1918 comparator = cm->dwt_comparator_list;
1919 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1920 int j;
1921
1922 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1923 for (j = 0; j < 3; j++, reg++)
1924 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1925 dwt_comp + 3 * i + j);
1926
1927 /* make sure we clear any watchpoints enabled on the target */
1928 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1929 }
1930
1931 *register_get_last_cache_p(&target->reg_cache) = cache;
1932 cm->dwt_cache = cache;
1933
1934 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1935 dwtcr, cm->dwt_num_comp,
1936 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1937
1938 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1939 * implement single-address data value watchpoints ... so we
1940 * won't need to check it later, when asked to set one up.
1941 */
1942 }
1943
1944 static void cortex_m_dwt_free(struct target *target)
1945 {
1946 struct cortex_m_common *cm = target_to_cm(target);
1947 struct reg_cache *cache = cm->dwt_cache;
1948
1949 free(cm->dwt_comparator_list);
1950 cm->dwt_comparator_list = NULL;
1951 cm->dwt_num_comp = 0;
1952
1953 if (cache) {
1954 register_unlink_cache(&target->reg_cache, cache);
1955
1956 if (cache->reg_list) {
1957 for (size_t i = 0; i < cache->num_regs; i++)
1958 free(cache->reg_list[i].arch_info);
1959 free(cache->reg_list);
1960 }
1961 free(cache);
1962 }
1963 cm->dwt_cache = NULL;
1964 }
1965
1966 #define MVFR0 0xe000ef40
1967 #define MVFR1 0xe000ef44
1968
1969 #define MVFR0_DEFAULT_M4 0x10110021
1970 #define MVFR1_DEFAULT_M4 0x11000011
1971
1972 #define MVFR0_DEFAULT_M7_SP 0x10110021
1973 #define MVFR0_DEFAULT_M7_DP 0x10110221
1974 #define MVFR1_DEFAULT_M7_SP 0x11000011
1975 #define MVFR1_DEFAULT_M7_DP 0x12000011
1976
1977 int cortex_m_examine(struct target *target)
1978 {
1979 int retval;
1980 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1981 int i;
1982 struct cortex_m_common *cortex_m = target_to_cm(target);
1983 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1984 struct armv7m_common *armv7m = target_to_armv7m(target);
1985
1986 /* stlink shares the examine handler but does not support
1987 * all its calls */
1988 if (!armv7m->stlink) {
1989 if (cortex_m->apsel == DP_APSEL_INVALID) {
1990 /* Search for the MEM-AP */
1991 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
1992 if (retval != ERROR_OK) {
1993 LOG_ERROR("Could not find MEM-AP to control the core");
1994 return retval;
1995 }
1996 } else {
1997 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1998 }
1999
2000 /* Leave (only) generic DAP stuff for debugport_init(); */
2001 armv7m->debug_ap->memaccess_tck = 8;
2002
2003 retval = mem_ap_init(armv7m->debug_ap);
2004 if (retval != ERROR_OK)
2005 return retval;
2006 }
2007
2008 if (!target_was_examined(target)) {
2009 target_set_examined(target);
2010
2011 /* Read from Device Identification Registers */
2012 retval = target_read_u32(target, CPUID, &cpuid);
2013 if (retval != ERROR_OK)
2014 return retval;
2015
2016 /* Get CPU Type */
2017 i = (cpuid >> 4) & 0xf;
2018
2019 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2020 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2021 if (i == 7) {
2022 uint8_t rev, patch;
2023 rev = (cpuid >> 20) & 0xf;
2024 patch = (cpuid >> 0) & 0xf;
2025 if ((rev == 0) && (patch < 2))
2026 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2027 }
2028 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2029
2030 if (i == 4) {
2031 target_read_u32(target, MVFR0, &mvfr0);
2032 target_read_u32(target, MVFR1, &mvfr1);
2033
2034 /* test for floating point feature on Cortex-M4 */
2035 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2036 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2037 armv7m->fp_feature = FPv4_SP;
2038 }
2039 } else if (i == 7) {
2040 target_read_u32(target, MVFR0, &mvfr0);
2041 target_read_u32(target, MVFR1, &mvfr1);
2042
2043 /* test for floating point features on Cortex-M7 */
2044 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2045 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2046 armv7m->fp_feature = FPv5_SP;
2047 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2048 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2049 armv7m->fp_feature = FPv5_DP;
2050 }
2051 } else if (i == 0) {
2052 /* Cortex-M0 does not support unaligned memory access */
2053 armv7m->arm.is_armv6m = true;
2054 }
2055
2056 if (armv7m->fp_feature == FP_NONE &&
2057 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2058 /* free unavailable FPU registers */
2059 size_t idx;
2060
2061 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2062 idx < armv7m->arm.core_cache->num_regs;
2063 idx++) {
2064 free(armv7m->arm.core_cache->reg_list[idx].value);
2065 free(armv7m->arm.core_cache->reg_list[idx].feature);
2066 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2067 }
2068 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2069 }
2070
2071 if (!armv7m->stlink) {
2072 if (i == 3 || i == 4)
2073 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2074 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2075 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2076 else if (i == 7)
2077 /* Cortex-M7 has only 1024 bytes autoincrement range */
2078 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2079 }
2080
2081 /* Configure trace modules */
2082 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2083 if (retval != ERROR_OK)
2084 return retval;
2085
2086 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2087 armv7m_trace_tpiu_config(target);
2088 armv7m_trace_itm_config(target);
2089 }
2090
2091 /* NOTE: FPB and DWT are both optional. */
2092
2093 /* Setup FPB */
2094 target_read_u32(target, FP_CTRL, &fpcr);
2095 /* bits [14:12] and [7:4] */
2096 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2097 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2098 cortex_m->fp_code_available = cortex_m->fp_num_code;
2099 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2100 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2101 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2102 free(cortex_m->fp_comparator_list);
2103 cortex_m->fp_comparator_list = calloc(
2104 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2105 sizeof(struct cortex_m_fp_comparator));
2106 cortex_m->fpb_enabled = fpcr & 1;
2107 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2108 cortex_m->fp_comparator_list[i].type =
2109 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2110 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2111
2112 /* make sure we clear any breakpoints enabled on the target */
2113 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2114 }
2115 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2116 fpcr,
2117 cortex_m->fp_num_code,
2118 cortex_m->fp_num_lit);
2119
2120 /* Setup DWT */
2121 cortex_m_dwt_free(target);
2122 cortex_m_dwt_setup(cortex_m, target);
2123
2124 /* These hardware breakpoints only work for code in flash! */
2125 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2126 target_name(target),
2127 cortex_m->fp_num_code,
2128 cortex_m->dwt_num_comp);
2129 }
2130
2131 return ERROR_OK;
2132 }
2133
2134 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2135 {
2136 struct armv7m_common *armv7m = target_to_armv7m(target);
2137 uint16_t dcrdr;
2138 uint8_t buf[2];
2139 int retval;
2140
2141 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2142 if (retval != ERROR_OK)
2143 return retval;
2144
2145 dcrdr = target_buffer_get_u16(target, buf);
2146 *ctrl = (uint8_t)dcrdr;
2147 *value = (uint8_t)(dcrdr >> 8);
2148
2149 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2150
2151 /* write ack back to software dcc register
2152 * signify we have read data */
2153 if (dcrdr & (1 << 0)) {
2154 target_buffer_set_u16(target, buf, 0);
2155 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2156 if (retval != ERROR_OK)
2157 return retval;
2158 }
2159
2160 return ERROR_OK;
2161 }
2162
2163 static int cortex_m_target_request_data(struct target *target,
2164 uint32_t size, uint8_t *buffer)
2165 {
2166 uint8_t data;
2167 uint8_t ctrl;
2168 uint32_t i;
2169
2170 for (i = 0; i < (size * 4); i++) {
2171 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2172 if (retval != ERROR_OK)
2173 return retval;
2174 buffer[i] = data;
2175 }
2176
2177 return ERROR_OK;
2178 }
2179
2180 static int cortex_m_handle_target_request(void *priv)
2181 {
2182 struct target *target = priv;
2183 if (!target_was_examined(target))
2184 return ERROR_OK;
2185
2186 if (!target->dbg_msg_enabled)
2187 return ERROR_OK;
2188
2189 if (target->state == TARGET_RUNNING) {
2190 uint8_t data;
2191 uint8_t ctrl;
2192 int retval;
2193
2194 retval = cortex_m_dcc_read(target, &data, &ctrl);
2195 if (retval != ERROR_OK)
2196 return retval;
2197
2198 /* check if we have data */
2199 if (ctrl & (1 << 0)) {
2200 uint32_t request;
2201
2202 /* we assume target is quick enough */
2203 request = data;
2204 for (int i = 1; i <= 3; i++) {
2205 retval = cortex_m_dcc_read(target, &data, &ctrl);
2206 if (retval != ERROR_OK)
2207 return retval;
2208 request |= ((uint32_t)data << (i * 8));
2209 }
2210 target_request(target, request);
2211 }
2212 }
2213
2214 return ERROR_OK;
2215 }
2216
2217 static int cortex_m_init_arch_info(struct target *target,
2218 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2219 {
2220 struct armv7m_common *armv7m = &cortex_m->armv7m;
2221
2222 armv7m_init_arch_info(target, armv7m);
2223
2224 /* default reset mode is to use srst if fitted
2225 * if not it will use CORTEX_M3_RESET_VECTRESET */
2226 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2227
2228 armv7m->arm.dap = dap;
2229
2230 /* register arch-specific functions */
2231 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2232
2233 armv7m->post_debug_entry = NULL;
2234
2235 armv7m->pre_restore_context = NULL;
2236
2237 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2238 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2239
2240 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2241
2242 return ERROR_OK;
2243 }
2244
2245 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2246 {
2247 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2248 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2249 struct adiv5_private_config *pc;
2250
2251 pc = (struct adiv5_private_config *)target->private_config;
2252 if (adiv5_verify_config(pc) != ERROR_OK)
2253 return ERROR_FAIL;
2254
2255 cortex_m->apsel = pc->ap_num;
2256
2257 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2258
2259 return ERROR_OK;
2260 }
2261
2262 /*--------------------------------------------------------------------------*/
2263
2264 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2265 struct cortex_m_common *cm)
2266 {
2267 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2268 command_print(cmd_ctx, "target is not a Cortex-M");
2269 return ERROR_TARGET_INVALID;
2270 }
2271 return ERROR_OK;
2272 }
2273
2274 /*
2275 * Only stuff below this line should need to verify that its target
2276 * is a Cortex-M3. Everything else should have indirected through the
2277 * cortexm3_target structure, which is only used with CM3 targets.
2278 */
2279
2280 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2281 {
2282 struct target *target = get_current_target(CMD_CTX);
2283 struct cortex_m_common *cortex_m = target_to_cm(target);
2284 struct armv7m_common *armv7m = &cortex_m->armv7m;
2285 uint32_t demcr = 0;
2286 int retval;
2287
2288 static const struct {
2289 char name[10];
2290 unsigned mask;
2291 } vec_ids[] = {
2292 { "hard_err", VC_HARDERR, },
2293 { "int_err", VC_INTERR, },
2294 { "bus_err", VC_BUSERR, },
2295 { "state_err", VC_STATERR, },
2296 { "chk_err", VC_CHKERR, },
2297 { "nocp_err", VC_NOCPERR, },
2298 { "mm_err", VC_MMERR, },
2299 { "reset", VC_CORERESET, },
2300 };
2301
2302 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2303 if (retval != ERROR_OK)
2304 return retval;
2305
2306 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2307 if (retval != ERROR_OK)
2308 return retval;
2309
2310 if (CMD_ARGC > 0) {
2311 unsigned catch = 0;
2312
2313 if (CMD_ARGC == 1) {
2314 if (strcmp(CMD_ARGV[0], "all") == 0) {
2315 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2316 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2317 | VC_MMERR | VC_CORERESET;
2318 goto write;
2319 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2320 goto write;
2321 }
2322 while (CMD_ARGC-- > 0) {
2323 unsigned i;
2324 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2325 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2326 continue;
2327 catch |= vec_ids[i].mask;
2328 break;
2329 }
2330 if (i == ARRAY_SIZE(vec_ids)) {
2331 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2332 return ERROR_COMMAND_SYNTAX_ERROR;
2333 }
2334 }
2335 write:
2336 /* For now, armv7m->demcr only stores vector catch flags. */
2337 armv7m->demcr = catch;
2338
2339 demcr &= ~0xffff;
2340 demcr |= catch;
2341
2342 /* write, but don't assume it stuck (why not??) */
2343 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2344 if (retval != ERROR_OK)
2345 return retval;
2346 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2347 if (retval != ERROR_OK)
2348 return retval;
2349
2350 /* FIXME be sure to clear DEMCR on clean server shutdown.
2351 * Otherwise the vector catch hardware could fire when there's
2352 * no debugger hooked up, causing much confusion...
2353 */
2354 }
2355
2356 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2357 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2358 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2359 }
2360
2361 return ERROR_OK;
2362 }
2363
2364 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2365 {
2366 struct target *target = get_current_target(CMD_CTX);
2367 struct cortex_m_common *cortex_m = target_to_cm(target);
2368 int retval;
2369
2370 static const Jim_Nvp nvp_maskisr_modes[] = {
2371 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2372 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2373 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2374 { .name = NULL, .value = -1 },
2375 };
2376 const Jim_Nvp *n;
2377
2378
2379 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2380 if (retval != ERROR_OK)
2381 return retval;
2382
2383 if (target->state != TARGET_HALTED) {
2384 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2385 return ERROR_OK;
2386 }
2387
2388 if (CMD_ARGC > 0) {
2389 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2390 if (n->name == NULL)
2391 return ERROR_COMMAND_SYNTAX_ERROR;
2392 cortex_m->isrmasking_mode = n->value;
2393
2394
2395 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2396 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2397 else
2398 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2399 }
2400
2401 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2402 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2403
2404 return ERROR_OK;
2405 }
2406
2407 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2408 {
2409 struct target *target = get_current_target(CMD_CTX);
2410 struct cortex_m_common *cortex_m = target_to_cm(target);
2411 int retval;
2412 char *reset_config;
2413
2414 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2415 if (retval != ERROR_OK)
2416 return retval;
2417
2418 if (CMD_ARGC > 0) {
2419 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2420 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2421 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2422 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2423 }
2424
2425 switch (cortex_m->soft_reset_config) {
2426 case CORTEX_M_RESET_SYSRESETREQ:
2427 reset_config = "sysresetreq";
2428 break;
2429
2430 case CORTEX_M_RESET_VECTRESET:
2431 reset_config = "vectreset";
2432 break;
2433
2434 default:
2435 reset_config = "unknown";
2436 break;
2437 }
2438
2439 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2440
2441 return ERROR_OK;
2442 }
2443
2444 static const struct command_registration cortex_m_exec_command_handlers[] = {
2445 {
2446 .name = "maskisr",
2447 .handler = handle_cortex_m_mask_interrupts_command,
2448 .mode = COMMAND_EXEC,
2449 .help = "mask cortex_m interrupts",
2450 .usage = "['auto'|'on'|'off']",
2451 },
2452 {
2453 .name = "vector_catch",
2454 .handler = handle_cortex_m_vector_catch_command,
2455 .mode = COMMAND_EXEC,
2456 .help = "configure hardware vectors to trigger debug entry",
2457 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2458 },
2459 {
2460 .name = "reset_config",
2461 .handler = handle_cortex_m_reset_config_command,
2462 .mode = COMMAND_ANY,
2463 .help = "configure software reset handling",
2464 .usage = "['srst'|'sysresetreq'|'vectreset']",
2465 },
2466 COMMAND_REGISTRATION_DONE
2467 };
2468 static const struct command_registration cortex_m_command_handlers[] = {
2469 {
2470 .chain = armv7m_command_handlers,
2471 },
2472 {
2473 .chain = armv7m_trace_command_handlers,
2474 },
2475 {
2476 .name = "cortex_m",
2477 .mode = COMMAND_EXEC,
2478 .help = "Cortex-M command group",
2479 .usage = "",
2480 .chain = cortex_m_exec_command_handlers,
2481 },
2482 COMMAND_REGISTRATION_DONE
2483 };
2484
2485 struct target_type cortexm_target = {
2486 .name = "cortex_m",
2487 .deprecated_name = "cortex_m3",
2488
2489 .poll = cortex_m_poll,
2490 .arch_state = armv7m_arch_state,
2491
2492 .target_request_data = cortex_m_target_request_data,
2493
2494 .halt = cortex_m_halt,
2495 .resume = cortex_m_resume,
2496 .step = cortex_m_step,
2497
2498 .assert_reset = cortex_m_assert_reset,
2499 .deassert_reset = cortex_m_deassert_reset,
2500 .soft_reset_halt = cortex_m_soft_reset_halt,
2501
2502 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2503
2504 .read_memory = cortex_m_read_memory,
2505 .write_memory = cortex_m_write_memory,
2506 .checksum_memory = armv7m_checksum_memory,
2507 .blank_check_memory = armv7m_blank_check_memory,
2508
2509 .run_algorithm = armv7m_run_algorithm,
2510 .start_algorithm = armv7m_start_algorithm,
2511 .wait_algorithm = armv7m_wait_algorithm,
2512
2513 .add_breakpoint = cortex_m_add_breakpoint,
2514 .remove_breakpoint = cortex_m_remove_breakpoint,
2515 .add_watchpoint = cortex_m_add_watchpoint,
2516 .remove_watchpoint = cortex_m_remove_watchpoint,
2517
2518 .commands = cortex_m_command_handlers,
2519 .target_create = cortex_m_target_create,
2520 .target_jim_configure = adiv5_jim_configure,
2521 .init_target = cortex_m_init_target,
2522 .examine = cortex_m_examine,
2523 .deinit_target = cortex_m_deinit_target,
2524
2525 .profiling = cortex_m_profiling,
2526 };
Official OpenOCD Mirror