TARGET: fix handling return code of MMU translation
[openocd.git] / src / flash / nor / stellaris.h
bloba469323505a5d42af39535b0dd7f4fc095cea344
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef STELLARIS_FLASH_H
21 #define STELLARIS_FLASH_H
23 struct stellaris_flash_bank
25 /* chip id register */
26 uint32_t did0;
27 uint32_t did1;
28 uint32_t dc0;
29 uint32_t dc1;
31 char * target_name;
33 uint32_t sramsiz;
34 uint32_t flshsz;
35 /* flash geometry */
36 uint32_t num_pages;
37 uint32_t pagesize;
38 uint32_t pages_in_lockregion;
40 /* nv memory bits */
41 uint16_t num_lockbits;
43 /* main clock status */
44 uint32_t rcc;
45 uint32_t rcc2;
46 uint8_t mck_valid;
47 uint8_t xtal_mask;
48 uint32_t iosc_freq;
49 uint32_t mck_freq;
50 const char *iosc_desc;
51 const char *mck_desc;
54 /* STELLARIS control registers */
55 #define SCB_BASE 0x400FE000
56 #define DID0 0x000
57 #define DID1 0x004
58 #define DC0 0x008
59 #define DC1 0x010
60 #define DC2 0x014
61 #define DC3 0x018
62 #define DC4 0x01C
64 #define RIS 0x050
65 #define RCC 0x060
66 #define PLLCFG 0x064
67 #define RCC2 0x070
68 #define NVMSTAT 0x1a0
70 /* "legacy" flash memory protection registers (64KB max) */
71 #define FMPRE 0x130
72 #define FMPPE 0x134
74 /* new flash memory protection registers (for more than 64KB) */
75 #define FMPRE0 0x200 /* PRE1 = PRE0 + 4, etc */
76 #define FMPPE0 0x400 /* PPE1 = PPE0 + 4, etc */
78 #define USECRL 0x140
80 #define FLASH_CONTROL_BASE 0x400FD000
81 #define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
82 #define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
83 #define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
84 #define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
85 #define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
86 #define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
88 #define AMISC 1
89 #define PMISC 2
91 #define AMASK 1
92 #define PMASK 2
94 /* Flash Controller Command bits */
95 #define FMC_WRKEY (0xA442 << 16)
96 #define FMC_COMT (1 << 3)
97 #define FMC_MERASE (1 << 2)
98 #define FMC_ERASE (1 << 1)
99 #define FMC_WRITE (1 << 0)
101 /* STELLARIS constants */
103 /* values to write in FMA to commit write-"once" values */
104 #define FLASH_FMA_PRE(x) (2 * (x)) /* for FMPPREx */
105 #define FLASH_FMA_PPE(x) (2 * (x) + 1) /* for FMPPPEx */
107 #endif /* STELLARIS_H */