ARMv7-M: start using "struct arm"
[openocd.git] / src / target / arm.h
blobc72b194267b0a8f12ddc3b9086b17d89288ed2bb
1 /*
2 * Copyright (C) 2005 by Dominic Rath
3 * Dominic.Rath@gmx.de
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #ifndef ARM_H
27 #define ARM_H
29 #include <helper/command.h>
30 #include "target.h"
33 /**
34 * @file
35 * Holds the interface to ARM cores.
37 * At this writing, only "classic ARM" cores built on the ARMv4 register
38 * and mode model are supported. The Thumb2-only microcontroller profile
39 * support has not yet been integrated, affecting Cortex-M parts.
42 /**
43 * Represent state of an ARM core.
45 * Most numbers match the five low bits of the *PSR registers on
46 * "classic ARM" processors, which build on the ARMv4 processor
47 * modes and register set.
49 * ARM_MODE_ANY is a magic value, often used as a wildcard.
51 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
52 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
53 * they support.
55 enum arm_mode {
56 ARM_MODE_USR = 16,
57 ARM_MODE_FIQ = 17,
58 ARM_MODE_IRQ = 18,
59 ARM_MODE_SVC = 19,
60 ARM_MODE_ABT = 23,
61 ARM_MODE_MON = 26,
62 ARM_MODE_UND = 27,
63 ARM_MODE_SYS = 31,
65 ARM_MODE_THREAD,
66 ARM_MODE_USER_THREAD,
67 ARM_MODE_HANDLER,
69 ARM_MODE_ANY = -1
72 const char *arm_mode_name(unsigned psr_mode);
73 bool is_arm_mode(unsigned psr_mode);
75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
76 enum arm_state {
77 ARM_STATE_ARM,
78 ARM_STATE_THUMB,
79 ARM_STATE_JAZELLE,
80 ARM_STATE_THUMB_EE,
83 extern const char *arm_state_strings[];
85 #define ARM_COMMON_MAGIC 0x0A450A45
87 /**
88 * Represents a generic ARM core, with standard application registers.
90 * There are sixteen application registers (including PC, SP, LR) and a PSR.
91 * Cortex-M series cores do not support as many core states or shadowed
92 * registers as traditional ARM cores, and only support Thumb2 instructions.
94 struct arm {
95 int common_magic;
96 struct reg_cache *core_cache;
98 /** Handle to the CPSR; valid in all core modes. */
99 struct reg *cpsr;
101 /** Handle to the SPSR; valid only in core modes with an SPSR. */
102 struct reg *spsr;
104 /** Support for arm_reg_current() */
105 const int *map;
108 * Indicates what registers are in the ARM state core register set.
109 * ARM_MODE_ANY indicates the standard set of 37 registers,
110 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
111 * more registers are shadowed, for "Secure Monitor" mode.
112 * ARM_MODE_THREAD indicates a microcontroller profile core,
113 * which only shadows SP.
115 enum arm_mode core_type;
117 /** Record the current core mode: SVC, USR, or some other mode. */
118 enum arm_mode core_mode;
120 /** Record the current core state: ARM, Thumb, or otherwise. */
121 enum arm_state core_state;
123 /** Flag reporting unavailability of the BKPT instruction. */
124 bool is_armv4;
126 /** Flag reporting whether semihosting is active. */
127 bool is_semihosting;
129 /** Value to be returned by semihosting SYS_ERRNO request. */
130 int semihosting_errno;
132 /** Backpointer to the target. */
133 struct target *target;
135 /** Handle for the debug module, if one is present. */
136 struct arm_dpm *dpm;
138 /** Handle for the Embedded Trace Module, if one is present. */
139 struct etm_context *etm;
141 /* FIXME all these methods should take "struct arm *" not target */
143 /** Retrieve all core registers, for display. */
144 int (*full_context)(struct target *target);
146 /** Retrieve a single core register. */
147 int (*read_core_reg)(struct target *target, struct reg *reg,
148 int num, enum arm_mode mode);
149 int (*write_core_reg)(struct target *target, struct reg *reg,
150 int num, enum arm_mode mode, uint32_t value);
152 /** Read coprocessor register. */
153 int (*mrc)(struct target *target, int cpnum,
154 uint32_t op1, uint32_t op2,
155 uint32_t CRn, uint32_t CRm,
156 uint32_t *value);
158 /** Write coprocessor register. */
159 int (*mcr)(struct target *target, int cpnum,
160 uint32_t op1, uint32_t op2,
161 uint32_t CRn, uint32_t CRm,
162 uint32_t value);
164 void *arch_info;
167 /** Convert target handle to generic ARM target state handle. */
168 static inline struct arm *target_to_arm(struct target *target)
170 return target->arch_info;
173 static inline bool is_arm(struct arm *arm)
175 return arm && arm->common_magic == ARM_COMMON_MAGIC;
178 struct arm_algorithm {
179 int common_magic;
181 enum arm_mode core_mode;
182 enum arm_state core_state;
185 struct arm_reg {
186 int num;
187 enum arm_mode mode;
188 struct target *target;
189 struct arm *armv4_5_common;
190 uint32_t value;
193 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
195 extern const struct command_registration arm_command_handlers[];
197 int arm_arch_state(struct target *target);
198 int arm_get_gdb_reg_list(struct target *target,
199 struct reg **reg_list[], int *reg_list_size);
201 int arm_init_arch_info(struct target *target, struct arm *arm);
203 /* REVISIT rename this once it's usable by ARMv7-M */
204 int armv4_5_run_algorithm(struct target *target,
205 int num_mem_params, struct mem_param *mem_params,
206 int num_reg_params, struct reg_param *reg_params,
207 uint32_t entry_point, uint32_t exit_point,
208 int timeout_ms, void *arch_info);
209 int armv4_5_run_algorithm_inner(struct target *target,
210 int num_mem_params, struct mem_param *mem_params,
211 int num_reg_params, struct reg_param *reg_params,
212 uint32_t entry_point, uint32_t exit_point,
213 int timeout_ms, void *arch_info,
214 int (*run_it)(struct target *target, uint32_t exit_point,
215 int timeout_ms, void *arch_info));
217 int arm_checksum_memory(struct target *target,
218 uint32_t address, uint32_t count, uint32_t *checksum);
219 int arm_blank_check_memory(struct target *target,
220 uint32_t address, uint32_t count, uint32_t *blank);
222 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
223 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
225 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
227 extern struct reg arm_gdb_dummy_fp_reg;
228 extern struct reg arm_gdb_dummy_fps_reg;
230 #endif /* ARM_H */