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target|board: Add Intel (Altera) Arria 10 target and related board
[openocd.git]
/
tcl
/
board
/
avnet_ultrazed-eg.cfg
blob
a0ac5c6a743b21bbea77c96263b00d69dcb22eb2
1
#
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# AVNET UltraZED EG StarterKit
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# UlraScale-EG plus IO Carrier with on-board digilent smt2
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#
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source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
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# jtag transport only
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transport select jtag
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# reset lines are not wired
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reset_config none
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# slow default clock
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adapter_khz 1000
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set CHIPNAME uscale
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source [find target/xilinx_ultrascale.cfg]