1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_NDS32_H
20 #define OPENOCD_TARGET_NDS32_H
22 #include <jtag/jtag.h>
24 #include "target_type.h"
26 #include "breakpoints.h"
27 #include "nds32_reg.h"
28 #include "nds32_insn.h"
29 #include "nds32_edm.h"
31 #define NDS32_EDM_OPERATION_MAX_NUM 64
33 #define CHECK_RETVAL(action) \
35 int __retval = (action); \
36 if (__retval != ERROR_OK) { \
37 LOG_DEBUG("error while calling \"%s\"", \
45 * Holds the interface to Andes cores.
48 extern const char *nds32_debug_type_name
[11];
50 enum nds32_debug_reason
{
51 NDS32_DEBUG_BREAK
= 0,
53 NDS32_DEBUG_INST_BREAK
,
54 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE
,
55 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE
,
56 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE
,
57 NDS32_DEBUG_DEBUG_INTERRUPT
,
58 NDS32_DEBUG_HARDWARE_SINGLE_STEP
,
59 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE
,
60 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE
,
61 NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP
,
64 #define NDS32_STRUCT_STAT_SIZE 60
65 #define NDS32_STRUCT_TIMEVAL_SIZE 8
67 enum nds32_syscall_id
{
68 NDS32_SYSCALL_UNDEFINED
= 0,
69 NDS32_SYSCALL_EXIT
= 1,
70 NDS32_SYSCALL_OPEN
= 2,
71 NDS32_SYSCALL_CLOSE
= 3,
72 NDS32_SYSCALL_READ
= 4,
73 NDS32_SYSCALL_WRITE
= 5,
74 NDS32_SYSCALL_LSEEK
= 6,
75 NDS32_SYSCALL_UNLINK
= 7,
76 NDS32_SYSCALL_RENAME
= 3001,
77 NDS32_SYSCALL_FSTAT
= 10,
78 NDS32_SYSCALL_STAT
= 15,
79 NDS32_SYSCALL_GETTIMEOFDAY
= 19,
80 NDS32_SYSCALL_ISATTY
= 3002,
81 NDS32_SYSCALL_SYSTEM
= 3003,
82 NDS32_SYSCALL_ERRNO
= 6001,
85 #define NDS32_COMMON_MAGIC (int)0xADE5ADE5
89 /** EDM_CFG.VER, indicate the EDM version */
92 /** The number of hardware breakpoints */
95 /** EDM_CFG.DALM, indicate if direct local memory access
96 * feature is supported or not */
97 bool direct_access_local_memory
;
99 /** Support ACC_CTL register */
103 bool support_max_stop
;
108 /** enable cache or not */
111 /** cache sets per way */
117 /** cache line size */
120 /** cache locking support */
124 struct nds32_memory
{
127 struct nds32_cache icache
;
130 struct nds32_cache dcache
;
132 /** On-chip instruction local memory base */
135 /** On-chip instruction local memory size */
138 /** ILM base register alignment version */
141 /** DLM is enabled or not */
144 /** DLM start address */
147 /** DLM end address */
150 /** On-chip data local memory base */
153 /** On-chip data local memory size */
156 /** DLM base register alignment version */
159 /** DLM is enabled or not */
162 /** DLM start address */
165 /** DLM end address */
168 /** Memory access method */
169 enum nds_memory_access access_channel
;
171 /** Memory access mode */
172 enum nds_memory_select mode
;
174 /** Address translation */
175 bool address_translation
;
178 struct nds32_cpu_version
{
179 bool performance_extension
;
180 bool _16bit_extension
;
181 bool performance_extension_2
;
182 bool cop_fpu_extension
;
183 bool string_extension
;
190 struct nds32_mmu_config
{
191 int memory_protection
;
192 int memory_protection_version
;
193 bool fully_associative_tlb
;
197 bool _8k_page_support
;
198 int extra_page_size_support
;
200 bool hardware_page_table_walker
;
207 int default_min_page_size
;
208 bool multiple_page_size_in_use
;
211 struct nds32_misc_config
{
213 bool local_memory_dma
;
214 bool performance_monitor
;
215 bool high_speed_memory_port
;
217 bool div_instruction
;
218 bool mac_instruction
;
221 bool reduce_register
;
223 bool interruption_level
;
224 int baseline_instruction
;
226 bool implement_dependant_register
;
227 bool implement_dependant_sr_encoding
;
235 * Represents a generic Andes core.
239 struct reg_cache
*core_cache
;
241 /** Handle for the debug module. */
242 struct nds32_edm edm
;
244 /** Memory information */
245 struct nds32_memory memory
;
248 struct nds32_cpu_version cpu_version
;
250 /** MMU configuration */
251 struct nds32_mmu_config mmu_config
;
253 /** Misc configuration */
254 struct nds32_misc_config misc_config
;
256 /** Retrieve all core registers, for display. */
257 int (*full_context
)(struct nds32
*nds32
);
259 /** Register mappings */
260 int (*register_map
)(struct nds32
*nds32
, int reg_no
);
262 /** Get debug exception virtual address */
263 int (*get_debug_reason
)(struct nds32
*nds32
, uint32_t *reason
);
265 /** Restore target registers may be modified in debug state */
266 int (*leave_debug_state
)(struct nds32
*nds32
, bool enable_watchpoint
);
268 /** Backup target registers may be modified in debug state */
269 int (*enter_debug_state
)(struct nds32
*nds32
, bool enable_watchpoint
);
271 /** Get address hit watchpoint */
272 int (*get_watched_address
)(struct nds32
*nds32
, uint32_t *address
, uint32_t reason
);
274 /** maximum interrupt level */
275 uint32_t max_interrupt_level
;
277 /** current interrupt level */
278 uint32_t current_interrupt_level
;
280 uint32_t watched_address
;
282 /** Flag reporting whether virtual hosting is active. */
283 bool virtual_hosting
;
285 /** Flag reporting whether continue/step hits syscall or not */
288 /** Value to be returned by virtual hosting SYS_ERRNO request. */
289 int virtual_hosting_errno
;
291 /** Flag reporting whether syscall is aborted */
292 bool virtual_hosting_ctrl_c
;
294 /** Record syscall ID for other operations to do special processing for target */
295 int active_syscall_id
;
297 struct breakpoint syscall_break
;
299 /** Flag reporting whether global stop is active. */
302 /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
303 bool soft_reset_halt
;
305 /** reset-halt as target examine */
306 bool reset_halt_as_examine
;
308 /** backup/restore target EDM_CTL value. As debugging target debug
309 * handler, it should be true. */
310 bool keep_target_edm_ctl
;
312 /* Value of $EDM_CTL before target enters debug mode */
313 uint32_t backup_edm_ctl
;
315 /** always use word-aligned address to access memory */
316 bool word_access_mem
;
318 /** EDM passcode for debugging secure MCU */
321 /** current privilege_level if using secure MCU. value 0 is the highest level. */
324 /** Period to wait after SRST. */
327 /** Flag to indicate HSS steps into ISR or not */
328 bool step_isr_enable
;
330 /** Flag to indicate register table is ready or not */
331 bool init_arch_info_after_halted
;
333 /** Flag to indicate audio-extension is enabled or not */
336 /** Flag to indicate fpu-extension is enabled or not */
339 /* Andes Core has mixed endian model. Instruction is always big-endian.
340 * Data may be big or little endian. Device registers may have different
341 * endian from data and instruction. */
342 /** Endian of data memory */
343 enum target_endianness data_endian
;
345 /** Endian of device registers */
346 enum target_endianness device_reg_endian
;
348 /** Flag to indicate if auto convert software breakpoints to
349 * hardware breakpoints or not in ROM */
350 bool auto_convert_hw_bp
;
352 /* Flag to indicate the target is attached by debugger or not */
355 /** Backpointer to the target. */
356 struct target
*target
;
364 struct target
*target
;
369 struct nds32_edm_operation
{
374 extern int nds32_config(struct nds32
*nds32
);
375 extern int nds32_init_arch_info(struct target
*target
, struct nds32
*nds32
);
376 extern int nds32_full_context(struct nds32
*nds32
);
377 extern int nds32_arch_state(struct target
*target
);
378 extern int nds32_add_software_breakpoint(struct target
*target
,
379 struct breakpoint
*breakpoint
);
380 extern int nds32_remove_software_breakpoint(struct target
*target
,
381 struct breakpoint
*breakpoint
);
383 extern int nds32_get_gdb_reg_list(struct target
*target
,
384 struct reg
**reg_list
[], int *reg_list_size
,
385 enum target_register_class reg_class
);
387 extern int nds32_write_buffer(struct target
*target
, uint32_t address
,
388 uint32_t size
, const uint8_t *buffer
);
389 extern int nds32_read_buffer(struct target
*target
, uint32_t address
,
390 uint32_t size
, uint8_t *buffer
);
391 extern int nds32_read_memory(struct target
*target
, uint32_t address
,
392 uint32_t size
, uint32_t count
, uint8_t *buffer
);
393 extern int nds32_write_memory(struct target
*target
, uint32_t address
,
394 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
396 extern int nds32_init_register_table(struct nds32
*nds32
);
397 extern int nds32_init_memory_info(struct nds32
*nds32
);
398 extern int nds32_restore_context(struct target
*target
);
399 extern int nds32_get_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t *value
);
400 extern int nds32_set_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t value
);
402 extern int nds32_edm_config(struct nds32
*nds32
);
403 extern int nds32_cache_sync(struct target
*target
, target_addr_t address
, uint32_t length
);
404 extern int nds32_mmu(struct target
*target
, int *enabled
);
405 extern int nds32_virtual_to_physical(struct target
*target
, target_addr_t address
,
406 target_addr_t
*physical
);
407 extern int nds32_read_phys_memory(struct target
*target
, target_addr_t address
,
408 uint32_t size
, uint32_t count
, uint8_t *buffer
);
409 extern int nds32_write_phys_memory(struct target
*target
, target_addr_t address
,
410 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
411 extern uint32_t nds32_nextpc(struct nds32
*nds32
, int current
, uint32_t address
);
412 extern int nds32_examine_debug_reason(struct nds32
*nds32
);
413 extern int nds32_step(struct target
*target
, int current
,
414 target_addr_t address
, int handle_breakpoints
);
415 extern int nds32_target_state(struct nds32
*nds32
, enum target_state
*state
);
416 extern int nds32_halt(struct target
*target
);
417 extern int nds32_poll(struct target
*target
);
418 extern int nds32_resume(struct target
*target
, int current
,
419 target_addr_t address
, int handle_breakpoints
, int debug_execution
);
420 extern int nds32_assert_reset(struct target
*target
);
421 extern int nds32_init(struct nds32
*nds32
);
422 extern int nds32_get_gdb_fileio_info(struct target
*target
, struct gdb_fileio_info
*fileio_info
);
423 extern int nds32_gdb_fileio_write_memory(struct nds32
*nds32
, uint32_t address
,
424 uint32_t size
, const uint8_t *buffer
);
425 extern int nds32_gdb_fileio_end(struct target
*target
, int retcode
, int fileio_errno
, bool ctrl_c
);
426 extern int nds32_reset_halt(struct nds32
*nds32
);
427 extern int nds32_login(struct nds32
*nds32
);
428 extern int nds32_profiling(struct target
*target
, uint32_t *samples
,
429 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
);
431 /** Convert target handle to generic Andes target state handle. */
432 static inline struct nds32
*target_to_nds32(struct target
*target
)
434 assert(target
!= NULL
);
435 return target
->arch_info
;
439 static inline struct aice_port_s
*target_to_aice(struct target
*target
)
441 assert(target
!= NULL
);
442 return target
->tap
->priv
;
445 static inline bool is_nds32(struct nds32
*nds32
)
447 assert(nds32
!= NULL
);
448 return nds32
->common_magic
== NDS32_COMMON_MAGIC
;
451 static inline bool nds32_reach_max_interrupt_level(struct nds32
*nds32
)
453 assert(nds32
!= NULL
);
454 return nds32
->max_interrupt_level
== nds32
->current_interrupt_level
;
457 #endif /* OPENOCD_TARGET_NDS32_H */