src/flash/nand/mx3.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2009 by Alexei Babich                                   *
   5  *   Rezonans plc., Chelyabinsk, Russia                                    *
   6  *   impatt@mail.ru                                                        *
   7  ***************************************************************************/
   8
   9 #ifndef OPENOCD_FLASH_NAND_MX3_H
  10 #define OPENOCD_FLASH_NAND_MX3_H
  11
  12 /*
  13  * Freescale iMX3* OpenOCD NAND Flash controller support.
  14  *
  15  * Many thanks to Ben Dooks for writing s3c24xx driver.
  16  */
  17
  18 #define MX3_NF_BASE_ADDR                                0xb8000000
  19 #define MX3_NF_BUFSIZ                                   (MX3_NF_BASE_ADDR + 0xe00)
  20 #define MX3_NF_BUFADDR                                  (MX3_NF_BASE_ADDR + 0xe04)
  21 #define MX3_NF_FADDR                                    (MX3_NF_BASE_ADDR + 0xe06)
  22 #define MX3_NF_FCMD                                             (MX3_NF_BASE_ADDR + 0xe08)
  23 #define MX3_NF_BUFCFG                                   (MX3_NF_BASE_ADDR + 0xe0a)
  24 #define MX3_NF_ECCSTATUS                                (MX3_NF_BASE_ADDR + 0xe0c)
  25 #define MX3_NF_ECCMAINPOS                               (MX3_NF_BASE_ADDR + 0xe0e)
  26 #define MX3_NF_ECCSPAREPOS                              (MX3_NF_BASE_ADDR + 0xe10)
  27 #define MX3_NF_FWP                                              (MX3_NF_BASE_ADDR + 0xe12)
  28 #define MX3_NF_LOCKSTART                                (MX3_NF_BASE_ADDR + 0xe14)
  29 #define MX3_NF_LOCKEND                                  (MX3_NF_BASE_ADDR + 0xe16)
  30 #define MX3_NF_FWPSTATUS                                (MX3_NF_BASE_ADDR + 0xe18)
  31 /*
  32  * all bits not marked as self-clearing bit
  33  */
  34 #define MX3_NF_CFG1                                             (MX3_NF_BASE_ADDR + 0xe1a)
  35 #define MX3_NF_CFG2                                             (MX3_NF_BASE_ADDR + 0xe1c)
  36
  37 #define MX3_NF_MAIN_BUFFER0                             (MX3_NF_BASE_ADDR + 0x0000)
  38 #define MX3_NF_MAIN_BUFFER1                             (MX3_NF_BASE_ADDR + 0x0200)
  39 #define MX3_NF_MAIN_BUFFER2                             (MX3_NF_BASE_ADDR + 0x0400)
  40 #define MX3_NF_MAIN_BUFFER3                             (MX3_NF_BASE_ADDR + 0x0600)
  41 #define MX3_NF_SPARE_BUFFER0                    (MX3_NF_BASE_ADDR + 0x0800)
  42 #define MX3_NF_SPARE_BUFFER1                    (MX3_NF_BASE_ADDR + 0x0810)
  43 #define MX3_NF_SPARE_BUFFER2                    (MX3_NF_BASE_ADDR + 0x0820)
  44 #define MX3_NF_SPARE_BUFFER3                    (MX3_NF_BASE_ADDR + 0x0830)
  45 #define MX3_NF_MAIN_BUFFER_LEN                  512
  46 #define MX3_NF_SPARE_BUFFER_LEN                 16
  47 #define MX3_NF_LAST_BUFFER_ADDR                 ((MX3_NF_SPARE_BUFFER3) + MX3_NF_SPARE_BUFFER_LEN - 2)
  48
  49 /* bits in MX3_NF_CFG1 register */
  50 #define MX3_NF_BIT_SPARE_ONLY_EN                (1<<2)
  51 #define MX3_NF_BIT_ECC_EN                               (1<<3)
  52 #define MX3_NF_BIT_INT_DIS                              (1<<4)
  53 #define MX3_NF_BIT_BE_EN                                (1<<5)
  54 #define MX3_NF_BIT_RESET_EN                             (1<<6)
  55 #define MX3_NF_BIT_FORCE_CE                             (1<<7)
  56
  57 /* bits in MX3_NF_CFG2 register */
  58
  59 /*Flash Command Input*/
  60 #define MX3_NF_BIT_OP_FCI                               (1<<0)
  61 /*
  62  * Flash Address Input
  63  */
  64 #define MX3_NF_BIT_OP_FAI                               (1<<1)
  65 /*
  66  * Flash Data Input
  67  */
  68 #define MX3_NF_BIT_OP_FDI                               (1<<2)
  69
  70 /* see "enum mx_dataout_type" below */
  71 #define MX3_NF_BIT_DATAOUT_TYPE(x)              ((x)<<3)
  72 #define MX3_NF_BIT_OP_DONE                              (1<<15)
  73
  74 #define MX3_CCM_CGR2                                    0x53f80028
  75 #define MX3_GPR                                                 0x43fac008
  76 #define MX3_PCSR                                                0x53f8000c
  77
  78 enum mx_dataout_type {
  79         MX3_NF_DATAOUT_PAGE = 1,
  80         MX3_NF_DATAOUT_NANDID = 2,
  81         MX3_NF_DATAOUT_NANDSTATUS = 4,
  82 };
  83 enum mx_nf_finalize_action {
  84         MX3_NF_FIN_NONE,
  85         MX3_NF_FIN_DATAOUT,
  86 };
  87
  88 struct mx3_nf_flags {
  89         unsigned target_little_endian:1;
  90         unsigned nand_readonly:1;
  91         unsigned one_kb_sram:1;
  92         unsigned hw_ecc_enabled:1;
  93 };
  94
  95 struct mx3_nf_controller {
  96         enum mx_dataout_type optype;
  97         enum mx_nf_finalize_action fin;
  98         struct mx3_nf_flags flags;
  99 };
 100
 101 #endif /* OPENOCD_FLASH_NAND_MX3_H */