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disable polling continuous polling during reset
[openocd.git] / src / target / etb.c
blob5791e578720b795f24ae10283abb4bafc6b5bfe8
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm7_9_common.h"
25 #include "etb.h"
26
27
28 static char* etb_reg_list[] =
29 {
30 "ETB_identification",
31 "ETB_ram_depth",
32 "ETB_ram_width",
33 "ETB_status",
34 "ETB_ram_data",
35 "ETB_ram_read_pointer",
36 "ETB_ram_write_pointer",
37 "ETB_trigger_counter",
38 "ETB_control",
39 };
40
41 static int etb_reg_arch_type = -1;
42
43 static int etb_get_reg(reg_t *reg);
44
45 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46
47 static int etb_set_instr(etb_t *etb, u32 new_instr)
48 {
49 jtag_tap_t *tap;
50
51 tap = etb->tap;
52 if (tap==NULL)
53 return ERROR_FAIL;
54
55 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
56 {
57 scan_field_t field;
58
59 field.tap = tap;
60 field.num_bits = tap->ir_length;
61 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
62 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
63
64 field.in_value = NULL;
65
66 jtag_add_ir_scan(1, &field, jtag_get_end_state());
67
68 free(field.out_value);
69 }
70
71 return ERROR_OK;
72 }
73
74 static int etb_scann(etb_t *etb, u32 new_scan_chain)
75 {
76 if (etb->cur_scan_chain != new_scan_chain)
77 {
78 scan_field_t field;
79
80 field.tap = etb->tap;
81 field.num_bits = 5;
82 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
83 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
84
85 field.in_value = NULL;
86
87 /* select INTEST instruction */
88 etb_set_instr(etb, 0x2);
89 jtag_add_dr_scan(1, &field, jtag_get_end_state());
90
91 etb->cur_scan_chain = new_scan_chain;
92
93 free(field.out_value);
94 }
95
96 return ERROR_OK;
97 }
98
99 reg_cache_t* etb_build_reg_cache(etb_t *etb)
100 {
101 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
102 reg_t *reg_list = NULL;
103 etb_reg_t *arch_info = NULL;
104 int num_regs = 9;
105 int i;
106
107 /* register a register arch-type for etm registers only once */
108 if (etb_reg_arch_type == -1)
109 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
110
111 /* the actual registers are kept in two arrays */
112 reg_list = calloc(num_regs, sizeof(reg_t));
113 arch_info = calloc(num_regs, sizeof(etb_reg_t));
114
115 /* fill in values for the reg cache */
116 reg_cache->name = "etb registers";
117 reg_cache->next = NULL;
118 reg_cache->reg_list = reg_list;
119 reg_cache->num_regs = num_regs;
120
121 /* set up registers */
122 for (i = 0; i < num_regs; i++)
123 {
124 reg_list[i].name = etb_reg_list[i];
125 reg_list[i].size = 32;
126 reg_list[i].dirty = 0;
127 reg_list[i].valid = 0;
128 reg_list[i].bitfield_desc = NULL;
129 reg_list[i].num_bitfields = 0;
130 reg_list[i].value = calloc(1, 4);
131 reg_list[i].arch_info = &arch_info[i];
132 reg_list[i].arch_type = etb_reg_arch_type;
133 reg_list[i].size = 32;
134 arch_info[i].addr = i;
135 arch_info[i].etb = etb;
136 }
137
138 return reg_cache;
139 }
140
141 static int etb_get_reg(reg_t *reg)
142 {
143 int retval;
144
145 if ((retval = etb_read_reg(reg)) != ERROR_OK)
146 {
147 LOG_ERROR("BUG: error scheduling etm register read");
148 return retval;
149 }
150
151 if ((retval = jtag_execute_queue()) != ERROR_OK)
152 {
153 LOG_ERROR("register read failed");
154 return retval;
155 }
156
157 return ERROR_OK;
158 }
159
160
161 static void etb_getbuf(u8 *in)
162 {
163 *((u32 *)in)=buf_get_u32(in, 0, 32);
164 }
165
166
167 static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
168 {
169 scan_field_t fields[3];
170 int i;
171
172 jtag_set_end_state(TAP_IDLE);
173 etb_scann(etb, 0x0);
174 etb_set_instr(etb, 0xc);
175
176 fields[0].tap = etb->tap;
177 fields[0].num_bits = 32;
178 fields[0].out_value = NULL;
179 fields[0].in_value = NULL;
180
181 fields[1].tap = etb->tap;
182 fields[1].num_bits = 7;
183 fields[1].out_value = malloc(1);
184 buf_set_u32(fields[1].out_value, 0, 7, 4);
185 fields[1].in_value = NULL;
186
187 fields[2].tap = etb->tap;
188 fields[2].num_bits = 1;
189 fields[2].out_value = malloc(1);
190 buf_set_u32(fields[2].out_value, 0, 1, 0);
191 fields[2].in_value = NULL;
192
193 jtag_add_dr_scan(3, fields, jtag_get_end_state());
194
195 for (i = 0; i < num_frames; i++)
196 {
197 /* ensure nR/W reamins set to read */
198 buf_set_u32(fields[2].out_value, 0, 1, 0);
199
200 /* address remains set to 0x4 (RAM data) until we read the last frame */
201 if (i < num_frames - 1)
202 buf_set_u32(fields[1].out_value, 0, 7, 4);
203 else
204 buf_set_u32(fields[1].out_value, 0, 7, 0);
205
206 fields[0].in_value = (u8 *)(data+i);
207 jtag_add_dr_scan(3, fields, jtag_get_end_state());
208
209 jtag_add_callback(etb_getbuf, (u8 *)(data+i));
210 }
211
212 jtag_execute_queue();
213
214 free(fields[1].out_value);
215 free(fields[2].out_value);
216
217 return ERROR_OK;
218 }
219
220 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
221 {
222 etb_reg_t *etb_reg = reg->arch_info;
223 u8 reg_addr = etb_reg->addr & 0x7f;
224 scan_field_t fields[3];
225
226 LOG_DEBUG("%i", etb_reg->addr);
227
228 jtag_set_end_state(TAP_IDLE);
229 etb_scann(etb_reg->etb, 0x0);
230 etb_set_instr(etb_reg->etb, 0xc);
231
232 fields[0].tap = etb_reg->etb->tap;
233 fields[0].num_bits = 32;
234 fields[0].out_value = reg->value;
235 fields[0].in_value = NULL;
236 fields[0].check_value = NULL;
237 fields[0].check_mask = NULL;
238
239 fields[1].tap = etb_reg->etb->tap;
240 fields[1].num_bits = 7;
241 fields[1].out_value = malloc(1);
242 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
243 fields[1].in_value = NULL;
244 fields[1].check_value = NULL;
245 fields[1].check_mask = NULL;
246
247 fields[2].tap = etb_reg->etb->tap;
248 fields[2].num_bits = 1;
249 fields[2].out_value = malloc(1);
250 buf_set_u32(fields[2].out_value, 0, 1, 0);
251 fields[2].in_value = NULL;
252 fields[2].check_value = NULL;
253 fields[2].check_mask = NULL;
254
255 jtag_add_dr_scan(3, fields, jtag_get_end_state());
256
257 /* read the identification register in the second run, to make sure we
258 * don't read the ETB data register twice, skipping every second entry
259 */
260 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
261 fields[0].in_value = reg->value;
262 fields[0].check_value = check_value;
263 fields[0].check_mask = check_mask;
264
265 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
266
267 free(fields[1].out_value);
268 free(fields[2].out_value);
269
270 return ERROR_OK;
271 }
272
273 int etb_read_reg(reg_t *reg)
274 {
275 return etb_read_reg_w_check(reg, NULL, NULL);
276 }
277
278 int etb_set_reg(reg_t *reg, u32 value)
279 {
280 int retval;
281
282 if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
283 {
284 LOG_ERROR("BUG: error scheduling etm register write");
285 return retval;
286 }
287
288 buf_set_u32(reg->value, 0, reg->size, value);
289 reg->valid = 1;
290 reg->dirty = 0;
291
292 return ERROR_OK;
293 }
294
295 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
296 {
297 int retval;
298
299 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
300
301 if ((retval = jtag_execute_queue()) != ERROR_OK)
302 {
303 LOG_ERROR("register write failed");
304 return retval;
305 }
306 return ERROR_OK;
307 }
308
309 int etb_write_reg(reg_t *reg, u32 value)
310 {
311 etb_reg_t *etb_reg = reg->arch_info;
312 u8 reg_addr = etb_reg->addr & 0x7f;
313 scan_field_t fields[3];
314
315 LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
316
317 jtag_set_end_state(TAP_IDLE);
318 etb_scann(etb_reg->etb, 0x0);
319 etb_set_instr(etb_reg->etb, 0xc);
320
321 fields[0].tap = etb_reg->etb->tap;
322 fields[0].num_bits = 32;
323 fields[0].out_value = malloc(4);
324 buf_set_u32(fields[0].out_value, 0, 32, value);
325 fields[0].in_value = NULL;
326
327 fields[1].tap = etb_reg->etb->tap;
328 fields[1].num_bits = 7;
329 fields[1].out_value = malloc(1);
330 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
331 fields[1].in_value = NULL;
332
333 fields[2].tap = etb_reg->etb->tap;
334 fields[2].num_bits = 1;
335 fields[2].out_value = malloc(1);
336 buf_set_u32(fields[2].out_value, 0, 1, 1);
337
338 fields[2].in_value = NULL;
339
340 free(fields[0].out_value);
341 free(fields[1].out_value);
342 free(fields[2].out_value);
343
344 return ERROR_OK;
345 }
346
347 int etb_store_reg(reg_t *reg)
348 {
349 return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
350 }
351
352 static int etb_register_commands(struct command_context_s *cmd_ctx)
353 {
354 command_t *etb_cmd;
355
356 etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
357
358 register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
359
360 return ERROR_OK;
361 }
362
363 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
364 {
365 target_t *target;
366 jtag_tap_t *tap;
367 armv4_5_common_t *armv4_5;
368 arm7_9_common_t *arm7_9;
369
370 if (argc != 2)
371 {
372 return ERROR_COMMAND_SYNTAX_ERROR;
373 }
374
375 target = get_target(args[0]);
376
377 if (!target)
378 {
379 LOG_ERROR("target '%s' not defined", args[0]);
380 return ERROR_FAIL;
381 }
382
383 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
384 {
385 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
386 return ERROR_FAIL;
387 }
388
389 tap = jtag_tap_by_string( args[1] );
390 if (tap == NULL)
391 {
392 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
393 return ERROR_FAIL;
394 }
395
396 if (arm7_9->etm_ctx)
397 {
398 etb_t *etb = malloc(sizeof(etb_t));
399
400 arm7_9->etm_ctx->capture_driver_priv = etb;
401
402 etb->tap = tap;
403 etb->cur_scan_chain = 0xffffffff;
404 etb->reg_cache = NULL;
405 etb->ram_width = 0;
406 etb->ram_depth = 0;
407 }
408 else
409 {
410 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
411 return ERROR_FAIL;
412 }
413
414 return ERROR_OK;
415 }
416
417 static int etb_init(etm_context_t *etm_ctx)
418 {
419 etb_t *etb = etm_ctx->capture_driver_priv;
420
421 etb->etm_ctx = etm_ctx;
422
423 /* identify ETB RAM depth and width */
424 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
425 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
426 jtag_execute_queue();
427
428 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
429 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
430
431 return ERROR_OK;
432 }
433
434 static trace_status_t etb_status(etm_context_t *etm_ctx)
435 {
436 etb_t *etb = etm_ctx->capture_driver_priv;
437
438 etb->etm_ctx = etm_ctx;
439
440 /* if tracing is currently idle, return this information */
441 if (etm_ctx->capture_status == TRACE_IDLE)
442 {
443 return etm_ctx->capture_status;
444 }
445 else if (etm_ctx->capture_status & TRACE_RUNNING)
446 {
447 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
448 int etb_timeout = 100;
449
450 /* trace is running, check the ETB status flags */
451 etb_get_reg(etb_status_reg);
452
453 /* check Full bit to identify an overflow */
454 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
455 etm_ctx->capture_status |= TRACE_OVERFLOWED;
456
457 /* check Triggered bit to identify trigger condition */
458 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
459 etm_ctx->capture_status |= TRACE_TRIGGERED;
460
461 /* check AcqComp to identify trace completion */
462 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
463 {
464 while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
465 {
466 /* wait for data formatter idle */
467 etb_get_reg(etb_status_reg);
468 }
469
470 if (etb_timeout == 0)
471 {
472 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
473 buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
474 }
475
476 if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
477 {
478 LOG_ERROR("trace completed, but no trigger condition detected");
479 }
480
481 etm_ctx->capture_status &= ~TRACE_RUNNING;
482 etm_ctx->capture_status |= TRACE_COMPLETED;
483 }
484 }
485
486 return etm_ctx->capture_status;
487 }
488
489 static int etb_read_trace(etm_context_t *etm_ctx)
490 {
491 etb_t *etb = etm_ctx->capture_driver_priv;
492 int first_frame = 0;
493 int num_frames = etb->ram_depth;
494 u32 *trace_data = NULL;
495 int i, j;
496
497 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
498 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
499 jtag_execute_queue();
500
501 /* check if we overflowed, and adjust first frame of the trace accordingly
502 * if we didn't overflow, read only up to the frame that would be written next,
503 * i.e. don't read invalid entries
504 */
505 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
506 {
507 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
508 }
509 else
510 {
511 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
512 }
513
514 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
515
516 /* read data into temporary array for unpacking */
517 trace_data = malloc(sizeof(u32) * num_frames);
518 etb_read_ram(etb, trace_data, num_frames);
519
520 if (etm_ctx->trace_depth > 0)
521 {
522 free(etm_ctx->trace_data);
523 }
524
525 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
526 etm_ctx->trace_depth = num_frames * 3;
527 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
528 etm_ctx->trace_depth = num_frames * 2;
529 else
530 etm_ctx->trace_depth = num_frames;
531
532 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
533
534 for (i = 0, j = 0; i < num_frames; i++)
535 {
536 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
537 {
538 /* trace word j */
539 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
540 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
541 etm_ctx->trace_data[j].flags = 0;
542 if ((trace_data[i] & 0x80) >> 7)
543 {
544 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
545 }
546 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
547 {
548 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
549 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
550 }
551
552 /* trace word j+1 */
553 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
554 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
555 etm_ctx->trace_data[j+1].flags = 0;
556 if ((trace_data[i] & 0x8000) >> 15)
557 {
558 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
559 }
560 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
561 {
562 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
563 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
564 }
565
566 /* trace word j+2 */
567 etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
568 etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
569 etm_ctx->trace_data[j+2].flags = 0;
570 if ((trace_data[i] & 0x800000) >> 23)
571 {
572 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
573 }
574 if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
575 {
576 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
577 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
578 }
579
580 j += 3;
581 }
582 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
583 {
584 /* trace word j */
585 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
586 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
587 etm_ctx->trace_data[j].flags = 0;
588 if ((trace_data[i] & 0x800) >> 11)
589 {
590 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
591 }
592 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
593 {
594 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
595 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
596 }
597
598 /* trace word j+1 */
599 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
600 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
601 etm_ctx->trace_data[j+1].flags = 0;
602 if ((trace_data[i] & 0x800000) >> 23)
603 {
604 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
605 }
606 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
607 {
608 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
609 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
610 }
611
612 j += 2;
613 }
614 else
615 {
616 /* trace word j */
617 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
618 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
619 etm_ctx->trace_data[j].flags = 0;
620 if ((trace_data[i] & 0x80000) >> 19)
621 {
622 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
623 }
624 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
625 {
626 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
627 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
628 }
629
630 j += 1;
631 }
632 }
633
634 free(trace_data);
635
636 return ERROR_OK;
637 }
638
639 static int etb_start_capture(etm_context_t *etm_ctx)
640 {
641 etb_t *etb = etm_ctx->capture_driver_priv;
642 u32 etb_ctrl_value = 0x1;
643 u32 trigger_count;
644
645 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
646 {
647 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
648 {
649 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
650 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
651 }
652 etb_ctrl_value |= 0x2;
653 }
654
655 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
656 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
657
658 trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
659
660 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
661 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
662 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
663 jtag_execute_queue();
664
665 /* we're starting a new trace, initialize capture status */
666 etm_ctx->capture_status = TRACE_RUNNING;
667
668 return ERROR_OK;
669 }
670
671 static int etb_stop_capture(etm_context_t *etm_ctx)
672 {
673 etb_t *etb = etm_ctx->capture_driver_priv;
674 reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
675
676 etb_write_reg(etb_ctrl_reg, 0x0);
677 jtag_execute_queue();
678
679 /* trace stopped, just clear running flag, but preserve others */
680 etm_ctx->capture_status &= ~TRACE_RUNNING;
681
682 return ERROR_OK;
683 }
684
685 etm_capture_driver_t etb_capture_driver =
686 {
687 .name = "etb",
688 .register_commands = etb_register_commands,
689 .init = etb_init,
690 .status = etb_status,
691 .start_capture = etb_start_capture,
692 .stop_capture = etb_stop_capture,
693 .read_trace = etb_read_trace,
694 };
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