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Indentation and white space fixes.
[openocd.git] / src / flash / nand / mx2.c
blobfca8ea2fc70a1f15b1ab1cbcf73bce2af549869a
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 /*
26 * Freescale iMX2* OpenOCD NAND Flash controller support.
27 * based on Freescale iMX3* OpenOCD NAND Flash controller support.
28 */
29
30 /*
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
34 *
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; imx27_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
39 */
40 #ifdef HAVE_CONFIG_H
41 #include "config.h"
42 #endif
43
44 #include "imp.h"
45 #include "mx2.h"
46 #include <target/target.h>
47
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
52 */
53 #undef _MX2_PRINT_STAT
54 /* #define _MX2_PRINT_STAT */
55
56 static const char target_not_halted_err_msg[] =
57 "target must be halted to use mx2 NAND flash controller";
58 static const char data_block_size_err_msg[] =
59 "minimal granularity is one half-word, %" PRId32 " is incorrect";
60 static const char sram_buffer_bounds_err_msg[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
62 static const char get_status_register_err_msg[] = "can't get NAND status";
63 static uint32_t in_sram_address;
64 static unsigned char sign_of_sequental_byte_read;
65
66 static int initialize_nf_controller(struct nand_device *nand);
67 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
68 static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value);
69 static int poll_for_complete_op(struct target *target, const char *text);
70 static int validate_target_state(struct nand_device *nand);
71 static int do_data_output(struct nand_device *nand);
72
73 static int imx27_command(struct nand_device *nand, uint8_t command);
74 static int imx27_address(struct nand_device *nand, uint8_t address);
75
76 NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
77 {
78 struct mx2_nf_controller *mx2_nf_info;
79 int hwecc_needed;
80 int x;
81
82 mx2_nf_info = malloc(sizeof(struct mx2_nf_controller));
83 if (mx2_nf_info == NULL) {
84 LOG_ERROR("no memory for nand controller");
85 return ERROR_FAIL;
86 }
87 nand->controller_priv = mx2_nf_info;
88
89 if (CMD_ARGC < 3) {
90 LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
91 return ERROR_FAIL;
92 }
93
94 /*
95 * check hwecc requirements
96 */
97 hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
98 if (hwecc_needed == 0)
99 mx2_nf_info->flags.hw_ecc_enabled = 1;
100 else
101 mx2_nf_info->flags.hw_ecc_enabled = 0;
102
103 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
104 mx2_nf_info->fin = MX2_NF_FIN_NONE;
105 mx2_nf_info->flags.target_little_endian =
106 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
107
108 /*
109 * testing host endianness
110 */
111 x = 1;
112 if (*(char *) &x == 1)
113 mx2_nf_info->flags.host_little_endian = 1;
114 else
115 mx2_nf_info->flags.host_little_endian = 0;
116 return ERROR_OK;
117 }
118
119 static int imx27_init(struct nand_device *nand)
120 {
121 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
122 struct target *target = nand->target;
123
124 int validate_target_result;
125 uint16_t buffsize_register_content;
126 uint32_t pcsr_register_content;
127 int retval;
128 uint16_t nand_status_content;
129 /*
130 * validate target state
131 */
132 validate_target_result = validate_target_state(nand);
133 if (validate_target_result != ERROR_OK)
134 return validate_target_result;
135
136 target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content);
137 mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
138
139 target_read_u32(target, MX2_FMCR, &pcsr_register_content);
140 if (!nand->bus_width) {
141 /* bus_width not yet defined. Read it from MX2_FMCR */
142 nand->bus_width =
143 (pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8;
144 } else {
145 /* bus_width forced in soft. Sync it to MX2_FMCR */
146 pcsr_register_content |=
147 ((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000);
148 target_write_u32(target, MX2_FMCR, pcsr_register_content);
149 }
150 if (nand->bus_width == 16)
151 LOG_DEBUG("MX2_NF : bus is 16-bit width");
152 else
153 LOG_DEBUG("MX2_NF : bus is 8-bit width");
154
155 if (!nand->page_size) {
156 nand->page_size = (pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512;
157 } else {
158 pcsr_register_content |=
159 ((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000);
160 target_write_u32(target, MX2_FMCR, pcsr_register_content);
161 }
162 if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
163 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
164 "pagesize 2048 is incompatible with it");
165 } else {
166 LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
167 }
168
169 initialize_nf_controller(nand);
170
171 retval = ERROR_OK;
172 retval |= imx27_command(nand, NAND_CMD_STATUS);
173 retval |= imx27_address(nand, 0x00);
174 retval |= do_data_output(nand);
175 if (retval != ERROR_OK) {
176 LOG_ERROR(get_status_register_err_msg);
177 return ERROR_FAIL;
178 }
179 target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
180 if (!(nand_status_content & 0x0080)) {
181 LOG_INFO("NAND read-only");
182 mx2_nf_info->flags.nand_readonly = 1;
183 } else {
184 mx2_nf_info->flags.nand_readonly = 0;
185 }
186 return ERROR_OK;
187 }
188
189 static int imx27_read_data(struct nand_device *nand, void *data)
190 {
191 struct target *target = nand->target;
192 int validate_target_result;
193 int try_data_output_from_nand_chip;
194 /*
195 * validate target state
196 */
197 validate_target_result = validate_target_state(nand);
198 if (validate_target_result != ERROR_OK)
199 return validate_target_result;
200
201 /*
202 * get data from nand chip
203 */
204 try_data_output_from_nand_chip = do_data_output(nand);
205 if (try_data_output_from_nand_chip != ERROR_OK) {
206 LOG_ERROR("imx27_read_data : read data failed : '%x'",
207 try_data_output_from_nand_chip);
208 return try_data_output_from_nand_chip;
209 }
210
211 if (nand->bus_width == 16)
212 get_next_halfword_from_sram_buffer(target, data);
213 else
214 get_next_byte_from_sram_buffer(target, data);
215
216 return ERROR_OK;
217 }
218
219 static int imx27_write_data(struct nand_device *nand, uint16_t data)
220 {
221 LOG_ERROR("write_data() not implemented");
222 return ERROR_NAND_OPERATION_FAILED;
223 }
224
225 static int imx27_reset(struct nand_device *nand)
226 {
227 /*
228 * validate target state
229 */
230 int validate_target_result;
231 validate_target_result = validate_target_state(nand);
232 if (validate_target_result != ERROR_OK)
233 return validate_target_result;
234 initialize_nf_controller(nand);
235 return ERROR_OK;
236 }
237
238 static int imx27_command(struct nand_device *nand, uint8_t command)
239 {
240 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
241 struct target *target = nand->target;
242 int validate_target_result;
243 int poll_result;
244 /*
245 * validate target state
246 */
247 validate_target_result = validate_target_state(nand);
248 if (validate_target_result != ERROR_OK)
249 return validate_target_result;
250
251 switch (command) {
252 case NAND_CMD_READOOB:
253 command = NAND_CMD_READ0;
254 /* set read point for data_read() and read_block_data() to
255 * spare area in SRAM buffer
256 */
257 in_sram_address = MX2_NF_SPARE_BUFFER0;
258 break;
259 case NAND_CMD_READ1:
260 command = NAND_CMD_READ0;
261 /*
262 * offset == one half of page size
263 */
264 in_sram_address = MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
265 break;
266 default:
267 in_sram_address = MX2_NF_MAIN_BUFFER0;
268 break;
269 }
270
271 target_write_u16(target, MX2_NF_FCMD, command);
272 /*
273 * start command input operation (set MX2_NF_BIT_OP_DONE==0)
274 */
275 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI);
276 poll_result = poll_for_complete_op(target, "command");
277 if (poll_result != ERROR_OK)
278 return poll_result;
279 /*
280 * reset cursor to begin of the buffer
281 */
282 sign_of_sequental_byte_read = 0;
283 /* Handle special read command and adjust NF_CFG2(FDO) */
284 switch (command) {
285 case NAND_CMD_READID:
286 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID;
287 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
288 break;
289 case NAND_CMD_STATUS:
290 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
291 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
292 target_write_u16 (target, MX2_NF_BUFADDR, 0);
293 in_sram_address = 0;
294 break;
295 case NAND_CMD_READ0:
296 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
297 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
298 break;
299 default:
300 /* Ohter command use the default 'One page data out' FDO */
301 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
302 break;
303 }
304 return ERROR_OK;
305 }
306
307 static int imx27_address(struct nand_device *nand, uint8_t address)
308 {
309 struct target *target = nand->target;
310 int validate_target_result;
311 int poll_result;
312 /*
313 * validate target state
314 */
315 validate_target_result = validate_target_state(nand);
316 if (validate_target_result != ERROR_OK)
317 return validate_target_result;
318
319 target_write_u16(target, MX2_NF_FADDR, address);
320 /*
321 * start address input operation (set MX2_NF_BIT_OP_DONE==0)
322 */
323 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI);
324 poll_result = poll_for_complete_op(target, "address");
325 if (poll_result != ERROR_OK)
326 return poll_result;
327
328 return ERROR_OK;
329 }
330
331 static int imx27_nand_ready(struct nand_device *nand, int tout)
332 {
333 uint16_t poll_complete_status;
334 struct target *target = nand->target;
335 int validate_target_result;
336
337 /*
338 * validate target state
339 */
340 validate_target_result = validate_target_state(nand);
341 if (validate_target_result != ERROR_OK)
342 return validate_target_result;
343
344 do {
345 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
346 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
347 return tout;
348
349 alive_sleep(1);
350 }
351 while (tout-- > 0);
352 return tout;
353 }
354
355 static int imx27_write_page(struct nand_device *nand, uint32_t page,
356 uint8_t *data, uint32_t data_size,
357 uint8_t *oob, uint32_t oob_size)
358 {
359 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
360 struct target *target = nand->target;
361 int retval;
362 uint16_t nand_status_content;
363 uint16_t swap1, swap2, new_swap1;
364 int poll_result;
365 if (data_size % 2) {
366 LOG_ERROR(data_block_size_err_msg, data_size);
367 return ERROR_NAND_OPERATION_FAILED;
368 }
369 if (oob_size % 2) {
370 LOG_ERROR(data_block_size_err_msg, oob_size);
371 return ERROR_NAND_OPERATION_FAILED;
372 }
373 if (!data) {
374 LOG_ERROR("nothing to program");
375 return ERROR_NAND_OPERATION_FAILED;
376 }
377 /*
378 * validate target state
379 */
380 retval = validate_target_state(nand);
381 if (retval != ERROR_OK)
382 return retval;
383
384 in_sram_address = MX2_NF_MAIN_BUFFER0;
385 sign_of_sequental_byte_read = 0;
386 retval = ERROR_OK;
387 retval |= imx27_command(nand, NAND_CMD_SEQIN);
388 retval |= imx27_address(nand, 0); /* col */
389 retval |= imx27_address(nand, 0); /* col */
390 retval |= imx27_address(nand, page & 0xff); /* page address */
391 retval |= imx27_address(nand, (page >> 8) & 0xff); /* page address */
392 retval |= imx27_address(nand, (page >> 16) & 0xff); /* page address */
393
394 target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
395 if (oob) {
396 if (mx2_nf_info->flags.hw_ecc_enabled) {
397 /*
398 * part of spare block will be overrided by hardware
399 * ECC generator
400 */
401 LOG_DEBUG("part of spare block will be overrided "
402 "by hardware ECC generator");
403 }
404 target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size, oob);
405 }
406 /* BI-swap - work-around of imx27 NFC for NAND device with page == 2kb */
407 target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
408 if (oob) {
409 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mx2 driver");
410 return ERROR_NAND_OPERATION_FAILED;
411 }
412 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
413 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
414 swap2 = (swap1 << 8) | (swap2 & 0xFF);
415
416 target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
417 target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
418 /*
419 * start data input operation (set MX2_NF_BIT_OP_DONE==0)
420 */
421 target_write_u16(target, MX2_NF_BUFADDR, 0);
422 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
423 poll_result = poll_for_complete_op(target, "data input");
424 if (poll_result != ERROR_OK)
425 return poll_result;
426
427 target_write_u16(target, MX2_NF_BUFADDR, 1);
428 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
429 poll_result = poll_for_complete_op(target, "data input");
430 if (poll_result != ERROR_OK)
431 return poll_result;
432
433 target_write_u16(target, MX2_NF_BUFADDR, 2);
434 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
435 poll_result = poll_for_complete_op(target, "data input");
436 if (poll_result != ERROR_OK)
437 return poll_result;
438
439 target_write_u16(target, MX2_NF_BUFADDR, 3);
440 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
441 poll_result = poll_for_complete_op(target, "data input");
442 if (poll_result != ERROR_OK)
443 return poll_result;
444
445 retval |= imx27_command(nand, NAND_CMD_PAGEPROG);
446 if (retval != ERROR_OK)
447 return retval;
448
449 /*
450 * check status register
451 */
452 retval = ERROR_OK;
453 retval |= imx27_command(nand, NAND_CMD_STATUS);
454 target_write_u16 (target, MX2_NF_BUFADDR, 0);
455 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
456 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
457 retval |= do_data_output(nand);
458 if (retval != ERROR_OK) {
459 LOG_ERROR(get_status_register_err_msg);
460 return retval;
461 }
462 target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
463 if (nand_status_content & 0x0001) {
464 /*
465 * page not correctly written
466 */
467 return ERROR_NAND_OPERATION_FAILED;
468 }
469 #ifdef _MX2_PRINT_STAT
470 LOG_INFO("%d bytes newly written", data_size);
471 #endif
472 return ERROR_OK;
473 }
474
475 static int imx27_read_page(struct nand_device *nand, uint32_t page,
476 uint8_t *data, uint32_t data_size,
477 uint8_t *oob, uint32_t oob_size)
478 {
479 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
480 struct target *target = nand->target;
481 int retval;
482 uint16_t swap1, swap2, new_swap1;
483
484 if (data_size % 2) {
485 LOG_ERROR(data_block_size_err_msg, data_size);
486 return ERROR_NAND_OPERATION_FAILED;
487 }
488 if (oob_size % 2) {
489 LOG_ERROR(data_block_size_err_msg, oob_size);
490 return ERROR_NAND_OPERATION_FAILED;
491 }
492
493 /*
494 * validate target state
495 */
496 retval = validate_target_state(nand);
497 if (retval != ERROR_OK) {
498 return retval;
499 }
500 /* Reset address_cycles before imx27_command ?? */
501 retval = imx27_command(nand, NAND_CMD_READ0);
502 if (retval != ERROR_OK) return retval;
503 retval = imx27_address(nand, 0); /* col */
504 if (retval != ERROR_OK) return retval;
505 retval = imx27_address(nand, 0); /* col */
506 if (retval != ERROR_OK) return retval;
507 retval = imx27_address(nand, page & 0xff); /* page address */
508 if (retval != ERROR_OK) return retval;
509 retval = imx27_address(nand, (page >> 8) & 0xff); /* page address */
510 if (retval != ERROR_OK) return retval;
511 retval = imx27_address(nand, (page >> 16) & 0xff); /* page address */
512 if (retval != ERROR_OK) return retval;
513 retval = imx27_command(nand, NAND_CMD_READSTART);
514 if (retval != ERROR_OK) return retval;
515
516 target_write_u16(target, MX2_NF_BUFADDR, 0);
517 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
518 retval = do_data_output(nand);
519 if (retval != ERROR_OK) {
520 LOG_ERROR("MX2_NF : Error reading page 0");
521 return retval;
522 }
523 /* Test nand page size to know how much MAIN_BUFFER must be written */
524 target_write_u16(target, MX2_NF_BUFADDR, 1);
525 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
526 retval = do_data_output(nand);
527 if (retval != ERROR_OK) {
528 LOG_ERROR("MX2_NF : Error reading page 1");
529 return retval;
530 }
531 target_write_u16(target, MX2_NF_BUFADDR, 2);
532 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
533 retval = do_data_output(nand);
534 if (retval != ERROR_OK) {
535 LOG_ERROR("MX2_NF : Error reading page 2");
536 return retval;
537 }
538 target_write_u16(target, MX2_NF_BUFADDR, 3);
539 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
540 retval = do_data_output(nand);
541 if (retval != ERROR_OK) {
542 LOG_ERROR("MX2_NF : Error reading page 3");
543 return retval;
544 }
545 /* BI-swap - work-around of imx27 NFC for NAND device with page == 2k */
546 target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
547 target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
548 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
549 swap2 = (swap1 << 8) | (swap2 & 0xFF);
550 target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
551 target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
552
553 if (data)
554 target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
555 if (oob)
556 target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size, oob);
557
558 #ifdef _MX2_PRINT_STAT
559 if (data_size > 0) {
560 /* When Operation Status is read (when page is erased),
561 * this function is used but data_size is null.
562 */
563 LOG_INFO("%d bytes newly read", data_size);
564 }
565 #endif
566 return ERROR_OK;
567 }
568
569 static int initialize_nf_controller(struct nand_device *nand)
570 {
571 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
572 struct target *target = nand->target;
573 uint16_t work_mode;
574 uint16_t temp;
575 /*
576 * resets NAND flash controller in zero time ? I dont know.
577 */
578 target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN);
579 work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */
580 if (target->endianness == TARGET_BIG_ENDIAN) {
581 LOG_DEBUG("MX2_NF : work in Big Endian mode");
582 work_mode |= MX2_NF_BIT_BE_EN;
583 } else {
584 LOG_DEBUG("MX2_NF : work in Little Endian mode");
585 }
586 if (mx2_nf_info->flags.hw_ecc_enabled) {
587 LOG_DEBUG("MX2_NF : work with ECC mode");
588 work_mode |= MX2_NF_BIT_ECC_EN;
589 } else {
590 LOG_DEBUG("MX2_NF : work without ECC mode");
591 }
592 target_write_u16(target, MX2_NF_CFG1, work_mode);
593 /*
594 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
595 */
596 target_write_u16(target, MX2_NF_BUFCFG, 2);
597 target_read_u16(target, MX2_NF_FWP, &temp);
598 if ((temp & 0x0007) == 1) {
599 LOG_ERROR("NAND flash is tight-locked, reset needed");
600 return ERROR_FAIL;
601 }
602
603 /*
604 * unlock NAND flash for write
605 */
606 target_write_u16(target, MX2_NF_FWP, 4);
607 target_write_u16(target, MX2_NF_LOCKSTART, 0x0000);
608 target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF);
609 /*
610 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
611 */
612 target_write_u16(target, MX2_NF_BUFADDR, 0x0000);
613 /*
614 * address of SRAM buffer
615 */
616 in_sram_address = MX2_NF_MAIN_BUFFER0;
617 sign_of_sequental_byte_read = 0;
618 return ERROR_OK;
619 }
620
621 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
622 {
623 static uint8_t even_byte = 0;
624 uint16_t temp;
625 /*
626 * host-big_endian ??
627 */
628 if (sign_of_sequental_byte_read == 0)
629 even_byte = 0;
630
631 if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
632 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
633 *value = 0;
634 sign_of_sequental_byte_read = 0;
635 even_byte = 0;
636 return ERROR_NAND_OPERATION_FAILED;
637 } else {
638 target_read_u16(target, in_sram_address, &temp);
639 if (even_byte) {
640 *value = temp >> 8;
641 even_byte = 0;
642 in_sram_address += 2;
643 } else {
644 *value = temp & 0xff;
645 even_byte = 1;
646 }
647 }
648 sign_of_sequental_byte_read = 1;
649 return ERROR_OK;
650 }
651
652 static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value)
653 {
654 if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
655 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
656 *value = 0;
657 return ERROR_NAND_OPERATION_FAILED;
658 } else {
659 target_read_u16(target, in_sram_address, value);
660 in_sram_address += 2;
661 }
662 return ERROR_OK;
663 }
664
665 static int poll_for_complete_op(struct target *target, const char *text)
666 {
667 uint16_t poll_complete_status;
668 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
669 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
670 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
671 break;
672
673 usleep(10);
674 }
675 if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) {
676 LOG_ERROR("%s sending timeout", text);
677 return ERROR_NAND_OPERATION_FAILED;
678 }
679 return ERROR_OK;
680 }
681
682 static int validate_target_state(struct nand_device *nand)
683 {
684 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
685 struct target *target = nand->target;
686
687 if (target->state != TARGET_HALTED) {
688 LOG_ERROR(target_not_halted_err_msg);
689 return ERROR_NAND_OPERATION_FAILED;
690 }
691
692 if (mx2_nf_info->flags.target_little_endian !=
693 (target->endianness == TARGET_LITTLE_ENDIAN)) {
694 /*
695 * endianness changed after NAND controller probed
696 */
697 return ERROR_NAND_OPERATION_FAILED;
698 }
699 return ERROR_OK;
700 }
701
702 static int do_data_output(struct nand_device *nand)
703 {
704 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
705 struct target *target = nand->target;
706 int poll_result;
707 uint16_t ecc_status;
708 switch (mx2_nf_info->fin) {
709 case MX2_NF_FIN_DATAOUT:
710 /*
711 * start data output operation (set MX2_NF_BIT_OP_DONE==0)
712 */
713 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype));
714 poll_result = poll_for_complete_op(target, "data output");
715 if (poll_result != ERROR_OK)
716 return poll_result;
717
718 mx2_nf_info->fin = MX2_NF_FIN_NONE;
719 /*
720 * ECC stuff
721 */
722 if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) {
723 target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status);
724 switch (ecc_status & 0x000c) {
725 case 1 << 2:
726 LOG_INFO("main area readed with 1 (correctable) error");
727 break;
728 case 2 << 2:
729 LOG_INFO("main area readed with more than 1 (incorrectable) error");
730 return ERROR_NAND_OPERATION_FAILED;
731 break;
732 }
733 switch (ecc_status & 0x0003) {
734 case 1:
735 LOG_INFO("spare area readed with 1 (correctable) error");
736 break;
737 case 2:
738 LOG_INFO("main area readed with more than 1 (incorrectable) error");
739 return ERROR_NAND_OPERATION_FAILED;
740 break;
741 }
742 }
743 break;
744 case MX2_NF_FIN_NONE:
745 break;
746 }
747 return ERROR_OK;
748 }
749
750 struct nand_flash_controller imx27_nand_flash_controller = {
751 .name = "imx27",
752 .nand_device_command = &imx27_nand_device_command,
753 .init = &imx27_init,
754 .reset = &imx27_reset,
755 .command = &imx27_command,
756 .address = &imx27_address,
757 .write_data = &imx27_write_data,
758 .read_data = &imx27_read_data,
759 .write_page = &imx27_write_page,
760 .read_page = &imx27_read_page,
761 .nand_ready = &imx27_nand_ready,
762 };
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