tcl/memory.tcl

   1 # MEMORY
   2 #
   3 # All Memory regions have two components.
   4 #    (1) A count of regions, in the form N_NAME
   5 #    (2) An array within info about each region.
   6 #
   7 # The ARRAY
   8 #
   9 #       <NAME>(  RegionNumber ,  ATTRIBUTE )
  10 #
  11 # Where <NAME> is one of:
  12 #
  13 #     N_FLASH  & FLASH   (internal memory)
  14 #     N_RAM    & RAM     (internal memory)
  15 #     N_MMREGS & MMREGS  (for memory mapped registers)
  16 #     N_XMEM   & XMEM    (off chip memory, ie: flash on cs0, sdram on cs2)
  17 # or  N_UNKNOWN & UNKNOWN for things that do not exist.
  18 #
  19 # We have 1 unknown region.
  20 set N_UNKNOWN 1
  21 # All MEMORY regions must have these attributes
  22 #     CS          - chip select (if internal, use -1)
  23 set UNKNOWN(0,CHIPSELECT) -1
  24 #     BASE        - base address in memory
  25 set UNKNOWN(0,BASE)       0
  26 #     LEN         - length in bytes
  27 set UNKNOWN(0,LEN)        $CPU_MAX_ADDRESS
  28 #     HUMAN       - human name of the region
  29 set UNKNOWN(0,HUMAN) "unknown"
  30 #     TYPE        - one of:
  31 #                       flash, ram, mmr, unknown
  32 #                    For harvard arch:
  33 #                       iflash, dflash, iram, dram
  34 set UNKNOWN(0,TYPE)       "unknown"
  35 #     RWX         - access ablity
  36 #                       unix style chmod bits
  37 #                           0 - no access
  38 #                           1 - execute
  39 #                           2 - write
  40 #                           4 - read
  41 #                       hence: 7 - readwrite execute
  42 set RWX_NO_ACCESS     0
  43 set RWX_X_ONLY        $BIT0
  44 set RWX_W_ONLY        $BIT1
  45 set RWX_R_ONLY        $BIT2
  46 set RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
  47 set RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
  48 set RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
  49 set UNKNOWN(0,RWX)     $RWX_NO_ACCESS
  50
  51 #     WIDTH       - access width
  52 #                      8,16,32 [0 means ANY]
  53 set ACCESS_WIDTH_NONE 0
  54 set ACCESS_WIDTH_8    $BIT0
  55 set ACCESS_WIDTH_16   $BIT1
  56 set ACCESS_WIDTH_32   $BIT2
  57 set ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
  58 set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
  59
  60 proc iswithin { ADDRESS BASE LEN } {
  61     return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
  62 }
  63
  64 proc address_info { ADDRESS } {
  65
  66     foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
  67         if { info exists $WHERE } {
  68             set lmt [set N_[set WHERE]]
  69             for { set region 0 } { $region < $lmt } { incr region } {
  70                 if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
  71                     return  "$WHERE $region";
  72                 }
  73             }
  74         }
  75     }
  76
  77     # Return the 'unknown'
  78     return "UNKNOWN 0"
  79 }
  80
  81 proc memread32 {ADDR} {
  82     set foo(0) 0
  83     if ![ catch { mem2array foo 32 $ADDR 1  } msg ] {
  84         return $foo(0)
  85     } else {
  86         error "memread32: $msg"
  87     }
  88 }
  89
  90 proc memread16 {ADDR} {
  91     set foo(0) 0
  92     if ![ catch { mem2array foo 16 $ADDR 1  } msg ] {
  93         return $foo(0)
  94     } else {
  95         error "memread16: $msg"
  96     }
  97 }
  98
  99 proc memread8 {ADDR} {
 100     set foo(0) 0
 101     if ![ catch { mem2array foo 8 $ADDR 1  } msg ] {
 102         return $foo(0)
 103     } else {
 104         error "memread8: $msg"
 105     }
 106 }
 107
 108 proc memwrite32 {ADDR DATA} {
 109     set foo(0) $DATA
 110     if ![ catch { array2mem foo 32 $ADDR 1  } msg ] {
 111         return $foo(0)
 112     } else {
 113         error "memwrite32: $msg"
 114     }
 115 }
 116
 117 proc memwrite16 {ADDR DATA} {
 118     set foo(0) $DATA
 119     if ![ catch { array2mem foo 16 $ADDR 1  } msg ] {
 120         return $foo(0)
 121     } else {
 122         error "memwrite16: $msg"
 123     }
 124 }
 125
 126 proc memwrite8 {ADDR DATA} {
 127     set foo(0) $DATA
 128     if ![ catch { array2mem foo 8 $ADDR 1  } msg ] {
 129         return $foo(0)
 130     } else {
 131         error "memwrite8: $msg"
 132     }
 133 }
 134
 135 proc memread32_phys {ADDR} {
 136     set foo(0) 0
 137     if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
 138         return $foo(0)
 139     } else {
 140         error "memread32: $msg"
 141     }
 142 }
 143
 144 proc memread16_phys {ADDR} {
 145     set foo(0) 0
 146     if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
 147         return $foo(0)
 148     } else {
 149         error "memread16: $msg"
 150     }
 151 }
 152
 153 proc memread8_phys {ADDR} {
 154     set foo(0) 0
 155     if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
 156         return $foo(0)
 157     } else {
 158         error "memread8: $msg"
 159     }
 160 }
 161
 162 proc memwrite32_phys {ADDR DATA} {
 163     set foo(0) $DATA
 164     if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
 165         return $foo(0)
 166     } else {
 167         error "memwrite32: $msg"
 168     }
 169 }
 170
 171 proc memwrite16_phys {ADDR DATA} {
 172     set foo(0) $DATA
 173     if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
 174         return $foo(0)
 175     } else {
 176         error "memwrite16: $msg"
 177     }
 178 }
 179
 180 proc memwrite8_phys {ADDR DATA} {
 181     set foo(0) $DATA
 182     if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
 183         return $foo(0)
 184     } else {
 185         error "memwrite8: $msg"
 186     }
 187 }