1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ****************************************************************************/
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
58 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
76 /* at91sam3sd series (has always two flash banks) */
77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
81 /* at91sam3n series (has always one flash bank) */
82 #define FLASH_BANK_BASE_N 0x00400000
84 /* at91sam3a/x series has two flash banks*/
85 #define FLASH_BANK0_BASE_AX 0x00080000
86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
87 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
88 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
90 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
91 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
92 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
93 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
94 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
95 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
99 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
100 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
101 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
102 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
103 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
104 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
105 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
106 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
107 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
109 #define offset_EFC_FMR 0
110 #define offset_EFC_FCR 4
111 #define offset_EFC_FSR 8
112 #define offset_EFC_FRR 12
114 extern struct flash_driver at91sam3_flash
;
116 static float _tomhz(uint32_t freq_hz
)
120 f
= ((float)(freq_hz
)) / 1000000.0;
124 /* How the chip is configured. */
126 uint32_t unique_id
[4];
130 uint32_t mainosc_freq
;
140 #define SAM3_CHIPID_CIDR (0x400E0740)
141 uint32_t CHIPID_CIDR
;
142 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_CIDR2
;
144 #define SAM3_CHIPID_EXID (0x400E0744)
145 uint32_t CHIPID_EXID
;
146 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
147 uint32_t CHIPID_EXID2
;
150 #define SAM3_PMC_BASE (0x400E0400)
151 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
153 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
155 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
157 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
159 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
161 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
163 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
165 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
167 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
169 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
171 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
173 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
175 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
177 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
182 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
183 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
184 * the flash wait state (FWS) should be set to 6. It seems like that the
185 * cause of the problem is not the flash itself, but the flash write
186 * buffer. Ie the wait states have to be set before writing into the
188 * Tested and confirmed with SAM3N and SAM3U
191 struct sam3_bank_private
{
193 /* DANGER: THERE ARE DRAGONS HERE.. */
194 /* NOTE: If you add more 'ghost' pointers */
195 /* be aware that you must *manually* update */
196 /* these pointers in the function sam3_GetDetails() */
197 /* See the comment "Here there be dragons" */
199 /* so we can find the chip we belong to */
200 struct sam3_chip
*pChip
;
201 /* so we can find the original bank pointer */
202 struct flash_bank
*pBank
;
203 unsigned bank_number
;
204 uint32_t controller_address
;
205 uint32_t base_address
;
206 uint32_t flash_wait_states
;
210 unsigned sector_size
;
214 struct sam3_chip_details
{
215 /* THERE ARE DRAGONS HERE.. */
216 /* note: If you add pointers here */
217 /* be careful about them as they */
218 /* may need to be updated inside */
219 /* the function: "sam3_GetDetails() */
220 /* which copy/overwrites the */
221 /* 'runtime' copy of this structure */
222 uint32_t chipid_cidr
;
226 #define SAM3_N_NVM_BITS 3
227 unsigned gpnvm
[SAM3_N_NVM_BITS
];
228 unsigned total_flash_size
;
229 unsigned total_sram_size
;
231 #define SAM3_MAX_FLASH_BANKS 2
232 /* these are "initialized" from the global const data */
233 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
237 struct sam3_chip
*next
;
240 /* this is "initialized" from the global const structure */
241 struct sam3_chip_details details
;
242 struct target
*target
;
247 struct sam3_reg_list
{
248 uint32_t address
; size_t struct_offset
; const char *name
;
249 void (*explain_func
)(struct sam3_chip
*pInfo
);
252 static struct sam3_chip
*all_sam3_chips
;
254 static struct sam3_chip
*get_current_sam3(struct command_context
*cmd_ctx
)
257 static struct sam3_chip
*p
;
259 t
= get_current_target(cmd_ctx
);
261 command_print(cmd_ctx
, "No current target?");
267 /* this should not happen */
268 /* the command is not registered until the chip is created? */
269 command_print(cmd_ctx
, "No SAM3 chips exist?");
278 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
282 /* these are used to *initialize* the "pChip->details" structure. */
283 static const struct sam3_chip_details all_sam3_details
[] = {
284 /* Start at91sam3u* series */
286 .chipid_cidr
= 0x28100960,
287 .name
= "at91sam3u4e",
288 .total_flash_size
= 256 * 1024,
289 .total_sram_size
= 52 * 1024,
293 /* System boots at address 0x0 */
294 /* gpnvm[1] = selects boot code */
295 /* if gpnvm[1] == 0 */
296 /* boot is via "SAMBA" (rom) */
298 /* boot is via FLASH */
299 /* Selection is via gpnvm[2] */
302 /* NOTE: banks 0 & 1 switch places */
303 /* if gpnvm[2] == 0 */
304 /* Bank0 is the boot rom */
306 /* Bank1 is the boot rom */
315 .base_address
= FLASH_BANK0_BASE_U
,
316 .controller_address
= 0x400e0800,
317 .flash_wait_states
= 6, /* workaround silicon bug */
319 .size_bytes
= 128 * 1024,
331 .base_address
= FLASH_BANK1_BASE_U
,
332 .controller_address
= 0x400e0a00,
333 .flash_wait_states
= 6, /* workaround silicon bug */
335 .size_bytes
= 128 * 1024,
344 .chipid_cidr
= 0x281a0760,
345 .name
= "at91sam3u2e",
346 .total_flash_size
= 128 * 1024,
347 .total_sram_size
= 36 * 1024,
351 /* System boots at address 0x0 */
352 /* gpnvm[1] = selects boot code */
353 /* if gpnvm[1] == 0 */
354 /* boot is via "SAMBA" (rom) */
356 /* boot is via FLASH */
357 /* Selection is via gpnvm[2] */
366 .base_address
= FLASH_BANK0_BASE_U
,
367 .controller_address
= 0x400e0800,
368 .flash_wait_states
= 6, /* workaround silicon bug */
370 .size_bytes
= 128 * 1024,
384 .chipid_cidr
= 0x28190560,
385 .name
= "at91sam3u1e",
386 .total_flash_size
= 64 * 1024,
387 .total_sram_size
= 20 * 1024,
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
408 .base_address
= FLASH_BANK0_BASE_U
,
409 .controller_address
= 0x400e0800,
410 .flash_wait_states
= 6, /* workaround silicon bug */
412 .size_bytes
= 64 * 1024,
428 .chipid_cidr
= 0x28000960,
429 .name
= "at91sam3u4c",
430 .total_flash_size
= 256 * 1024,
431 .total_sram_size
= 52 * 1024,
435 /* System boots at address 0x0 */
436 /* gpnvm[1] = selects boot code */
437 /* if gpnvm[1] == 0 */
438 /* boot is via "SAMBA" (rom) */
440 /* boot is via FLASH */
441 /* Selection is via gpnvm[2] */
444 /* NOTE: banks 0 & 1 switch places */
445 /* if gpnvm[2] == 0 */
446 /* Bank0 is the boot rom */
448 /* Bank1 is the boot rom */
457 .base_address
= FLASH_BANK0_BASE_U
,
458 .controller_address
= 0x400e0800,
459 .flash_wait_states
= 6, /* workaround silicon bug */
461 .size_bytes
= 128 * 1024,
472 .base_address
= FLASH_BANK1_BASE_U
,
473 .controller_address
= 0x400e0a00,
474 .flash_wait_states
= 6, /* workaround silicon bug */
476 .size_bytes
= 128 * 1024,
485 .chipid_cidr
= 0x280a0760,
486 .name
= "at91sam3u2c",
487 .total_flash_size
= 128 * 1024,
488 .total_sram_size
= 36 * 1024,
492 /* System boots at address 0x0 */
493 /* gpnvm[1] = selects boot code */
494 /* if gpnvm[1] == 0 */
495 /* boot is via "SAMBA" (rom) */
497 /* boot is via FLASH */
498 /* Selection is via gpnvm[2] */
507 .base_address
= FLASH_BANK0_BASE_U
,
508 .controller_address
= 0x400e0800,
509 .flash_wait_states
= 6, /* workaround silicon bug */
511 .size_bytes
= 128 * 1024,
525 .chipid_cidr
= 0x28090560,
526 .name
= "at91sam3u1c",
527 .total_flash_size
= 64 * 1024,
528 .total_sram_size
= 20 * 1024,
532 /* System boots at address 0x0 */
533 /* gpnvm[1] = selects boot code */
534 /* if gpnvm[1] == 0 */
535 /* boot is via "SAMBA" (rom) */
537 /* boot is via FLASH */
538 /* Selection is via gpnvm[2] */
549 .base_address
= FLASH_BANK0_BASE_U
,
550 .controller_address
= 0x400e0800,
551 .flash_wait_states
= 6, /* workaround silicon bug */
553 .size_bytes
= 64 * 1024,
568 /* Start at91sam3s* series */
570 /* Note: The preliminary at91sam3s datasheet says on page 302 */
571 /* that the flash controller is at address 0x400E0800. */
572 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
574 .chipid_cidr
= 0x28A00960,
575 .name
= "at91sam3s4c",
576 .total_flash_size
= 256 * 1024,
577 .total_sram_size
= 48 * 1024,
587 .base_address
= FLASH_BANK_BASE_S
,
588 .controller_address
= 0x400e0a00,
589 .flash_wait_states
= 6, /* workaround silicon bug */
591 .size_bytes
= 256 * 1024,
593 .sector_size
= 16384,
607 .chipid_cidr
= 0x28900960,
608 .name
= "at91sam3s4b",
609 .total_flash_size
= 256 * 1024,
610 .total_sram_size
= 48 * 1024,
620 .base_address
= FLASH_BANK_BASE_S
,
621 .controller_address
= 0x400e0a00,
622 .flash_wait_states
= 6, /* workaround silicon bug */
624 .size_bytes
= 256 * 1024,
626 .sector_size
= 16384,
639 .chipid_cidr
= 0x28800960,
640 .name
= "at91sam3s4a",
641 .total_flash_size
= 256 * 1024,
642 .total_sram_size
= 48 * 1024,
652 .base_address
= FLASH_BANK_BASE_S
,
653 .controller_address
= 0x400e0a00,
654 .flash_wait_states
= 6, /* workaround silicon bug */
656 .size_bytes
= 256 * 1024,
658 .sector_size
= 16384,
671 .chipid_cidr
= 0x28AA0760,
672 .name
= "at91sam3s2c",
673 .total_flash_size
= 128 * 1024,
674 .total_sram_size
= 32 * 1024,
684 .base_address
= FLASH_BANK_BASE_S
,
685 .controller_address
= 0x400e0a00,
686 .flash_wait_states
= 6, /* workaround silicon bug */
688 .size_bytes
= 128 * 1024,
690 .sector_size
= 16384,
703 .chipid_cidr
= 0x289A0760,
704 .name
= "at91sam3s2b",
705 .total_flash_size
= 128 * 1024,
706 .total_sram_size
= 32 * 1024,
716 .base_address
= FLASH_BANK_BASE_S
,
717 .controller_address
= 0x400e0a00,
718 .flash_wait_states
= 6, /* workaround silicon bug */
720 .size_bytes
= 128 * 1024,
722 .sector_size
= 16384,
735 .chipid_cidr
= 0x298B0A60,
736 .name
= "at91sam3sd8a",
737 .total_flash_size
= 512 * 1024,
738 .total_sram_size
= 64 * 1024,
748 .base_address
= FLASH_BANK0_BASE_SD
,
749 .controller_address
= 0x400e0a00,
750 .flash_wait_states
= 6, /* workaround silicon bug */
752 .size_bytes
= 256 * 1024,
754 .sector_size
= 32768,
763 .base_address
= FLASH_BANK1_BASE_512K_SD
,
764 .controller_address
= 0x400e0a00,
765 .flash_wait_states
= 6, /* workaround silicon bug */
767 .size_bytes
= 256 * 1024,
769 .sector_size
= 32768,
775 .chipid_cidr
= 0x299B0A60,
776 .name
= "at91sam3sd8b",
777 .total_flash_size
= 512 * 1024,
778 .total_sram_size
= 64 * 1024,
788 .base_address
= FLASH_BANK0_BASE_SD
,
789 .controller_address
= 0x400e0a00,
790 .flash_wait_states
= 6, /* workaround silicon bug */
792 .size_bytes
= 256 * 1024,
794 .sector_size
= 32768,
803 .base_address
= FLASH_BANK1_BASE_512K_SD
,
804 .controller_address
= 0x400e0a00,
805 .flash_wait_states
= 6, /* workaround silicon bug */
807 .size_bytes
= 256 * 1024,
809 .sector_size
= 32768,
815 .chipid_cidr
= 0x29ab0a60,
816 .name
= "at91sam3sd8c",
817 .total_flash_size
= 512 * 1024,
818 .total_sram_size
= 64 * 1024,
828 .base_address
= FLASH_BANK0_BASE_SD
,
829 .controller_address
= 0x400e0a00,
830 .flash_wait_states
= 6, /* workaround silicon bug */
832 .size_bytes
= 256 * 1024,
834 .sector_size
= 32768,
843 .base_address
= FLASH_BANK1_BASE_512K_SD
,
844 .controller_address
= 0x400e0a00,
845 .flash_wait_states
= 6, /* workaround silicon bug */
847 .size_bytes
= 256 * 1024,
849 .sector_size
= 32768,
855 .chipid_cidr
= 0x288A0760,
856 .name
= "at91sam3s2a",
857 .total_flash_size
= 128 * 1024,
858 .total_sram_size
= 32 * 1024,
868 .base_address
= FLASH_BANK_BASE_S
,
869 .controller_address
= 0x400e0a00,
870 .flash_wait_states
= 6, /* workaround silicon bug */
872 .size_bytes
= 128 * 1024,
874 .sector_size
= 16384,
887 .chipid_cidr
= 0x28A90560,
888 .name
= "at91sam3s1c",
889 .total_flash_size
= 64 * 1024,
890 .total_sram_size
= 16 * 1024,
900 .base_address
= FLASH_BANK_BASE_S
,
901 .controller_address
= 0x400e0a00,
902 .flash_wait_states
= 6, /* workaround silicon bug */
904 .size_bytes
= 64 * 1024,
906 .sector_size
= 16384,
919 .chipid_cidr
= 0x28990560,
920 .name
= "at91sam3s1b",
921 .total_flash_size
= 64 * 1024,
922 .total_sram_size
= 16 * 1024,
932 .base_address
= FLASH_BANK_BASE_S
,
933 .controller_address
= 0x400e0a00,
934 .flash_wait_states
= 6, /* workaround silicon bug */
936 .size_bytes
= 64 * 1024,
938 .sector_size
= 16384,
951 .chipid_cidr
= 0x28890560,
952 .name
= "at91sam3s1a",
953 .total_flash_size
= 64 * 1024,
954 .total_sram_size
= 16 * 1024,
964 .base_address
= FLASH_BANK_BASE_S
,
965 .controller_address
= 0x400e0a00,
966 .flash_wait_states
= 6, /* workaround silicon bug */
968 .size_bytes
= 64 * 1024,
970 .sector_size
= 16384,
983 .chipid_cidr
= 0x288B0A60,
984 .name
= "at91sam3s8a",
985 .total_flash_size
= 256 * 2048,
986 .total_sram_size
= 64 * 1024,
996 .base_address
= FLASH_BANK_BASE_S
,
997 .controller_address
= 0x400e0a00,
998 .flash_wait_states
= 6, /* workaround silicon bug */
1000 .size_bytes
= 256 * 2048,
1002 .sector_size
= 32768,
1015 .chipid_cidr
= 0x289B0A60,
1016 .name
= "at91sam3s8b",
1017 .total_flash_size
= 256 * 2048,
1018 .total_sram_size
= 64 * 1024,
1028 .base_address
= FLASH_BANK_BASE_S
,
1029 .controller_address
= 0x400e0a00,
1030 .flash_wait_states
= 6, /* workaround silicon bug */
1032 .size_bytes
= 256 * 2048,
1034 .sector_size
= 32768,
1047 .chipid_cidr
= 0x28AB0A60,
1048 .name
= "at91sam3s8c",
1049 .total_flash_size
= 256 * 2048,
1050 .total_sram_size
= 64 * 1024,
1060 .base_address
= FLASH_BANK_BASE_S
,
1061 .controller_address
= 0x400e0a00,
1062 .flash_wait_states
= 6, /* workaround silicon bug */
1064 .size_bytes
= 256 * 2048,
1066 .sector_size
= 32768,
1079 /* Start at91sam3n* series */
1081 .chipid_cidr
= 0x29540960,
1082 .name
= "at91sam3n4c",
1083 .total_flash_size
= 256 * 1024,
1084 .total_sram_size
= 24 * 1024,
1088 /* System boots at address 0x0 */
1089 /* gpnvm[1] = selects boot code */
1090 /* if gpnvm[1] == 0 */
1091 /* boot is via "SAMBA" (rom) */
1093 /* boot is via FLASH */
1094 /* Selection is via gpnvm[2] */
1097 /* NOTE: banks 0 & 1 switch places */
1098 /* if gpnvm[2] == 0 */
1099 /* Bank0 is the boot rom */
1101 /* Bank1 is the boot rom */
1110 .base_address
= FLASH_BANK_BASE_N
,
1111 .controller_address
= 0x400e0A00,
1112 .flash_wait_states
= 6, /* workaround silicon bug */
1114 .size_bytes
= 256 * 1024,
1116 .sector_size
= 16384,
1130 .chipid_cidr
= 0x29440960,
1131 .name
= "at91sam3n4b",
1132 .total_flash_size
= 256 * 1024,
1133 .total_sram_size
= 24 * 1024,
1137 /* System boots at address 0x0 */
1138 /* gpnvm[1] = selects boot code */
1139 /* if gpnvm[1] == 0 */
1140 /* boot is via "SAMBA" (rom) */
1142 /* boot is via FLASH */
1143 /* Selection is via gpnvm[2] */
1146 /* NOTE: banks 0 & 1 switch places */
1147 /* if gpnvm[2] == 0 */
1148 /* Bank0 is the boot rom */
1150 /* Bank1 is the boot rom */
1159 .base_address
= FLASH_BANK_BASE_N
,
1160 .controller_address
= 0x400e0A00,
1161 .flash_wait_states
= 6, /* workaround silicon bug */
1163 .size_bytes
= 256 * 1024,
1165 .sector_size
= 16384,
1179 .chipid_cidr
= 0x29340960,
1180 .name
= "at91sam3n4a",
1181 .total_flash_size
= 256 * 1024,
1182 .total_sram_size
= 24 * 1024,
1186 /* System boots at address 0x0 */
1187 /* gpnvm[1] = selects boot code */
1188 /* if gpnvm[1] == 0 */
1189 /* boot is via "SAMBA" (rom) */
1191 /* boot is via FLASH */
1192 /* Selection is via gpnvm[2] */
1195 /* NOTE: banks 0 & 1 switch places */
1196 /* if gpnvm[2] == 0 */
1197 /* Bank0 is the boot rom */
1199 /* Bank1 is the boot rom */
1208 .base_address
= FLASH_BANK_BASE_N
,
1209 .controller_address
= 0x400e0A00,
1210 .flash_wait_states
= 6, /* workaround silicon bug */
1212 .size_bytes
= 256 * 1024,
1214 .sector_size
= 16384,
1228 .chipid_cidr
= 0x29590760,
1229 .name
= "at91sam3n2c",
1230 .total_flash_size
= 128 * 1024,
1231 .total_sram_size
= 16 * 1024,
1235 /* System boots at address 0x0 */
1236 /* gpnvm[1] = selects boot code */
1237 /* if gpnvm[1] == 0 */
1238 /* boot is via "SAMBA" (rom) */
1240 /* boot is via FLASH */
1241 /* Selection is via gpnvm[2] */
1244 /* NOTE: banks 0 & 1 switch places */
1245 /* if gpnvm[2] == 0 */
1246 /* Bank0 is the boot rom */
1248 /* Bank1 is the boot rom */
1257 .base_address
= FLASH_BANK_BASE_N
,
1258 .controller_address
= 0x400e0A00,
1259 .flash_wait_states
= 6, /* workaround silicon bug */
1261 .size_bytes
= 128 * 1024,
1263 .sector_size
= 16384,
1277 .chipid_cidr
= 0x29490760,
1278 .name
= "at91sam3n2b",
1279 .total_flash_size
= 128 * 1024,
1280 .total_sram_size
= 16 * 1024,
1284 /* System boots at address 0x0 */
1285 /* gpnvm[1] = selects boot code */
1286 /* if gpnvm[1] == 0 */
1287 /* boot is via "SAMBA" (rom) */
1289 /* boot is via FLASH */
1290 /* Selection is via gpnvm[2] */
1293 /* NOTE: banks 0 & 1 switch places */
1294 /* if gpnvm[2] == 0 */
1295 /* Bank0 is the boot rom */
1297 /* Bank1 is the boot rom */
1306 .base_address
= FLASH_BANK_BASE_N
,
1307 .controller_address
= 0x400e0A00,
1308 .flash_wait_states
= 6, /* workaround silicon bug */
1310 .size_bytes
= 128 * 1024,
1312 .sector_size
= 16384,
1326 .chipid_cidr
= 0x29390760,
1327 .name
= "at91sam3n2a",
1328 .total_flash_size
= 128 * 1024,
1329 .total_sram_size
= 16 * 1024,
1333 /* System boots at address 0x0 */
1334 /* gpnvm[1] = selects boot code */
1335 /* if gpnvm[1] == 0 */
1336 /* boot is via "SAMBA" (rom) */
1338 /* boot is via FLASH */
1339 /* Selection is via gpnvm[2] */
1342 /* NOTE: banks 0 & 1 switch places */
1343 /* if gpnvm[2] == 0 */
1344 /* Bank0 is the boot rom */
1346 /* Bank1 is the boot rom */
1355 .base_address
= FLASH_BANK_BASE_N
,
1356 .controller_address
= 0x400e0A00,
1357 .flash_wait_states
= 6, /* workaround silicon bug */
1359 .size_bytes
= 128 * 1024,
1361 .sector_size
= 16384,
1375 .chipid_cidr
= 0x29580560,
1376 .name
= "at91sam3n1c",
1377 .total_flash_size
= 64 * 1024,
1378 .total_sram_size
= 8 * 1024,
1382 /* System boots at address 0x0 */
1383 /* gpnvm[1] = selects boot code */
1384 /* if gpnvm[1] == 0 */
1385 /* boot is via "SAMBA" (rom) */
1387 /* boot is via FLASH */
1388 /* Selection is via gpnvm[2] */
1391 /* NOTE: banks 0 & 1 switch places */
1392 /* if gpnvm[2] == 0 */
1393 /* Bank0 is the boot rom */
1395 /* Bank1 is the boot rom */
1404 .base_address
= FLASH_BANK_BASE_N
,
1405 .controller_address
= 0x400e0A00,
1406 .flash_wait_states
= 6, /* workaround silicon bug */
1408 .size_bytes
= 64 * 1024,
1410 .sector_size
= 16384,
1424 .chipid_cidr
= 0x29480560,
1425 .name
= "at91sam3n1b",
1426 .total_flash_size
= 64 * 1024,
1427 .total_sram_size
= 8 * 1024,
1431 /* System boots at address 0x0 */
1432 /* gpnvm[1] = selects boot code */
1433 /* if gpnvm[1] == 0 */
1434 /* boot is via "SAMBA" (rom) */
1436 /* boot is via FLASH */
1437 /* Selection is via gpnvm[2] */
1440 /* NOTE: banks 0 & 1 switch places */
1441 /* if gpnvm[2] == 0 */
1442 /* Bank0 is the boot rom */
1444 /* Bank1 is the boot rom */
1453 .base_address
= FLASH_BANK_BASE_N
,
1454 .controller_address
= 0x400e0A00,
1455 .flash_wait_states
= 6, /* workaround silicon bug */
1457 .size_bytes
= 64 * 1024,
1459 .sector_size
= 16384,
1473 .chipid_cidr
= 0x29380560,
1474 .name
= "at91sam3n1a",
1475 .total_flash_size
= 64 * 1024,
1476 .total_sram_size
= 8 * 1024,
1480 /* System boots at address 0x0 */
1481 /* gpnvm[1] = selects boot code */
1482 /* if gpnvm[1] == 0 */
1483 /* boot is via "SAMBA" (rom) */
1485 /* boot is via FLASH */
1486 /* Selection is via gpnvm[2] */
1489 /* NOTE: banks 0 & 1 switch places */
1490 /* if gpnvm[2] == 0 */
1491 /* Bank0 is the boot rom */
1493 /* Bank1 is the boot rom */
1502 .base_address
= FLASH_BANK_BASE_N
,
1503 .controller_address
= 0x400e0A00,
1504 .flash_wait_states
= 6, /* workaround silicon bug */
1506 .size_bytes
= 64 * 1024,
1508 .sector_size
= 16384,
1521 /* Start at91sam3a series*/
1522 /* System boots at address 0x0 */
1523 /* gpnvm[1] = selects boot code */
1524 /* if gpnvm[1] == 0 */
1525 /* boot is via "SAMBA" (rom) */
1527 /* boot is via FLASH */
1528 /* Selection is via gpnvm[2] */
1531 /* NOTE: banks 0 & 1 switch places */
1532 /* if gpnvm[2] == 0 */
1533 /* Bank0 is the boot rom */
1535 /* Bank1 is the boot rom */
1539 .chipid_cidr
= 0x283E0A60,
1540 .name
= "at91sam3a8c",
1541 .total_flash_size
= 512 * 1024,
1542 .total_sram_size
= 96 * 1024,
1552 .base_address
= FLASH_BANK0_BASE_AX
,
1553 .controller_address
= 0x400e0a00,
1554 .flash_wait_states
= 6, /* workaround silicon bug */
1556 .size_bytes
= 256 * 1024,
1558 .sector_size
= 16384,
1567 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1568 .controller_address
= 0x400e0c00,
1569 .flash_wait_states
= 6, /* workaround silicon bug */
1571 .size_bytes
= 256 * 1024,
1573 .sector_size
= 16384,
1580 .chipid_cidr
= 0x283B0960,
1581 .name
= "at91sam3a4c",
1582 .total_flash_size
= 256 * 1024,
1583 .total_sram_size
= 64 * 1024,
1593 .base_address
= FLASH_BANK0_BASE_AX
,
1594 .controller_address
= 0x400e0a00,
1595 .flash_wait_states
= 6, /* workaround silicon bug */
1597 .size_bytes
= 128 * 1024,
1599 .sector_size
= 16384,
1608 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1609 .controller_address
= 0x400e0c00,
1610 .flash_wait_states
= 6, /* workaround silicon bug */
1612 .size_bytes
= 128 * 1024,
1614 .sector_size
= 16384,
1621 /* Start at91sam3x* series */
1622 /* System boots at address 0x0 */
1623 /* gpnvm[1] = selects boot code */
1624 /* if gpnvm[1] == 0 */
1625 /* boot is via "SAMBA" (rom) */
1627 /* boot is via FLASH */
1628 /* Selection is via gpnvm[2] */
1631 /* NOTE: banks 0 & 1 switch places */
1632 /* if gpnvm[2] == 0 */
1633 /* Bank0 is the boot rom */
1635 /* Bank1 is the boot rom */
1637 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1639 .chipid_cidr
= 0x286E0A20,
1640 .name
= "at91sam3x8h - ES",
1641 .total_flash_size
= 512 * 1024,
1642 .total_sram_size
= 96 * 1024,
1652 .base_address
= FLASH_BANK0_BASE_AX
,
1653 .controller_address
= 0x400e0a00,
1654 .flash_wait_states
= 6, /* workaround silicon bug */
1656 .size_bytes
= 256 * 1024,
1658 .sector_size
= 16384,
1667 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1668 .controller_address
= 0x400e0c00,
1669 .flash_wait_states
= 6, /* workaround silicon bug */
1671 .size_bytes
= 256 * 1024,
1673 .sector_size
= 16384,
1679 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1681 .chipid_cidr
= 0x286E0A60,
1682 .name
= "at91sam3x8h",
1683 .total_flash_size
= 512 * 1024,
1684 .total_sram_size
= 96 * 1024,
1694 .base_address
= FLASH_BANK0_BASE_AX
,
1695 .controller_address
= 0x400e0a00,
1696 .flash_wait_states
= 6, /* workaround silicon bug */
1698 .size_bytes
= 256 * 1024,
1700 .sector_size
= 16384,
1709 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1710 .controller_address
= 0x400e0c00,
1711 .flash_wait_states
= 6, /* workaround silicon bug */
1713 .size_bytes
= 256 * 1024,
1715 .sector_size
= 16384,
1722 .chipid_cidr
= 0x285E0A60,
1723 .name
= "at91sam3x8e",
1724 .total_flash_size
= 512 * 1024,
1725 .total_sram_size
= 96 * 1024,
1735 .base_address
= FLASH_BANK0_BASE_AX
,
1736 .controller_address
= 0x400e0a00,
1737 .flash_wait_states
= 6, /* workaround silicon bug */
1739 .size_bytes
= 256 * 1024,
1741 .sector_size
= 16384,
1750 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1751 .controller_address
= 0x400e0c00,
1752 .flash_wait_states
= 6, /* workaround silicon bug */
1754 .size_bytes
= 256 * 1024,
1756 .sector_size
= 16384,
1763 .chipid_cidr
= 0x284E0A60,
1764 .name
= "at91sam3x8c",
1765 .total_flash_size
= 512 * 1024,
1766 .total_sram_size
= 96 * 1024,
1776 .base_address
= FLASH_BANK0_BASE_AX
,
1777 .controller_address
= 0x400e0a00,
1778 .flash_wait_states
= 6, /* workaround silicon bug */
1780 .size_bytes
= 256 * 1024,
1782 .sector_size
= 16384,
1791 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1792 .controller_address
= 0x400e0c00,
1793 .flash_wait_states
= 6, /* workaround silicon bug */
1795 .size_bytes
= 256 * 1024,
1797 .sector_size
= 16384,
1804 .chipid_cidr
= 0x285B0960,
1805 .name
= "at91sam3x4e",
1806 .total_flash_size
= 256 * 1024,
1807 .total_sram_size
= 64 * 1024,
1817 .base_address
= FLASH_BANK0_BASE_AX
,
1818 .controller_address
= 0x400e0a00,
1819 .flash_wait_states
= 6, /* workaround silicon bug */
1821 .size_bytes
= 128 * 1024,
1823 .sector_size
= 16384,
1832 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1833 .controller_address
= 0x400e0c00,
1834 .flash_wait_states
= 6, /* workaround silicon bug */
1836 .size_bytes
= 128 * 1024,
1838 .sector_size
= 16384,
1845 .chipid_cidr
= 0x284B0960,
1846 .name
= "at91sam3x4c",
1847 .total_flash_size
= 256 * 1024,
1848 .total_sram_size
= 64 * 1024,
1858 .base_address
= FLASH_BANK0_BASE_AX
,
1859 .controller_address
= 0x400e0a00,
1860 .flash_wait_states
= 6, /* workaround silicon bug */
1862 .size_bytes
= 128 * 1024,
1864 .sector_size
= 16384,
1873 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1874 .controller_address
= 0x400e0c00,
1875 .flash_wait_states
= 6, /* workaround silicon bug */
1877 .size_bytes
= 128 * 1024,
1879 .sector_size
= 16384,
1893 /***********************************************************************
1894 **********************************************************************
1895 **********************************************************************
1896 **********************************************************************
1897 **********************************************************************
1898 **********************************************************************/
1899 /* *ATMEL* style code - from the SAM3 driver code */
1902 * Get the current status of the EEFC and
1903 * the value of some status bits (LOCKE, PROGE).
1904 * @param pPrivate - info about the bank
1905 * @param v - result goes here
1907 static int EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1910 r
= target_read_u32(pPrivate
->pChip
->target
,
1911 pPrivate
->controller_address
+ offset_EFC_FSR
,
1913 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1915 ((unsigned int)((*v
>> 2) & 1)),
1916 ((unsigned int)((*v
>> 1) & 1)),
1917 ((unsigned int)((*v
>> 0) & 1)));
1923 * Get the result of the last executed command.
1924 * @param pPrivate - info about the bank
1925 * @param v - result goes here
1927 static int EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1931 r
= target_read_u32(pPrivate
->pChip
->target
,
1932 pPrivate
->controller_address
+ offset_EFC_FRR
,
1936 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1940 static int EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
1941 unsigned command
, unsigned argument
)
1950 /* Check command & argument */
1953 case AT91C_EFC_FCMD_WP
:
1954 case AT91C_EFC_FCMD_WPL
:
1955 case AT91C_EFC_FCMD_EWP
:
1956 case AT91C_EFC_FCMD_EWPL
:
1957 /* case AT91C_EFC_FCMD_EPL: */
1958 /* case AT91C_EFC_FCMD_EPA: */
1959 case AT91C_EFC_FCMD_SLB
:
1960 case AT91C_EFC_FCMD_CLB
:
1961 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
1963 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1966 case AT91C_EFC_FCMD_SFB
:
1967 case AT91C_EFC_FCMD_CFB
:
1968 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1969 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1970 pPrivate
->pChip
->details
.n_gpnvms
);
1974 case AT91C_EFC_FCMD_GETD
:
1975 case AT91C_EFC_FCMD_EA
:
1976 case AT91C_EFC_FCMD_GLB
:
1977 case AT91C_EFC_FCMD_GFB
:
1978 case AT91C_EFC_FCMD_STUI
:
1979 case AT91C_EFC_FCMD_SPUI
:
1981 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1984 LOG_ERROR("Unknown command %d", command
);
1988 if (command
== AT91C_EFC_FCMD_SPUI
) {
1989 /* this is a very special situation. */
1990 /* Situation (1) - error/retry - see below */
1991 /* And we are being called recursively */
1992 /* Situation (2) - normal, finished reading unique id */
1994 /* it should be "ready" */
1995 EFC_GetStatus(pPrivate
, &v
);
1997 /* then it is ready */
2001 /* we have done this before */
2002 /* the controller is not responding. */
2003 LOG_ERROR("flash controller(%d) is not ready! Error",
2004 pPrivate
->bank_number
);
2008 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2009 pPrivate
->bank_number
);
2010 /* we do that by issuing the *STOP* command */
2011 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
2012 /* above is recursive, and further recursion is blocked by */
2013 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2019 v
= (0x5A << 24) | (argument
<< 8) | command
;
2020 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
2021 r
= target_write_u32(pPrivate
->pBank
->target
,
2022 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
2024 LOG_DEBUG("Error Write failed");
2029 * Performs the given command and wait until its completion (or an error).
2030 * @param pPrivate - info about the bank
2031 * @param command - Command to perform.
2032 * @param argument - Optional command argument.
2033 * @param status - put command status bits here
2035 static int EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
2043 long long ms_now
, ms_end
;
2049 r
= EFC_StartCommand(pPrivate
, command
, argument
);
2053 ms_end
= 500 + timeval_ms();
2056 r
= EFC_GetStatus(pPrivate
, &v
);
2059 ms_now
= timeval_ms();
2060 if (ms_now
> ms_end
) {
2062 LOG_ERROR("Command timeout");
2065 } while ((v
& 1) == 0);
2069 *status
= (v
& 0x6);
2075 * Read the unique ID.
2076 * @param pPrivate - info about the bank
2077 * The unique ID is stored in the 'pPrivate' structure.
2079 static int FLASHD_ReadUniqueID(struct sam3_bank_private
*pPrivate
)
2085 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
2086 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
2087 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
2088 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
2091 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
2095 for (x
= 0; x
< 4; x
++) {
2096 r
= target_read_u32(pPrivate
->pChip
->target
,
2097 pPrivate
->pBank
->base
+ (x
* 4),
2101 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
2104 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
2105 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2107 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
2108 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
2109 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
2110 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
2116 * Erases the entire flash.
2117 * @param pPrivate - the info about the bank.
2119 static int FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
2122 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
2126 * Gets current GPNVM state.
2127 * @param pPrivate - info about the bank.
2128 * @param gpnvm - GPNVM bit index.
2129 * @param puthere - result stored here.
2131 /* ------------------------------------------------------------------------------ */
2132 static int FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
2138 if (pPrivate
->bank_number
!= 0) {
2139 LOG_ERROR("GPNVM only works with Bank0");
2143 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2144 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2145 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2149 /* Get GPNVMs status */
2150 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
2151 if (r
!= ERROR_OK
) {
2152 LOG_ERROR("Failed");
2156 r
= EFC_GetResult(pPrivate
, &v
);
2159 /* Check if GPNVM is set */
2160 /* get the bit and make it a 0/1 */
2161 *puthere
= (v
>> gpnvm
) & 1;
2168 * Clears the selected GPNVM bit.
2169 * @param pPrivate info about the bank
2170 * @param gpnvm GPNVM index.
2171 * @returns 0 if successful; otherwise returns an error code.
2173 static int FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
2179 if (pPrivate
->bank_number
!= 0) {
2180 LOG_ERROR("GPNVM only works with Bank0");
2184 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2185 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2186 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2190 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
2191 if (r
!= ERROR_OK
) {
2192 LOG_DEBUG("Failed: %d", r
);
2195 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
2196 LOG_DEBUG("End: %d", r
);
2201 * Sets the selected GPNVM bit.
2202 * @param pPrivate info about the bank
2203 * @param gpnvm GPNVM index.
2205 static int FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
2210 if (pPrivate
->bank_number
!= 0) {
2211 LOG_ERROR("GPNVM only works with Bank0");
2215 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2216 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2217 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2221 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
2229 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
2235 * Returns a bit field (at most 64) of locked regions within a page.
2236 * @param pPrivate info about the bank
2237 * @param v where to store locked bits
2239 static int FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
2243 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
2245 r
= EFC_GetResult(pPrivate
, v
);
2246 LOG_DEBUG("End: %d", r
);
2251 * Unlocks all the regions in the given address range.
2252 * @param pPrivate info about the bank
2253 * @param start_sector first sector to unlock
2254 * @param end_sector last (inclusive) to unlock
2257 static int FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
2258 unsigned start_sector
,
2259 unsigned end_sector
)
2264 uint32_t pages_per_sector
;
2266 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2268 /* Unlock all pages */
2269 while (start_sector
<= end_sector
) {
2270 pg
= start_sector
* pages_per_sector
;
2272 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
2283 * @param pPrivate - info about the bank
2284 * @param start_sector - first sector to lock
2285 * @param end_sector - last sector (inclusive) to lock
2287 static int FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
2288 unsigned start_sector
,
2289 unsigned end_sector
)
2293 uint32_t pages_per_sector
;
2296 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2298 /* Lock all pages */
2299 while (start_sector
<= end_sector
) {
2300 pg
= start_sector
* pages_per_sector
;
2302 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
2310 /****** END SAM3 CODE ********/
2312 /* begin helpful debug code */
2313 /* print the fieldname, the field value, in dec & hex, and return field value */
2314 static uint32_t sam3_reg_fieldname(struct sam3_chip
*pChip
,
2315 const char *regname
,
2324 /* extract the field */
2326 v
= v
& ((1 << width
)-1);
2335 /* show the basics */
2336 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2337 REG_NAME_WIDTH
, regname
,
2343 static const char _unknown
[] = "unknown";
2344 static const char *const eproc_names
[] = {
2348 "cortex-m3", /* 3 */
2350 "arm926ejs", /* 5 */
2363 #define nvpsize2 nvpsize /* these two tables are identical */
2364 static const char *const nvpsize
[] = {
2367 "16K bytes", /* 2 */
2368 "32K bytes", /* 3 */
2370 "64K bytes", /* 5 */
2372 "128K bytes", /* 7 */
2374 "256K bytes", /* 9 */
2375 "512K bytes", /* 10 */
2377 "1024K bytes", /* 12 */
2379 "2048K bytes", /* 14 */
2383 static const char *const sramsize
[] = {
2384 "48K Bytes", /* 0 */
2388 "112K Bytes", /* 4 */
2390 "80K Bytes", /* 6 */
2391 "160K Bytes", /* 7 */
2393 "16K Bytes", /* 9 */
2394 "32K Bytes", /* 10 */
2395 "64K Bytes", /* 11 */
2396 "128K Bytes", /* 12 */
2397 "256K Bytes", /* 13 */
2398 "96K Bytes", /* 14 */
2399 "512K Bytes", /* 15 */
2403 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
2404 { 0x19, "AT91SAM9xx Series" },
2405 { 0x29, "AT91SAM9XExx Series" },
2406 { 0x34, "AT91x34 Series" },
2407 { 0x37, "CAP7 Series" },
2408 { 0x39, "CAP9 Series" },
2409 { 0x3B, "CAP11 Series" },
2410 { 0x40, "AT91x40 Series" },
2411 { 0x42, "AT91x42 Series" },
2412 { 0x55, "AT91x55 Series" },
2413 { 0x60, "AT91SAM7Axx Series" },
2414 { 0x61, "AT91SAM7AQxx Series" },
2415 { 0x63, "AT91x63 Series" },
2416 { 0x70, "AT91SAM7Sxx Series" },
2417 { 0x71, "AT91SAM7XCxx Series" },
2418 { 0x72, "AT91SAM7SExx Series" },
2419 { 0x73, "AT91SAM7Lxx Series" },
2420 { 0x75, "AT91SAM7Xxx Series" },
2421 { 0x76, "AT91SAM7SLxx Series" },
2422 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2423 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2424 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2425 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2426 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2427 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2428 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2429 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2430 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2431 { 0x92, "AT91x92 Series" },
2432 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2433 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2434 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2435 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2436 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2437 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2438 { 0xA5, "ATSAM5A" },
2439 { 0xF0, "AT75Cxx Series" },
2443 static const char *const nvptype
[] = {
2445 "romless or onchip flash", /* 1 */
2446 "embedded flash memory",/* 2 */
2447 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2448 "sram emulating flash", /* 4 */
2454 static const char *_yes_or_no(uint32_t v
)
2462 static const char *const _rc_freq
[] = {
2463 "4 MHz", "8 MHz", "12 MHz", "reserved"
2466 static void sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
2471 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
2472 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2473 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
2474 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2475 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
2476 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2477 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
2478 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2480 pChip
->cfg
.rc_freq
= 0;
2484 pChip
->cfg
.rc_freq
= 0;
2487 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2490 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2493 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2498 v
= sam3_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
2499 LOG_USER("(startup clks, time= %f uSecs)",
2500 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
2501 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
2502 LOG_USER("(mainosc source: %s)",
2503 v
? "external xtal" : "internal RC");
2505 v
= sam3_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
2506 LOG_USER("(clock failure enabled: %s)",
2510 static void sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
2516 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
2519 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
2520 LOG_USER("%s", eproc_names
[v
]);
2522 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
2523 LOG_USER("%s", nvpsize
[v
]);
2525 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
2526 LOG_USER("%s", nvpsize2
[v
]);
2528 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
2529 LOG_USER("%s", sramsize
[v
]);
2531 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
2533 for (x
= 0; archnames
[x
].name
; x
++) {
2534 if (v
== archnames
[x
].value
) {
2535 cp
= archnames
[x
].name
;
2542 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
2543 LOG_USER("%s", nvptype
[v
]);
2545 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
2546 LOG_USER("(exists: %s)", _yes_or_no(v
));
2549 static void sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
2553 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
2554 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2556 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
2558 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
2559 pChip
->cfg
.mainosc_freq
= v
;
2561 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2563 pChip
->cfg
.slow_freq
/ 1000,
2564 pChip
->cfg
.slow_freq
% 1000);
2567 static void sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
2569 uint32_t mula
, diva
;
2571 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2573 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2575 pChip
->cfg
.plla_freq
= 0;
2577 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2579 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2580 else if (diva
>= 1) {
2581 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
2582 LOG_USER("\tPLLA Freq: %3.03f MHz",
2583 _tomhz(pChip
->cfg
.plla_freq
));
2587 static void sam3_explain_mckr(struct sam3_chip
*pChip
)
2589 uint32_t css
, pres
, fin
= 0;
2591 const char *cp
= NULL
;
2593 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2596 fin
= pChip
->cfg
.slow_freq
;
2600 fin
= pChip
->cfg
.mainosc_freq
;
2604 fin
= pChip
->cfg
.plla_freq
;
2608 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2609 fin
= 480 * 1000 * 1000;
2613 cp
= "upll (*ERROR* UPLL is disabled)";
2621 LOG_USER("%s (%3.03f Mhz)",
2624 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2625 switch (pres
& 0x07) {
2628 cp
= "selected clock";
2662 LOG_USER("(%s)", cp
);
2664 /* sam3 has a *SINGLE* clock - */
2665 /* other at91 series parts have divisors for these. */
2666 pChip
->cfg
.cpu_freq
= fin
;
2667 pChip
->cfg
.mclk_freq
= fin
;
2668 pChip
->cfg
.fclk_freq
= fin
;
2669 LOG_USER("\t\tResult CPU Freq: %3.03f",
2674 static struct sam3_chip
*target2sam3(struct target
*pTarget
)
2676 struct sam3_chip
*pChip
;
2678 if (pTarget
== NULL
)
2681 pChip
= all_sam3_chips
;
2683 if (pChip
->target
== pTarget
)
2684 break; /* return below */
2686 pChip
= pChip
->next
;
2692 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
2694 /* this function exists to help */
2695 /* keep funky offsetof() errors */
2696 /* and casting from causing bugs */
2698 /* By using prototypes - we can detect what would */
2699 /* be casting errors. */
2701 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
2705 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2707 NAME), # NAME, FUNC }
2708 static const struct sam3_reg_list sam3_all_regs
[] = {
2709 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2710 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2711 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2712 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2713 SAM3_ENTRY(PMC_FSMR
, NULL
),
2714 SAM3_ENTRY(PMC_FSPR
, NULL
),
2715 SAM3_ENTRY(PMC_IMR
, NULL
),
2716 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2717 SAM3_ENTRY(PMC_PCK0
, NULL
),
2718 SAM3_ENTRY(PMC_PCK1
, NULL
),
2719 SAM3_ENTRY(PMC_PCK2
, NULL
),
2720 SAM3_ENTRY(PMC_PCSR
, NULL
),
2721 SAM3_ENTRY(PMC_SCSR
, NULL
),
2722 SAM3_ENTRY(PMC_SR
, NULL
),
2723 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2724 SAM3_ENTRY(CHIPID_CIDR2
, sam3_explain_chipid_cidr
),
2725 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2726 SAM3_ENTRY(CHIPID_EXID2
, NULL
),
2727 /* TERMINATE THE LIST */
2732 static struct sam3_bank_private
*get_sam3_bank_private(struct flash_bank
*bank
)
2734 return (struct sam3_bank_private
*)(bank
->driver_priv
);
2738 * Given a pointer to where it goes in the structure,
2739 * determine the register name, address from the all registers table.
2741 static const struct sam3_reg_list
*sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2743 const struct sam3_reg_list
*pReg
;
2745 pReg
= &(sam3_all_regs
[0]);
2746 while (pReg
->name
) {
2747 uint32_t *pPossible
;
2749 /* calculate where this one go.. */
2750 /* it is "possibly" this register. */
2752 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2754 /* well? Is it this register */
2755 if (pPossible
== goes_here
) {
2763 /* This is *TOTAL*PANIC* - we are totally screwed. */
2764 LOG_ERROR("INVALID SAM3 REGISTER");
2768 static int sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2770 const struct sam3_reg_list
*pReg
;
2773 pReg
= sam3_GetReg(pChip
, goes_here
);
2777 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2778 if (r
!= ERROR_OK
) {
2779 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2780 pReg
->name
, (unsigned)(pReg
->address
), r
);
2785 static int sam3_ReadAllRegs(struct sam3_chip
*pChip
)
2788 const struct sam3_reg_list
*pReg
;
2790 pReg
= &(sam3_all_regs
[0]);
2791 while (pReg
->name
) {
2792 r
= sam3_ReadThisReg(pChip
,
2793 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
2794 if (r
!= ERROR_OK
) {
2795 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2796 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2802 /* Chip identification register
2804 * Unfortunately, the chip identification register is not at
2805 * a constant address across all of the SAM3 series'. As a
2806 * consequence, a simple heuristic is used to find where it's
2809 * If the contents at the first address is zero, then we know
2810 * that the second address is where the chip id register is.
2811 * We can deduce this because for those SAM's that have the
2812 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2813 * located in the memory map of the Power Management Controller
2814 * (PMC). Furthermore, the address is not used by the PMC.
2815 * So when read, the memory controller returns zero.*/
2816 if (pChip
->cfg
.CHIPID_CIDR
== 0) {
2817 /*Put the correct CIDR and EXID values in the pChip structure */
2818 pChip
->cfg
.CHIPID_CIDR
= pChip
->cfg
.CHIPID_CIDR2
;
2819 pChip
->cfg
.CHIPID_EXID
= pChip
->cfg
.CHIPID_EXID2
;
2824 static int sam3_GetInfo(struct sam3_chip
*pChip
)
2826 const struct sam3_reg_list
*pReg
;
2829 pReg
= &(sam3_all_regs
[0]);
2830 while (pReg
->name
) {
2831 /* display all regs */
2832 LOG_DEBUG("Start: %s", pReg
->name
);
2833 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
2834 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2839 if (pReg
->explain_func
)
2840 (*(pReg
->explain_func
))(pChip
);
2841 LOG_DEBUG("End: %s", pReg
->name
);
2844 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2845 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2846 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2847 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2848 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2850 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2851 pChip
->cfg
.unique_id
[0],
2852 pChip
->cfg
.unique_id
[1],
2853 pChip
->cfg
.unique_id
[2],
2854 pChip
->cfg
.unique_id
[3]);
2859 static int sam3_erase_check(struct flash_bank
*bank
)
2864 if (bank
->target
->state
!= TARGET_HALTED
) {
2865 LOG_ERROR("Target not halted");
2866 return ERROR_TARGET_NOT_HALTED
;
2868 if (0 == bank
->num_sectors
) {
2869 LOG_ERROR("Target: not supported/not probed");
2873 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2874 for (x
= 0; x
< bank
->num_sectors
; x
++)
2875 bank
->sectors
[x
].is_erased
= 1;
2881 static int sam3_protect_check(struct flash_bank
*bank
)
2886 struct sam3_bank_private
*pPrivate
;
2889 if (bank
->target
->state
!= TARGET_HALTED
) {
2890 LOG_ERROR("Target not halted");
2891 return ERROR_TARGET_NOT_HALTED
;
2894 pPrivate
= get_sam3_bank_private(bank
);
2896 LOG_ERROR("no private for this bank?");
2899 if (!(pPrivate
->probed
))
2900 return ERROR_FLASH_BANK_NOT_PROBED
;
2902 r
= FLASHD_GetLockBits(pPrivate
, &v
);
2903 if (r
!= ERROR_OK
) {
2904 LOG_DEBUG("Failed: %d", r
);
2908 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
2909 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
2914 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
2916 struct sam3_chip
*pChip
;
2918 pChip
= all_sam3_chips
;
2920 /* is this an existing chip? */
2922 if (pChip
->target
== bank
->target
)
2924 pChip
= pChip
->next
;
2928 /* this is a *NEW* chip */
2929 pChip
= calloc(1, sizeof(struct sam3_chip
));
2931 LOG_ERROR("NO RAM!");
2934 pChip
->target
= bank
->target
;
2935 /* insert at head */
2936 pChip
->next
= all_sam3_chips
;
2937 all_sam3_chips
= pChip
;
2938 pChip
->target
= bank
->target
;
2939 /* assumption is this runs at 32khz */
2940 pChip
->cfg
.slow_freq
= 32768;
2944 switch (bank
->base
) {
2946 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2947 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2948 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2949 ((unsigned int)(bank
->base
)),
2950 ((unsigned int)(FLASH_BANK0_BASE_U
)),
2951 ((unsigned int)(FLASH_BANK1_BASE_U
)),
2952 ((unsigned int)(FLASH_BANK_BASE_S
)),
2953 ((unsigned int)(FLASH_BANK_BASE_N
)),
2954 ((unsigned int)(FLASH_BANK0_BASE_AX
)),
2955 ((unsigned int)(FLASH_BANK1_BASE_256K_AX
)),
2956 ((unsigned int)(FLASH_BANK1_BASE_512K_AX
)));
2960 /* at91sam3s and at91sam3n series only has bank 0*/
2961 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2962 case FLASH_BANK_BASE_S
:
2963 case FLASH_BANK0_BASE_U
:
2964 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2965 bank
->bank_number
= 0;
2966 pChip
->details
.bank
[0].pChip
= pChip
;
2967 pChip
->details
.bank
[0].pBank
= bank
;
2970 /* Bank 1 of at91sam3u or at91sam3ax series */
2971 case FLASH_BANK1_BASE_U
:
2972 case FLASH_BANK1_BASE_256K_AX
:
2973 case FLASH_BANK1_BASE_512K_AX
:
2974 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
2975 bank
->bank_number
= 1;
2976 pChip
->details
.bank
[1].pChip
= pChip
;
2977 pChip
->details
.bank
[1].pBank
= bank
;
2981 /* we initialize after probing. */
2985 static int sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
2987 const struct sam3_chip_details
*pDetails
;
2988 struct sam3_chip
*pChip
;
2989 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
2993 pDetails
= all_sam3_details
;
2994 while (pDetails
->name
) {
2995 /* Compare cidr without version bits */
2996 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
3001 if (pDetails
->name
== NULL
) {
3002 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3003 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
3004 /* Help the victim, print details about the chip */
3005 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
3006 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
3007 sam3_explain_chipid_cidr(pPrivate
->pChip
);
3011 /* DANGER: THERE ARE DRAGONS HERE */
3013 /* get our pChip - it is going */
3014 /* to be over-written shortly */
3015 pChip
= pPrivate
->pChip
;
3017 /* Note that, in reality: */
3019 /* pPrivate = &(pChip->details.bank[0]) */
3020 /* or pPrivate = &(pChip->details.bank[1]) */
3023 /* save the "bank" pointers */
3024 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++)
3025 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
3027 /* Overwrite the "details" structure. */
3028 memcpy(&(pPrivate
->pChip
->details
),
3030 sizeof(pPrivate
->pChip
->details
));
3032 /* now fix the ghosted pointers */
3033 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3034 pChip
->details
.bank
[x
].pChip
= pChip
;
3035 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
3038 /* update the *BANK*SIZE* */
3044 static int _sam3_probe(struct flash_bank
*bank
, int noise
)
3048 struct sam3_bank_private
*pPrivate
;
3051 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
3052 if (bank
->target
->state
!= TARGET_HALTED
) {
3053 LOG_ERROR("Target not halted");
3054 return ERROR_TARGET_NOT_HALTED
;
3057 pPrivate
= get_sam3_bank_private(bank
);
3059 LOG_ERROR("Invalid/unknown bank number");
3063 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
3068 if (pPrivate
->pChip
->probed
)
3069 r
= sam3_GetInfo(pPrivate
->pChip
);
3071 r
= sam3_GetDetails(pPrivate
);
3075 /* update the flash bank size */
3076 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3077 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
3078 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
3083 if (bank
->sectors
== NULL
) {
3084 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
3085 if (bank
->sectors
== NULL
) {
3086 LOG_ERROR("No memory!");
3089 bank
->num_sectors
= pPrivate
->nsectors
;
3091 for (x
= 0; ((int)(x
)) < bank
->num_sectors
; x
++) {
3092 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
3093 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
3094 /* mark as unknown */
3095 bank
->sectors
[x
].is_erased
= -1;
3096 bank
->sectors
[x
].is_protected
= -1;
3100 pPrivate
->probed
= 1;
3102 r
= sam3_protect_check(bank
);
3106 LOG_DEBUG("Bank = %d, nbanks = %d",
3107 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
3108 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
3109 /* read unique id, */
3110 /* it appears to be associated with the *last* flash bank. */
3111 FLASHD_ReadUniqueID(pPrivate
);
3117 static int sam3_probe(struct flash_bank
*bank
)
3119 return _sam3_probe(bank
, 1);
3122 static int sam3_auto_probe(struct flash_bank
*bank
)
3124 return _sam3_probe(bank
, 0);
3127 static int sam3_erase(struct flash_bank
*bank
, int first
, int last
)
3129 struct sam3_bank_private
*pPrivate
;
3133 if (bank
->target
->state
!= TARGET_HALTED
) {
3134 LOG_ERROR("Target not halted");
3135 return ERROR_TARGET_NOT_HALTED
;
3138 r
= sam3_auto_probe(bank
);
3139 if (r
!= ERROR_OK
) {
3140 LOG_DEBUG("Here,r=%d", r
);
3144 pPrivate
= get_sam3_bank_private(bank
);
3145 if (!(pPrivate
->probed
))
3146 return ERROR_FLASH_BANK_NOT_PROBED
;
3148 if ((first
== 0) && ((last
+ 1) == ((int)(pPrivate
->nsectors
)))) {
3151 return FLASHD_EraseEntireBank(pPrivate
);
3153 LOG_INFO("sam3 auto-erases while programming (request ignored)");
3157 static int sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
3159 struct sam3_bank_private
*pPrivate
;
3163 if (bank
->target
->state
!= TARGET_HALTED
) {
3164 LOG_ERROR("Target not halted");
3165 return ERROR_TARGET_NOT_HALTED
;
3168 pPrivate
= get_sam3_bank_private(bank
);
3169 if (!(pPrivate
->probed
))
3170 return ERROR_FLASH_BANK_NOT_PROBED
;
3173 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
3175 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
3176 LOG_DEBUG("End: r=%d", r
);
3182 static int sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
3187 adr
= pagenum
* pPrivate
->page_size
;
3188 adr
+= pPrivate
->base_address
;
3190 r
= target_read_memory(pPrivate
->pChip
->target
,
3192 4, /* THIS*MUST*BE* in 32bit values */
3193 pPrivate
->page_size
/ 4,
3196 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3197 (unsigned int)(adr
));
3201 /* The code below is basically this: */
3203 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3205 /* Only the *CPU* can write to the flash buffer. */
3206 /* the DAP cannot... so - we download this 28byte thing */
3207 /* Run the algorithm - (below) */
3208 /* to program the device */
3210 /* ======================================== */
3211 /* #include <stdint.h> */
3214 /* uint32_t *dst; */
3215 /* const uint32_t *src; */
3217 /* volatile uint32_t *base; */
3222 /* uint32_t sam3_function(struct foo *p) */
3224 /* volatile uint32_t *v; */
3226 /* const uint32_t *s; */
3241 /* v[ 1 ] = p->cmd; */
3244 /* } while (!(r&1)) */
3248 /* ======================================== */
3250 static const uint8_t
3251 sam3_page_write_opcodes
[] = {
3252 /* 24 0000 0446 mov r4, r0 */
3254 /* 25 0002 6168 ldr r1, [r4, #4] */
3256 /* 26 0004 0068 ldr r0, [r0, #0] */
3258 /* 27 0006 A268 ldr r2, [r4, #8] */
3260 /* 28 @ lr needed for prologue */
3262 /* 30 0008 51F8043B ldr r3, [r1], #4 */
3263 0x51, 0xf8, 0x04, 0x3b,
3264 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
3265 0x12, 0xf1, 0xff, 0x32,
3266 /* 32 0010 40F8043B str r3, [r0], #4 */
3267 0x40, 0xf8, 0x04, 0x3b,
3268 /* 33 0014 F8D1 bne .L2 */
3270 /* 34 0016 E268 ldr r2, [r4, #12] */
3272 /* 35 0018 2369 ldr r3, [r4, #16] */
3274 /* 36 001a 5360 str r3, [r2, #4] */
3276 /* 37 001c 0832 adds r2, r2, #8 */
3279 /* 39 001e 1068 ldr r0, [r2, #0] */
3281 /* 40 0020 10F0010F tst r0, #1 */
3282 0x10, 0xf0, 0x01, 0x0f,
3283 /* 41 0024 FBD0 beq .L4 */
3285 0x00, 0xBE /* bkpt #0 */
3288 static int sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
3292 uint32_t fmr
; /* EEFC Flash Mode Register */
3295 adr
= pagenum
* pPrivate
->page_size
;
3296 adr
+= pPrivate
->base_address
;
3298 /* Get flash mode register value */
3299 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
3301 LOG_DEBUG("Error Read failed: read flash mode register");
3303 /* Clear flash wait state field */
3306 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3307 fmr
|= (pPrivate
->flash_wait_states
<< 8);
3309 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
3310 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
3312 LOG_DEBUG("Error Write failed: set flash mode register");
3314 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
3315 r
= target_write_memory(pPrivate
->pChip
->target
,
3317 4, /* THIS*MUST*BE* in 32bit values */
3318 pPrivate
->page_size
/ 4,
3320 if (r
!= ERROR_OK
) {
3321 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3322 (unsigned int)(adr
));
3326 r
= EFC_PerformCommand(pPrivate
,
3327 /* send Erase & Write Page */
3333 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3334 (unsigned int)(adr
));
3335 if (status
& (1 << 2)) {
3336 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
3339 if (status
& (1 << 1)) {
3340 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
3346 static int sam3_write(struct flash_bank
*bank
,
3355 unsigned page_offset
;
3356 struct sam3_bank_private
*pPrivate
;
3357 uint8_t *pagebuffer
;
3359 /* incase we bail further below, set this to null */
3362 /* ignore dumb requests */
3368 if (bank
->target
->state
!= TARGET_HALTED
) {
3369 LOG_ERROR("Target not halted");
3370 r
= ERROR_TARGET_NOT_HALTED
;
3374 pPrivate
= get_sam3_bank_private(bank
);
3375 if (!(pPrivate
->probed
)) {
3376 r
= ERROR_FLASH_BANK_NOT_PROBED
;
3380 if ((offset
+ count
) > pPrivate
->size_bytes
) {
3381 LOG_ERROR("Flash write error - past end of bank");
3382 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3383 (unsigned int)(offset
),
3384 (unsigned int)(count
),
3385 (unsigned int)(pPrivate
->size_bytes
));
3390 pagebuffer
= malloc(pPrivate
->page_size
);
3392 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
3397 /* what page do we start & end in? */
3398 page_cur
= offset
/ pPrivate
->page_size
;
3399 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
3401 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
3402 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
3404 /* Special case: all one page */
3407 /* (1) non-aligned start */
3408 /* (2) body pages */
3409 /* (3) non-aligned end. */
3411 /* Handle special case - all one page. */
3412 if (page_cur
== page_end
) {
3413 LOG_DEBUG("Special case, all in one page");
3414 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3418 page_offset
= (offset
& (pPrivate
->page_size
-1));
3419 memcpy(pagebuffer
+ page_offset
,
3423 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3430 /* non-aligned start */
3431 page_offset
= offset
& (pPrivate
->page_size
- 1);
3433 LOG_DEBUG("Not-Aligned start");
3434 /* read the partial */
3435 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3439 /* over-write with new data */
3440 n
= (pPrivate
->page_size
- page_offset
);
3441 memcpy(pagebuffer
+ page_offset
,
3445 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3455 /* By checking that offset is correct here, we also
3456 fix a clang warning */
3457 assert(offset
% pPrivate
->page_size
== 0);
3459 /* intermediate large pages */
3460 /* also - the final *terminal* */
3461 /* if that terminal page is a full page */
3462 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3463 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3465 while ((page_cur
< page_end
) &&
3466 (count
>= pPrivate
->page_size
)) {
3467 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
3470 count
-= pPrivate
->page_size
;
3471 buffer
+= pPrivate
->page_size
;
3475 /* terminal partial page? */
3477 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3478 /* we have a partial page */
3479 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3482 /* data goes at start */
3483 memcpy(pagebuffer
, buffer
, count
);
3484 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3496 COMMAND_HANDLER(sam3_handle_info_command
)
3498 struct sam3_chip
*pChip
;
3499 pChip
= get_current_sam3(CMD_CTX
);
3506 /* bank0 must exist before we can do anything */
3507 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3510 command_print(CMD_CTX
,
3511 "Please define bank %d via command: flash bank %s ... ",
3513 at91sam3_flash
.name
);
3517 /* if bank 0 is not probed, then probe it */
3518 if (!(pChip
->details
.bank
[0].probed
)) {
3519 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3523 /* above guarantees the "chip details" structure is valid */
3524 /* and thus, bank private areas are valid */
3525 /* and we have a SAM3 chip, what a concept! */
3527 /* auto-probe other banks, 0 done above */
3528 for (x
= 1; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3529 /* skip banks not present */
3530 if (!(pChip
->details
.bank
[x
].present
))
3533 if (pChip
->details
.bank
[x
].pBank
== NULL
)
3536 if (pChip
->details
.bank
[x
].probed
)
3539 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
3544 r
= sam3_GetInfo(pChip
);
3545 if (r
!= ERROR_OK
) {
3546 LOG_DEBUG("Sam3Info, Failed %d", r
);
3553 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3557 struct sam3_chip
*pChip
;
3559 pChip
= get_current_sam3(CMD_CTX
);
3563 if (pChip
->target
->state
!= TARGET_HALTED
) {
3564 LOG_ERROR("sam3 - target not halted");
3565 return ERROR_TARGET_NOT_HALTED
;
3568 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3569 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
3570 at91sam3_flash
.name
);
3573 if (!pChip
->details
.bank
[0].probed
) {
3574 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3581 return ERROR_COMMAND_SYNTAX_ERROR
;
3590 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
3594 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3600 if (0 == strcmp("show", CMD_ARGV
[0])) {
3604 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
3605 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3608 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
3612 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3613 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3614 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
3617 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
3618 return ERROR_COMMAND_SYNTAX_ERROR
;
3623 command_print(CMD_CTX
, "Missing GPNVM number");
3624 return ERROR_COMMAND_SYNTAX_ERROR
;
3627 if (0 == strcmp("set", CMD_ARGV
[0]))
3628 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3629 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3630 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
3631 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3633 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
3634 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3639 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3641 struct sam3_chip
*pChip
;
3643 pChip
= get_current_sam3(CMD_CTX
);
3655 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3657 /* absurd slow clock of 200Khz? */
3658 command_print(CMD_CTX
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3659 return ERROR_COMMAND_SYNTAX_ERROR
;
3661 pChip
->cfg
.slow_freq
= v
;
3666 command_print(CMD_CTX
, "Too many parameters");
3667 return ERROR_COMMAND_SYNTAX_ERROR
;
3670 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
3671 (int)(pChip
->cfg
.slow_freq
/ 1000),
3672 (int)(pChip
->cfg
.slow_freq
% 1000));
3676 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3679 .handler
= sam3_handle_gpnvm_command
,
3680 .mode
= COMMAND_EXEC
,
3681 .usage
= "[('clr'|'set'|'show') bitnum]",
3682 .help
= "Without arguments, shows all bits in the gpnvm "
3683 "register. Otherwise, clears, sets, or shows one "
3684 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3688 .handler
= sam3_handle_info_command
,
3689 .mode
= COMMAND_EXEC
,
3690 .help
= "Print information about the current at91sam3 chip"
3691 "and its flash configuration.",
3695 .handler
= sam3_handle_slowclk_command
,
3696 .mode
= COMMAND_EXEC
,
3697 .usage
= "[clock_hz]",
3698 .help
= "Display or set the slowclock frequency "
3699 "(default 32768 Hz).",
3701 COMMAND_REGISTRATION_DONE
3703 static const struct command_registration at91sam3_command_handlers
[] = {
3706 .mode
= COMMAND_ANY
,
3707 .help
= "at91sam3 flash command group",
3709 .chain
= at91sam3_exec_command_handlers
,
3711 COMMAND_REGISTRATION_DONE
3714 struct flash_driver at91sam3_flash
= {
3716 .commands
= at91sam3_command_handlers
,
3717 .flash_bank_command
= sam3_flash_bank_command
,
3718 .erase
= sam3_erase
,
3719 .protect
= sam3_protect
,
3720 .write
= sam3_write
,
3721 .read
= default_flash_read
,
3722 .probe
= sam3_probe
,
3723 .auto_probe
= sam3_auto_probe
,
3724 .erase_check
= sam3_erase_check
,
3725 .protect_check
= sam3_protect_check
,