1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Cadence virtual debug interface
3 # RISCV swerv core with Swerv through JTAG
5 source [find interface/vdebug.cfg]
9 set _CPUTAPID 0x1000008b
10 set _MEMSTART 0x00000000
13 # vdebug select transport
16 # JTAG reset config, frequency and reset delay
17 reset_config trst_and_srst
21 # BFM hierarchical path and input clk period
22 vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
24 # DMA Memories to access backdoor (up to 4)
25 vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE
27 # need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
28 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
32 source [find target/vd_riscv.cfg]