1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # If you want to use the VJTAG TAP or the XILINX BSCAN,
4 # you must set your FPGA TAP ID here
6 set FPGATAPID 0x020b30dd
8 # Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
9 if { [info exists TAP_TYPE] == 0} {
16 source [find target/or1k.cfg]
18 # Set the servers polling period to 1ms (needed to JSP Server)
21 # Set the adapter speed
24 # Enable the target description feature
25 gdb_target_description enable
27 # Add a new register in the cpu register list. This register will be
28 # included in the generated target descriptor file.
29 # format is addreg [name] [address] [feature] [reg_group]
30 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
32 # Override default init_reset
33 proc init_reset {mode} {
38 # Target initialization
40 echo "Halting processor"
43 foreach name [target names] {
44 set y [$name cget -endian]
45 set z [$name cget -type]
46 puts [format "Chip is %s, Endian: %s, type: %s" \
50 set c_blue "\033\[01;34m"
51 set c_reset "\033\[0m"
53 puts [format "%sTarget ready...%s" $c_blue $c_reset]