src/target/arm920t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm920t.h"
  25 #include "time_support.h"
  26 #include "target_type.h"
  27
  28
  29 #if 0
  30 #define _DEBUG_INSTRUCTION_EXECUTION_
  31 #endif
  32
  33 /* cli handling */
  34 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  36 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37 int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  38 int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  39
  40 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42
  43 /* forward declarations */
  44 int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
  45 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  46
  47 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
  48
  49 target_type_t arm920t_target =
  50 {
  51         .name = "arm920t",
  52
  53         .poll = arm7_9_poll,
  54         .arch_state = arm920t_arch_state,
  55
  56         .target_request_data = arm7_9_target_request_data,
  57
  58         .halt = arm7_9_halt,
  59         .resume = arm7_9_resume,
  60         .step = arm7_9_step,
  61
  62         .assert_reset = arm7_9_assert_reset,
  63         .deassert_reset = arm7_9_deassert_reset,
  64         .soft_reset_halt = arm920t_soft_reset_halt,
  65
  66         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  67
  68         .read_memory = arm920t_read_memory,
  69         .write_memory = arm920t_write_memory,
  70         .read_phys_memory = arm920t_read_phys_memory,
  71         .write_phys_memory = arm920t_write_phys_memory,
  72         .bulk_write_memory = arm7_9_bulk_write_memory,
  73         .checksum_memory = arm7_9_checksum_memory,
  74         .blank_check_memory = arm7_9_blank_check_memory,
  75
  76         .run_algorithm = armv4_5_run_algorithm,
  77
  78         .add_breakpoint = arm7_9_add_breakpoint,
  79         .remove_breakpoint = arm7_9_remove_breakpoint,
  80         .add_watchpoint = arm7_9_add_watchpoint,
  81         .remove_watchpoint = arm7_9_remove_watchpoint,
  82
  83         .register_commands = arm920t_register_commands,
  84         .target_create = arm920t_target_create,
  85         .init_target = arm920t_init_target,
  86         .examine = arm9tdmi_examine,
  87 };
  88
  89 int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
  90 {
  91         armv4_5_common_t *armv4_5 = target->arch_info;
  92         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  93         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  94         scan_field_t fields[4];
  95         uint8_t access_type_buf = 1;
  96         uint8_t reg_addr_buf = reg_addr & 0x3f;
  97         uint8_t nr_w_buf = 0;
  98
  99         jtag_set_end_state(TAP_IDLE);
 100         arm_jtag_scann(jtag_info, 0xf);
 101         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 102
 103         fields[0].tap = jtag_info->tap;
 104         fields[0].num_bits = 1;
 105         fields[0].out_value = &access_type_buf;
 106         fields[0].in_value = NULL;
 107
 108         fields[1].tap = jtag_info->tap;
 109         fields[1].num_bits = 32;
 110         fields[1].out_value = NULL;
 111         fields[1].in_value = NULL;
 112
 113         fields[2].tap = jtag_info->tap;
 114         fields[2].num_bits = 6;
 115         fields[2].out_value = &reg_addr_buf;
 116         fields[2].in_value = NULL;
 117
 118         fields[3].tap = jtag_info->tap;
 119         fields[3].num_bits = 1;
 120         fields[3].out_value = &nr_w_buf;
 121         fields[3].in_value = NULL;
 122
 123         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 124
 125         fields[1].in_value = (uint8_t *)value;
 126
 127         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 128
 129         jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 130
 131         #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 132         jtag_execute_queue();
 133         LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 134 #endif
 135
 136         return ERROR_OK;
 137 }
 138
 139 int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
 140 {
 141         armv4_5_common_t *armv4_5 = target->arch_info;
 142         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 143         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 144         scan_field_t fields[4];
 145         uint8_t access_type_buf = 1;
 146         uint8_t reg_addr_buf = reg_addr & 0x3f;
 147         uint8_t nr_w_buf = 1;
 148         uint8_t value_buf[4];
 149
 150         buf_set_u32(value_buf, 0, 32, value);
 151
 152         jtag_set_end_state(TAP_IDLE);
 153         arm_jtag_scann(jtag_info, 0xf);
 154         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 155
 156         fields[0].tap = jtag_info->tap;
 157         fields[0].num_bits = 1;
 158         fields[0].out_value = &access_type_buf;
 159         fields[0].in_value = NULL;
 160
 161         fields[1].tap = jtag_info->tap;
 162         fields[1].num_bits = 32;
 163         fields[1].out_value = value_buf;
 164         fields[1].in_value = NULL;
 165
 166         fields[2].tap = jtag_info->tap;
 167         fields[2].num_bits = 6;
 168         fields[2].out_value = &reg_addr_buf;
 169         fields[2].in_value = NULL;
 170
 171         fields[3].tap = jtag_info->tap;
 172         fields[3].num_bits = 1;
 173         fields[3].out_value = &nr_w_buf;
 174         fields[3].in_value = NULL;
 175
 176         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 177
 178 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 179         LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
 180 #endif
 181
 182         return ERROR_OK;
 183 }
 184
 185 int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
 186 {
 187         int retval;
 188         armv4_5_common_t *armv4_5 = target->arch_info;
 189         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 190         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 191         scan_field_t fields[4];
 192         uint8_t access_type_buf = 0;            /* interpreted access */
 193         uint8_t reg_addr_buf = 0x0;
 194         uint8_t nr_w_buf = 0;
 195         uint8_t cp15_opcode_buf[4];
 196
 197         jtag_set_end_state(TAP_IDLE);
 198         arm_jtag_scann(jtag_info, 0xf);
 199         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 200
 201         buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 202
 203         fields[0].tap = jtag_info->tap;
 204         fields[0].num_bits = 1;
 205         fields[0].out_value = &access_type_buf;
 206         fields[0].in_value = NULL;
 207
 208         fields[1].tap = jtag_info->tap;
 209         fields[1].num_bits = 32;
 210         fields[1].out_value = cp15_opcode_buf;
 211         fields[1].in_value = NULL;
 212
 213         fields[2].tap = jtag_info->tap;
 214         fields[2].num_bits = 6;
 215         fields[2].out_value = &reg_addr_buf;
 216         fields[2].in_value = NULL;
 217
 218         fields[3].tap = jtag_info->tap;
 219         fields[3].num_bits = 1;
 220         fields[3].out_value = &nr_w_buf;
 221         fields[3].in_value = NULL;
 222
 223         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 224
 225         arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 226         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 227         retval = arm7_9_execute_sys_speed(target);
 228         if (retval != ERROR_OK)
 229                 return retval;
 230
 231         if ((retval = jtag_execute_queue()) != ERROR_OK)
 232         {
 233                 LOG_ERROR("failed executing JTAG queue, exiting");
 234                 return retval;
 235         }
 236
 237         return ERROR_OK;
 238 }
 239
 240 int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 241 {
 242         armv4_5_common_t *armv4_5 = target->arch_info;
 243         uint32_t* regs_p[1];
 244         uint32_t regs[2];
 245         uint32_t cp15c15 = 0x0;
 246
 247         /* load address into R1 */
 248         regs[1] = address;
 249         arm9tdmi_write_core_regs(target, 0x2, regs);
 250
 251         /* read-modify-write CP15 test state register
 252         * to enable interpreted access mode */
 253         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 254         jtag_execute_queue();
 255         cp15c15 |= 1;   /* set interpret mode */
 256         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 257
 258         /* execute CP15 instruction and ARM load (reading from coprocessor) */
 259         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 260
 261         /* disable interpreted access mode */
 262         cp15c15 &= ~1U; /* clear interpret mode */
 263         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 264
 265         /* retrieve value from R0 */
 266         regs_p[0] = value;
 267         arm9tdmi_read_core_regs(target, 0x1, regs_p);
 268         jtag_execute_queue();
 269
 270 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 271         LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 272 #endif
 273
 274         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 275                 return ERROR_FAIL;
 276
 277         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 278         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 279
 280         return ERROR_OK;
 281 }
 282
 283 int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
 284 {
 285         uint32_t cp15c15 = 0x0;
 286         armv4_5_common_t *armv4_5 = target->arch_info;
 287         uint32_t regs[2];
 288
 289         /* load value, address into R0, R1 */
 290         regs[0] = value;
 291         regs[1] = address;
 292         arm9tdmi_write_core_regs(target, 0x3, regs);
 293
 294         /* read-modify-write CP15 test state register
 295         * to enable interpreted access mode */
 296         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 297         jtag_execute_queue();
 298         cp15c15 |= 1;   /* set interpret mode */
 299         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 300
 301         /* execute CP15 instruction and ARM store (writing to coprocessor) */
 302         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 303
 304         /* disable interpreted access mode */
 305         cp15c15 &= ~1U; /* set interpret mode */
 306         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 307
 308 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 309         LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 310 #endif
 311
 312         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 313                 return ERROR_FAIL;
 314
 315         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 316         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 317
 318         return ERROR_OK;
 319 }
 320
 321 uint32_t arm920t_get_ttb(target_t *target)
 322 {
 323         int retval;
 324         uint32_t ttb = 0x0;
 325
 326         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 327                 return retval;
 328
 329         return ttb;
 330 }
 331
 332 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 333 {
 334         uint32_t cp15_control;
 335
 336         /* read cp15 control register */
 337         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 338         jtag_execute_queue();
 339
 340         if (mmu)
 341                 cp15_control &= ~0x1U;
 342
 343         if (d_u_cache)
 344                 cp15_control &= ~0x4U;
 345
 346         if (i_cache)
 347                 cp15_control &= ~0x1000U;
 348
 349         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 350 }
 351
 352 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 353 {
 354         uint32_t cp15_control;
 355
 356         /* read cp15 control register */
 357         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 358         jtag_execute_queue();
 359
 360         if (mmu)
 361                 cp15_control |= 0x1U;
 362
 363         if (d_u_cache)
 364                 cp15_control |= 0x4U;
 365
 366         if (i_cache)
 367                 cp15_control |= 0x1000U;
 368
 369         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 370 }
 371
 372 void arm920t_post_debug_entry(target_t *target)
 373 {
 374         uint32_t cp15c15;
 375         armv4_5_common_t *armv4_5 = target->arch_info;
 376         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 377         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 378         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 379
 380         /* examine cp15 control reg */
 381         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 382         jtag_execute_queue();
 383         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
 384
 385         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 386         {
 387                 uint32_t cache_type_reg;
 388                 /* identify caches */
 389                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 390                 jtag_execute_queue();
 391                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 392         }
 393
 394         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
 395         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 396         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 397
 398         /* save i/d fault status and address register */
 399         arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 400         arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 401         arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 402         arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 403
 404         LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
 405                 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 406
 407         if (arm920t->preserve_cache)
 408         {
 409                 /* read-modify-write CP15 test state register
 410                  * to disable I/D-cache linefills */
 411                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 412                 jtag_execute_queue();
 413                 cp15c15 |= 0x600;
 414                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 415         }
 416 }
 417
 418 void arm920t_pre_restore_context(target_t *target)
 419 {
 420         uint32_t cp15c15;
 421         armv4_5_common_t *armv4_5 = target->arch_info;
 422         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 423         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 424         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 425
 426         /* restore i/d fault status and address register */
 427         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
 428         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
 429         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
 430         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
 431
 432         /* read-modify-write CP15 test state register
 433         * to reenable I/D-cache linefills */
 434         if (arm920t->preserve_cache)
 435         {
 436                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 437                 jtag_execute_queue();
 438                 cp15c15 &= ~0x600U;
 439                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 440         }
 441 }
 442
 443 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
 444 {
 445         armv4_5_common_t *armv4_5 = target->arch_info;
 446         arm7_9_common_t *arm7_9;
 447         arm9tdmi_common_t *arm9tdmi;
 448         arm920t_common_t *arm920t;
 449
 450         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 451         {
 452                 return -1;
 453         }
 454
 455         arm7_9 = armv4_5->arch_info;
 456         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 457         {
 458                 return -1;
 459         }
 460
 461         arm9tdmi = arm7_9->arch_info;
 462         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 463         {
 464                 return -1;
 465         }
 466
 467         arm920t = arm9tdmi->arch_info;
 468         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
 469         {
 470                 return -1;
 471         }
 472
 473         *armv4_5_p = armv4_5;
 474         *arm7_9_p = arm7_9;
 475         *arm9tdmi_p = arm9tdmi;
 476         *arm920t_p = arm920t;
 477
 478         return ERROR_OK;
 479 }
 480
 481 int arm920t_arch_state(struct target_s *target)
 482 {
 483         armv4_5_common_t *armv4_5 = target->arch_info;
 484         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 485         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 486         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 487
 488         char *state[] =
 489         {
 490                 "disabled", "enabled"
 491         };
 492
 493         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 494         {
 495                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 496                 exit(-1);
 497         }
 498
 499         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 500                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 501                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 502                          armv4_5_state_strings[armv4_5->core_state],
 503                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 504                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 505                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 506                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 507                          state[arm920t->armv4_5_mmu.mmu_enabled],
 508                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 509                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 510
 511         return ERROR_OK;
 512 }
 513
 514 int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 515 {
 516         int retval;
 517
 518         retval = arm7_9_read_memory(target, address, size, count, buffer);
 519
 520         return retval;
 521 }
 522
 523
 524 int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 525 {
 526         armv4_5_common_t *armv4_5 = target->arch_info;
 527         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 528         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 529         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 530
 531         return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
 532 }
 533
 534 int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 535 {
 536         armv4_5_common_t *armv4_5 = target->arch_info;
 537         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 538         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 539         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 540
 541         return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
 542 }
 543
 544
 545 int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 546 {
 547         int retval;
 548         armv4_5_common_t *armv4_5 = target->arch_info;
 549         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 550         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 551         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 552
 553         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 554                 return retval;
 555
 556         /* This fn is used to write breakpoints, so we need to make sure that the
 557          * datacache is flushed and the instruction cache is invalidated */
 558         if (((size == 4) || (size == 2)) && (count == 1))
 559         {
 560                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 561                 {
 562                         LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
 563                         /* MCR p15,0,Rd,c7,c10,2 */
 564                         retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
 565                         if (retval != ERROR_OK)
 566                                 return retval;
 567                 }
 568
 569                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 570                 {
 571                         LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
 572                         retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
 573                         if (retval != ERROR_OK)
 574                                 return retval;
 575                 }
 576         }
 577
 578         return retval;
 579 }
 580
 581 int arm920t_soft_reset_halt(struct target_s *target)
 582 {
 583         int retval = ERROR_OK;
 584         armv4_5_common_t *armv4_5 = target->arch_info;
 585         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 586         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 587         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 588         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 589
 590         if ((retval = target_halt(target)) != ERROR_OK)
 591         {
 592                 return retval;
 593         }
 594
 595         long long then = timeval_ms();
 596         int timeout;
 597         while (!(timeout = ((timeval_ms()-then) > 1000)))
 598         {
 599                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 600                 {
 601                         embeddedice_read_reg(dbg_stat);
 602                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 603                         {
 604                                 return retval;
 605                         }
 606                 } else
 607                 {
 608                         break;
 609                 }
 610                 if (debug_level >= 3)
 611                 {
 612                         /* do not eat all CPU, time out after 1 se*/
 613                         alive_sleep(100);
 614                 } else
 615                 {
 616                         keep_alive();
 617                 }
 618         }
 619         if (timeout)
 620         {
 621                 LOG_ERROR("Failed to halt CPU after 1 sec");
 622                 return ERROR_TARGET_TIMEOUT;
 623         }
 624
 625         target->state = TARGET_HALTED;
 626
 627         /* SVC, ARM state, IRQ and FIQ disabled */
 628         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 629         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 630         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 631
 632         /* start fetching from 0x0 */
 633         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 634         armv4_5->core_cache->reg_list[15].dirty = 1;
 635         armv4_5->core_cache->reg_list[15].valid = 1;
 636
 637         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 638         armv4_5->core_state = ARMV4_5_STATE_ARM;
 639
 640         arm920t_disable_mmu_caches(target, 1, 1, 1);
 641         arm920t->armv4_5_mmu.mmu_enabled = 0;
 642         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 643         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 644
 645         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 646         {
 647                 return retval;
 648         }
 649
 650         return ERROR_OK;
 651 }
 652
 653 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 654 {
 655         arm9tdmi_init_target(cmd_ctx, target);
 656
 657         return ERROR_OK;
 658 }
 659
 660 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
 661 {
 662         arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 663         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 664
 665         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 666          */
 667         arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 668
 669         arm9tdmi->arch_info = arm920t;
 670         arm920t->common_magic = ARM920T_COMMON_MAGIC;
 671
 672         arm7_9->post_debug_entry = arm920t_post_debug_entry;
 673         arm7_9->pre_restore_context = arm920t_pre_restore_context;
 674
 675         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 676         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
 677         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 678         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 679         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 680         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 681         arm920t->armv4_5_mmu.has_tiny_pages = 1;
 682         arm920t->armv4_5_mmu.mmu_enabled = 0;
 683
 684         /* disabling linefills leads to lockups, so keep them enabled for now
 685          * this doesn't affect correctness, but might affect timing issues, if
 686          * important data is evicted from the cache during the debug session
 687          * */
 688         arm920t->preserve_cache = 0;
 689
 690         /* override hw single-step capability from ARM9TDMI */
 691         arm7_9->has_single_step = 1;
 692
 693         return ERROR_OK;
 694 }
 695
 696 int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
 697 {
 698         arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
 699
 700         arm920t_init_arch_info(target, arm920t, target->tap);
 701
 702         return ERROR_OK;
 703 }
 704
 705 int arm920t_register_commands(struct command_context_s *cmd_ctx)
 706 {
 707         int retval;
 708         command_t *arm920t_cmd;
 709
 710
 711         retval = arm9tdmi_register_commands(cmd_ctx);
 712
 713         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
 714
 715         register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 716         register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
 717         register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 718
 719         register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
 720         register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
 721
 722         return retval;
 723 }
 724
 725 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 726 {
 727         int retval = ERROR_OK;
 728         target_t *target = get_current_target(cmd_ctx);
 729         armv4_5_common_t *armv4_5;
 730         arm7_9_common_t *arm7_9;
 731         arm9tdmi_common_t *arm9tdmi;
 732         arm920t_common_t *arm920t;
 733         arm_jtag_t *jtag_info;
 734         uint32_t cp15c15;
 735         uint32_t cp15_ctrl, cp15_ctrl_saved;
 736         uint32_t regs[16];
 737         uint32_t *regs_p[16];
 738         uint32_t C15_C_D_Ind, C15_C_I_Ind;
 739         int i;
 740         FILE *output;
 741         arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
 742         int segment, index;
 743
 744         if (argc != 1)
 745         {
 746                 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
 747                 return ERROR_OK;
 748         }
 749
 750         if ((output = fopen(args[0], "w")) == NULL)
 751         {
 752                 LOG_DEBUG("error opening cache content file");
 753                 return ERROR_OK;
 754         }
 755
 756         for (i = 0; i < 16; i++)
 757                 regs_p[i] = &regs[i];
 758
 759         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 760         {
 761                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 762                 return ERROR_OK;
 763         }
 764
 765         jtag_info = &arm7_9->jtag_info;
 766
 767         /* disable MMU and Caches */
 768         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
 769         if ((retval = jtag_execute_queue()) != ERROR_OK)
 770         {
 771                 return retval;
 772         }
 773         cp15_ctrl_saved = cp15_ctrl;
 774         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 775         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 776
 777         /* read CP15 test state register */
 778         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
 779         jtag_execute_queue();
 780
 781         /* read DCache content */
 782         fprintf(output, "DCache:\n");
 783
 784         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 785         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 786         {
 787                 fprintf(output, "\nsegment: %i\n----------", segment);
 788
 789                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 790                 regs[0] = 0x0 | (segment << 5);
 791                 arm9tdmi_write_core_regs(target, 0x1, regs);
 792
 793                 /* set interpret mode */
 794                 cp15c15 |= 0x1;
 795                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 796
 797                 /* D CAM Read, loads current victim into C15.C.D.Ind */
 798                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 799
 800                 /* read current victim */
 801                 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
 802
 803                 /* clear interpret mode */
 804                 cp15c15 &= ~0x1;
 805                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 806
 807                 for (index = 0; index < 64; index++)
 808                 {
 809                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 810                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 811                         arm9tdmi_write_core_regs(target, 0x1, regs);
 812
 813                         /* set interpret mode */
 814                         cp15c15 |= 0x1;
 815                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 816
 817                         /* Write DCache victim */
 818                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 819
 820                         /* Read D RAM */
 821                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 822
 823                         /* Read D CAM */
 824                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
 825
 826                         /* clear interpret mode */
 827                         cp15c15 &= ~0x1;
 828                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 829
 830                         /* read D RAM and CAM content */
 831                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 832                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 833                         {
 834                                 return retval;
 835                         }
 836
 837                         d_cache[segment][index].cam = regs[9];
 838
 839                         /* mask LFSR[6] */
 840                         regs[9] &= 0xfffffffe;
 841                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 842
 843                         for (i = 1; i < 9; i++)
 844                         {
 845                                  d_cache[segment][index].data[i] = regs[i];
 846                                  fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
 847                         }
 848
 849                 }
 850
 851                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 852                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 853                 arm9tdmi_write_core_regs(target, 0x1, regs);
 854
 855                 /* set interpret mode */
 856                 cp15c15 |= 0x1;
 857                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 858
 859                 /* Write DCache victim */
 860                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 861
 862                 /* clear interpret mode */
 863                 cp15c15 &= ~0x1;
 864                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 865         }
 866
 867         /* read ICache content */
 868         fprintf(output, "ICache:\n");
 869
 870         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 871         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 872         {
 873                 fprintf(output, "segment: %i\n----------", segment);
 874
 875                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 876                 regs[0] = 0x0 | (segment << 5);
 877                 arm9tdmi_write_core_regs(target, 0x1, regs);
 878
 879                 /* set interpret mode */
 880                 cp15c15 |= 0x1;
 881                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 882
 883                 /* I CAM Read, loads current victim into C15.C.I.Ind */
 884                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 885
 886                 /* read current victim */
 887                 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
 888
 889                 /* clear interpret mode */
 890                 cp15c15 &= ~0x1;
 891                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 892
 893                 for (index = 0; index < 64; index++)
 894                 {
 895                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 896                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 897                         arm9tdmi_write_core_regs(target, 0x1, regs);
 898
 899                         /* set interpret mode */
 900                         cp15c15 |= 0x1;
 901                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 902
 903                         /* Write ICache victim */
 904                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 905
 906                         /* Read I RAM */
 907                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 908
 909                         /* Read I CAM */
 910                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
 911
 912                         /* clear interpret mode */
 913                         cp15c15 &= ~0x1;
 914                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 915
 916                         /* read I RAM and CAM content */
 917                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 918                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 919                         {
 920                                 return retval;
 921                         }
 922
 923                         i_cache[segment][index].cam = regs[9];
 924
 925                         /* mask LFSR[6] */
 926                         regs[9] &= 0xfffffffe;
 927                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 928
 929                         for (i = 1; i < 9; i++)
 930                         {
 931                                  i_cache[segment][index].data[i] = regs[i];
 932                                  fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
 933                         }
 934                 }
 935
 936                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 937                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 938                 arm9tdmi_write_core_regs(target, 0x1, regs);
 939
 940                 /* set interpret mode */
 941                 cp15c15 |= 0x1;
 942                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 943
 944                 /* Write ICache victim */
 945                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 946
 947                 /* clear interpret mode */
 948                 cp15c15 &= ~0x1;
 949                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 950         }
 951
 952         /* restore CP15 MMU and Cache settings */
 953         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
 954
 955         command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
 956
 957         fclose(output);
 958
 959         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 960                 return ERROR_FAIL;
 961
 962         /* mark registers dirty. */
 963         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
 964         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
 965         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
 966         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
 967         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
 968         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
 969         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
 970         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
 971         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
 972         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
 973
 974         return ERROR_OK;
 975 }
 976
 977 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 978 {
 979         int retval = ERROR_OK;
 980         target_t *target = get_current_target(cmd_ctx);
 981         armv4_5_common_t *armv4_5;
 982         arm7_9_common_t *arm7_9;
 983         arm9tdmi_common_t *arm9tdmi;
 984         arm920t_common_t *arm920t;
 985         arm_jtag_t *jtag_info;
 986         uint32_t cp15c15;
 987         uint32_t cp15_ctrl, cp15_ctrl_saved;
 988         uint32_t regs[16];
 989         uint32_t *regs_p[16];
 990         int i;
 991         FILE *output;
 992         uint32_t Dlockdown, Ilockdown;
 993         arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
 994         int victim;
 995
 996         if (argc != 1)
 997         {
 998                 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
 999                 return ERROR_OK;
1000         }
1001
1002         if ((output = fopen(args[0], "w")) == NULL)
1003         {
1004                 LOG_DEBUG("error opening mmu content file");
1005                 return ERROR_OK;
1006         }
1007
1008         for (i = 0; i < 16; i++)
1009                 regs_p[i] = &regs[i];
1010
1011         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1012         {
1013                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1014                 return ERROR_OK;
1015         }
1016
1017         jtag_info = &arm7_9->jtag_info;
1018
1019         /* disable MMU and Caches */
1020         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1021         if ((retval = jtag_execute_queue()) != ERROR_OK)
1022         {
1023                 return retval;
1024         }
1025         cp15_ctrl_saved = cp15_ctrl;
1026         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1027         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1028
1029         /* read CP15 test state register */
1030         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1031         if ((retval = jtag_execute_queue()) != ERROR_OK)
1032         {
1033                 return retval;
1034         }
1035
1036         /* prepare reading D TLB content
1037          * */
1038
1039         /* set interpret mode */
1040         cp15c15 |= 0x1;
1041         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1042
1043         /* Read D TLB lockdown */
1044         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1045
1046         /* clear interpret mode */
1047         cp15c15 &= ~0x1;
1048         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1049
1050         /* read D TLB lockdown stored to r1 */
1051         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1052         if ((retval = jtag_execute_queue()) != ERROR_OK)
1053         {
1054                 return retval;
1055         }
1056         Dlockdown = regs[1];
1057
1058         for (victim = 0; victim < 64; victim += 8)
1059         {
1060                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1061                  * base remains unchanged, victim goes through entries 0 to 63 */
1062                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1063                 arm9tdmi_write_core_regs(target, 0x2, regs);
1064
1065                 /* set interpret mode */
1066                 cp15c15 |= 0x1;
1067                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1068
1069                 /* Write D TLB lockdown */
1070                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1071
1072                 /* Read D TLB CAM */
1073                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1074
1075                 /* clear interpret mode */
1076                 cp15c15 &= ~0x1;
1077                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1078
1079                 /* read D TLB CAM content stored to r2-r9 */
1080                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1081                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1082                 {
1083                         return retval;
1084                 }
1085
1086                 for (i = 0; i < 8; i++)
1087                         d_tlb[victim + i].cam = regs[i + 2];
1088         }
1089
1090         for (victim = 0; victim < 64; victim++)
1091         {
1092                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1093                  * base remains unchanged, victim goes through entries 0 to 63 */
1094                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1095                 arm9tdmi_write_core_regs(target, 0x2, regs);
1096
1097                 /* set interpret mode */
1098                 cp15c15 |= 0x1;
1099                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1100
1101                 /* Write D TLB lockdown */
1102                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1103
1104                 /* Read D TLB RAM1 */
1105                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1106
1107                 /* Read D TLB RAM2 */
1108                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1109
1110                 /* clear interpret mode */
1111                 cp15c15 &= ~0x1;
1112                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1113
1114                 /* read D TLB RAM content stored to r2 and r3 */
1115                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1116                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1117                 {
1118                         return retval;
1119                 }
1120
1121                 d_tlb[victim].ram1 = regs[2];
1122                 d_tlb[victim].ram2 = regs[3];
1123         }
1124
1125         /* restore D TLB lockdown */
1126         regs[1] = Dlockdown;
1127         arm9tdmi_write_core_regs(target, 0x2, regs);
1128
1129         /* Write D TLB lockdown */
1130         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1131
1132         /* prepare reading I TLB content
1133          * */
1134
1135         /* set interpret mode */
1136         cp15c15 |= 0x1;
1137         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1138
1139         /* Read I TLB lockdown */
1140         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1141
1142         /* clear interpret mode */
1143         cp15c15 &= ~0x1;
1144         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1145
1146         /* read I TLB lockdown stored to r1 */
1147         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1148         if ((retval = jtag_execute_queue()) != ERROR_OK)
1149         {
1150                 return retval;
1151         }
1152         Ilockdown = regs[1];
1153
1154         for (victim = 0; victim < 64; victim += 8)
1155         {
1156                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1157                  * base remains unchanged, victim goes through entries 0 to 63 */
1158                 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1159                 arm9tdmi_write_core_regs(target, 0x2, regs);
1160
1161                 /* set interpret mode */
1162                 cp15c15 |= 0x1;
1163                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1164
1165                 /* Write I TLB lockdown */
1166                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1167
1168                 /* Read I TLB CAM */
1169                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1170
1171                 /* clear interpret mode */
1172                 cp15c15 &= ~0x1;
1173                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1174
1175                 /* read I TLB CAM content stored to r2-r9 */
1176                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1177                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1178                 {
1179                         return retval;
1180                 }
1181
1182                 for (i = 0; i < 8; i++)
1183                         i_tlb[i + victim].cam = regs[i + 2];
1184         }
1185
1186         for (victim = 0; victim < 64; victim++)
1187         {
1188                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1189                  * base remains unchanged, victim goes through entries 0 to 63 */
1190                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1191                 arm9tdmi_write_core_regs(target, 0x2, regs);
1192
1193                 /* set interpret mode */
1194                 cp15c15 |= 0x1;
1195                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1196
1197                 /* Write I TLB lockdown */
1198                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1199
1200                 /* Read I TLB RAM1 */
1201                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1202
1203                 /* Read I TLB RAM2 */
1204                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1205
1206                 /* clear interpret mode */
1207                 cp15c15 &= ~0x1;
1208                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1209
1210                 /* read I TLB RAM content stored to r2 and r3 */
1211                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1212                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1213                 {
1214                         return retval;
1215                 }
1216
1217                 i_tlb[victim].ram1 = regs[2];
1218                 i_tlb[victim].ram2 = regs[3];
1219         }
1220
1221         /* restore I TLB lockdown */
1222         regs[1] = Ilockdown;
1223         arm9tdmi_write_core_regs(target, 0x2, regs);
1224
1225         /* Write I TLB lockdown */
1226         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1227
1228         /* restore CP15 MMU and Cache settings */
1229         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1230
1231         /* output data to file */
1232         fprintf(output, "D TLB content:\n");
1233         for (i = 0; i < 64; i++)
1234         {
1235                 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1236         }
1237
1238         fprintf(output, "\n\nI TLB content:\n");
1239         for (i = 0; i < 64; i++)
1240         {
1241                 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1242         }
1243
1244         command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1245
1246         fclose(output);
1247
1248         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1249                 return ERROR_FAIL;
1250
1251         /* mark registers dirty */
1252         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1253         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1254         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1255         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1256         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1257         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1258         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1259         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1260         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1261         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1262
1263         return ERROR_OK;
1264 }
1265 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1266 {
1267         int retval;
1268         target_t *target = get_current_target(cmd_ctx);
1269         armv4_5_common_t *armv4_5;
1270         arm7_9_common_t *arm7_9;
1271         arm9tdmi_common_t *arm9tdmi;
1272         arm920t_common_t *arm920t;
1273         arm_jtag_t *jtag_info;
1274
1275         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1276         {
1277                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1278                 return ERROR_OK;
1279         }
1280
1281         jtag_info = &arm7_9->jtag_info;
1282
1283         if (target->state != TARGET_HALTED)
1284         {
1285                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1286                 return ERROR_OK;
1287         }
1288
1289         /* one or more argument, access a single register (write if second argument is given */
1290         if (argc >= 1)
1291         {
1292                 int address = strtoul(args[0], NULL, 0);
1293
1294                 if (argc == 1)
1295                 {
1296                         uint32_t value;
1297                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1298                         {
1299                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1300                                 return ERROR_OK;
1301                         }
1302                         if ((retval = jtag_execute_queue()) != ERROR_OK)
1303                         {
1304                                 return retval;
1305                         }
1306
1307                         command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
1308                 }
1309                 else if (argc == 2)
1310                 {
1311                         uint32_t value = strtoul(args[1], NULL, 0);
1312                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1313                         {
1314                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1315                                 return ERROR_OK;
1316                         }
1317                         command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
1318                 }
1319         }
1320
1321         return ERROR_OK;
1322 }
1323
1324 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1325 {
1326         int retval;
1327         target_t *target = get_current_target(cmd_ctx);
1328         armv4_5_common_t *armv4_5;
1329         arm7_9_common_t *arm7_9;
1330         arm9tdmi_common_t *arm9tdmi;
1331         arm920t_common_t *arm920t;
1332         arm_jtag_t *jtag_info;
1333
1334         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1335         {
1336                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1337                 return ERROR_OK;
1338         }
1339
1340         jtag_info = &arm7_9->jtag_info;
1341
1342         if (target->state != TARGET_HALTED)
1343         {
1344                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1345                 return ERROR_OK;
1346         }
1347
1348         /* one or more argument, access a single register (write if second argument is given */
1349         if (argc >= 1)
1350         {
1351                 uint32_t opcode = strtoul(args[0], NULL, 0);
1352
1353                 if (argc == 1)
1354                 {
1355                         uint32_t value;
1356                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1357                         {
1358                                 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1359                                 return ERROR_OK;
1360                         }
1361
1362                         command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1363                 }
1364                 else if (argc == 2)
1365                 {
1366                         uint32_t value = strtoul(args[1], NULL, 0);
1367                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1368                         {
1369                                 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1370                                 return ERROR_OK;
1371                         }
1372                         command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1373                 }
1374                 else if (argc == 3)
1375                 {
1376                         uint32_t value = strtoul(args[1], NULL, 0);
1377                         uint32_t address = strtoul(args[2], NULL, 0);
1378                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1379                         {
1380                                 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1381                                 return ERROR_OK;
1382                         }
1383                         command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1384                 }
1385         }
1386         else
1387         {
1388                 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1389         }
1390
1391         return ERROR_OK;
1392 }
1393
1394 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1395 {
1396         target_t *target = get_current_target(cmd_ctx);
1397         armv4_5_common_t *armv4_5;
1398         arm7_9_common_t *arm7_9;
1399         arm9tdmi_common_t *arm9tdmi;
1400         arm920t_common_t *arm920t;
1401
1402         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1403         {
1404                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1405                 return ERROR_OK;
1406         }
1407
1408         return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1409 }