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target: remove unused interface fn that clutters code
[openocd.git] / src / target / arm11.c
blob1e82b9389b91f08c310fea48a51e78d0c650c0b3
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
34
35
36 #if 0
37 #define _DEBUG_INSTRUCTION_EXECUTION_
38 #endif
39
40 #if 0
41 #define FNC_INFO LOG_DEBUG("-")
42 #else
43 #define FNC_INFO
44 #endif
45
46 #if 1
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #else
49 #define FNC_INFO_NOTIMPLEMENTED
50 #endif
51
52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
53
54 bool arm11_config_memwrite_burst = true;
55 bool arm11_config_memwrite_error_fatal = true;
56 uint32_t arm11_vcr = 0;
57 bool arm11_config_step_irq_enable = false;
58 bool arm11_config_hardware_step = false;
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 };
101
102 int arm11_regs_arch_type = -1;
103
104
105 enum arm11_regtype
106 {
107 ARM11_REGISTER_CORE,
108 ARM11_REGISTER_CPSR,
109
110 ARM11_REGISTER_FX,
111 ARM11_REGISTER_FPS,
112
113 ARM11_REGISTER_FIQ,
114 ARM11_REGISTER_SVC,
115 ARM11_REGISTER_ABT,
116 ARM11_REGISTER_IRQ,
117 ARM11_REGISTER_UND,
118 ARM11_REGISTER_MON,
119
120 ARM11_REGISTER_SPSR_FIQ,
121 ARM11_REGISTER_SPSR_SVC,
122 ARM11_REGISTER_SPSR_ABT,
123 ARM11_REGISTER_SPSR_IRQ,
124 ARM11_REGISTER_SPSR_UND,
125 ARM11_REGISTER_SPSR_MON,
126
127 /* debug regs */
128 ARM11_REGISTER_DSCR,
129 ARM11_REGISTER_WDTR,
130 ARM11_REGISTER_RDTR,
131 };
132
133
134 typedef struct arm11_reg_defs_s
135 {
136 char * name;
137 uint32_t num;
138 int gdb_num;
139 enum arm11_regtype type;
140 } arm11_reg_defs_t;
141
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs[] =
144 {
145 {"r0", 0, 0, ARM11_REGISTER_CORE},
146 {"r1", 1, 1, ARM11_REGISTER_CORE},
147 {"r2", 2, 2, ARM11_REGISTER_CORE},
148 {"r3", 3, 3, ARM11_REGISTER_CORE},
149 {"r4", 4, 4, ARM11_REGISTER_CORE},
150 {"r5", 5, 5, ARM11_REGISTER_CORE},
151 {"r6", 6, 6, ARM11_REGISTER_CORE},
152 {"r7", 7, 7, ARM11_REGISTER_CORE},
153 {"r8", 8, 8, ARM11_REGISTER_CORE},
154 {"r9", 9, 9, ARM11_REGISTER_CORE},
155 {"r10", 10, 10, ARM11_REGISTER_CORE},
156 {"r11", 11, 11, ARM11_REGISTER_CORE},
157 {"r12", 12, 12, ARM11_REGISTER_CORE},
158 {"sp", 13, 13, ARM11_REGISTER_CORE},
159 {"lr", 14, 14, ARM11_REGISTER_CORE},
160 {"pc", 15, 15, ARM11_REGISTER_CORE},
161
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX},
164 {"f1", 1, 17, ARM11_REGISTER_FX},
165 {"f2", 2, 18, ARM11_REGISTER_FX},
166 {"f3", 3, 19, ARM11_REGISTER_FX},
167 {"f4", 4, 20, ARM11_REGISTER_FX},
168 {"f5", 5, 21, ARM11_REGISTER_FX},
169 {"f6", 6, 22, ARM11_REGISTER_FX},
170 {"f7", 7, 23, ARM11_REGISTER_FX},
171 {"fps", 0, 24, ARM11_REGISTER_FPS},
172 #endif
173
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
175
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
185
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
189
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
193
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
197
198 {"r13_und", 13, -1, ARM11_REGISTER_UND},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
201
202 /* ARM1176 only */
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
206 #endif
207
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
212 };
213
214 enum arm11_regcache_ids
215 {
216 ARM11_RC_R0,
217 ARM11_RC_RX = ARM11_RC_R0,
218
219 ARM11_RC_R1,
220 ARM11_RC_R2,
221 ARM11_RC_R3,
222 ARM11_RC_R4,
223 ARM11_RC_R5,
224 ARM11_RC_R6,
225 ARM11_RC_R7,
226 ARM11_RC_R8,
227 ARM11_RC_R9,
228 ARM11_RC_R10,
229 ARM11_RC_R11,
230 ARM11_RC_R12,
231 ARM11_RC_R13,
232 ARM11_RC_SP = ARM11_RC_R13,
233 ARM11_RC_R14,
234 ARM11_RC_LR = ARM11_RC_R14,
235 ARM11_RC_R15,
236 ARM11_RC_PC = ARM11_RC_R15,
237
238 #if ARM11_REGCACHE_FREGS
239 ARM11_RC_F0,
240 ARM11_RC_FX = ARM11_RC_F0,
241 ARM11_RC_F1,
242 ARM11_RC_F2,
243 ARM11_RC_F3,
244 ARM11_RC_F4,
245 ARM11_RC_F5,
246 ARM11_RC_F6,
247 ARM11_RC_F7,
248 ARM11_RC_FPS,
249 #endif
250
251 ARM11_RC_CPSR,
252
253 #if ARM11_REGCACHE_MODEREGS
254 ARM11_RC_R8_FIQ,
255 ARM11_RC_R9_FIQ,
256 ARM11_RC_R10_FIQ,
257 ARM11_RC_R11_FIQ,
258 ARM11_RC_R12_FIQ,
259 ARM11_RC_R13_FIQ,
260 ARM11_RC_R14_FIQ,
261 ARM11_RC_SPSR_FIQ,
262
263 ARM11_RC_R13_SVC,
264 ARM11_RC_R14_SVC,
265 ARM11_RC_SPSR_SVC,
266
267 ARM11_RC_R13_ABT,
268 ARM11_RC_R14_ABT,
269 ARM11_RC_SPSR_ABT,
270
271 ARM11_RC_R13_IRQ,
272 ARM11_RC_R14_IRQ,
273 ARM11_RC_SPSR_IRQ,
274
275 ARM11_RC_R13_UND,
276 ARM11_RC_R14_UND,
277 ARM11_RC_SPSR_UND,
278
279 ARM11_RC_R13_MON,
280 ARM11_RC_R14_MON,
281 ARM11_RC_SPSR_MON,
282 #endif
283
284 ARM11_RC_DSCR,
285 ARM11_RC_WDTR,
286 ARM11_RC_RDTR,
287
288 ARM11_RC_MAX,
289 };
290
291 #define ARM11_GDB_REGISTER_COUNT 26
292
293 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
294
295 reg_t arm11_gdb_dummy_fp_reg =
296 {
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 };
299
300 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
301
302 reg_t arm11_gdb_dummy_fps_reg =
303 {
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
305 };
306
307
308
309 /** Check and if necessary take control of the system
310 *
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
315 */
316 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
317 {
318 FNC_INFO;
319
320 uint32_t dscr_local_tmp_copy;
321
322 if (!dscr)
323 {
324 dscr = &dscr_local_tmp_copy;
325
326 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
327 }
328
329 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
330 {
331 LOG_DEBUG("Bringing target into debug mode");
332
333 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
334 arm11_write_DSCR(arm11, *dscr);
335
336 /* add further reset initialization here */
337
338 arm11->simulate_reset_on_next_halt = true;
339
340 if (*dscr & ARM11_DSCR_CORE_HALTED)
341 {
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called.
344 * As a result we don't read the actual register states from
345 * the target.
346 */
347
348 arm11->target->state = TARGET_HALTED;
349 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
350 }
351 else
352 {
353 arm11->target->state = TARGET_RUNNING;
354 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
355 }
356
357 arm11_sc7_clear_vbw(arm11);
358 }
359
360 return ERROR_OK;
361 }
362
363
364
365 #define R(x) \
366 (arm11->reg_values[ARM11_RC_##x])
367
368 /** Save processor state.
369 *
370 * This is called when the HALT instruction has succeeded
371 * or on other occasions that stop the processor.
372 *
373 */
374 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
375 {
376 int retval;
377 FNC_INFO;
378
379 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
380 {
381 arm11->reg_list[i].valid = 1;
382 arm11->reg_list[i].dirty = 0;
383 }
384
385 /* Save DSCR */
386 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
387
388 /* Save wDTR */
389
390 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
391 {
392 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
393
394 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
395
396 scan_field_t chain5_fields[3];
397
398 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
399 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
400 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
401
402 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
403 }
404 else
405 {
406 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
407 }
408
409
410 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
411 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
412 ARM1136 seems to require this to issue ITR's as well */
413
414 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
415
416 /* this executes JTAG queue: */
417
418 arm11_write_DSCR(arm11, new_dscr);
419
420
421 /* From the spec:
422 Before executing any instruction in debug state you have to drain the write buffer.
423 This ensures that no imprecise Data Aborts can return at a later point:*/
424
425 /** \todo TODO: Test drain write buffer. */
426
427 #if 0
428 while (1)
429 {
430 /* MRC p14,0,R0,c5,c10,0 */
431 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
432
433 /* mcr 15, 0, r0, cr7, cr10, {4} */
434 arm11_run_instr_no_data1(arm11, 0xee070f9a);
435
436 uint32_t dscr = arm11_read_DSCR(arm11);
437
438 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
439
440 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
441 {
442 arm11_run_instr_no_data1(arm11, 0xe320f000);
443
444 dscr = arm11_read_DSCR(arm11);
445
446 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
447
448 break;
449 }
450 }
451 #endif
452
453 retval = arm11_run_instr_data_prepare(arm11);
454 if (retval != ERROR_OK)
455 return retval;
456
457 /* save r0 - r14 */
458
459 /** \todo TODO: handle other mode registers */
460
461 for (size_t i = 0; i < 15; i++)
462 {
463 /* MCR p14,0,R?,c0,c5,0 */
464 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
465 if (retval != ERROR_OK)
466 return retval;
467 }
468
469 /* save rDTR */
470
471 /* check rDTRfull in DSCR */
472
473 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
474 {
475 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
476 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
477 if (retval != ERROR_OK)
478 return retval;
479 }
480 else
481 {
482 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
483 }
484
485 /* save CPSR */
486
487 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
488 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
489 if (retval != ERROR_OK)
490 return retval;
491
492 /* save PC */
493
494 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
495 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
496 if (retval != ERROR_OK)
497 return retval;
498
499 /* adjust PC depending on ARM state */
500
501 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
502 {
503 arm11->reg_values[ARM11_RC_PC] -= 0;
504 }
505 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
506 {
507 arm11->reg_values[ARM11_RC_PC] -= 4;
508 }
509 else /* ARM state */
510 {
511 arm11->reg_values[ARM11_RC_PC] -= 8;
512 }
513
514 if (arm11->simulate_reset_on_next_halt)
515 {
516 arm11->simulate_reset_on_next_halt = false;
517
518 LOG_DEBUG("Reset c1 Control Register");
519
520 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
521
522 /* MCR p15,0,R0,c1,c0,0 */
523 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
524 if (retval != ERROR_OK)
525 return retval;
526
527 }
528
529 retval = arm11_run_instr_data_finish(arm11);
530 if (retval != ERROR_OK)
531 return retval;
532
533 arm11_dump_reg_changes(arm11);
534
535 return ERROR_OK;
536 }
537
538 void arm11_dump_reg_changes(arm11_common_t * arm11)
539 {
540
541 if (!(debug_level >= LOG_LVL_DEBUG))
542 {
543 return;
544 }
545
546 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
547 {
548 if (!arm11->reg_list[i].valid)
549 {
550 if (arm11->reg_history[i].valid)
551 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
552 }
553 else
554 {
555 if (arm11->reg_history[i].valid)
556 {
557 if (arm11->reg_history[i].value != arm11->reg_values[i])
558 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
559 }
560 else
561 {
562 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
563 }
564 }
565 }
566 }
567
568 /** Restore processor state
569 *
570 * This is called in preparation for the RESTART function.
571 *
572 */
573 int arm11_leave_debug_state(arm11_common_t * arm11)
574 {
575 FNC_INFO;
576 int retval;
577
578 retval = arm11_run_instr_data_prepare(arm11);
579 if (retval != ERROR_OK)
580 return retval;
581
582 /** \todo TODO: handle other mode registers */
583
584 /* restore R1 - R14 */
585
586 for (size_t i = 1; i < 15; i++)
587 {
588 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
589 continue;
590
591 /* MRC p14,0,r?,c0,c5,0 */
592 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
593
594 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
595 }
596
597 retval = arm11_run_instr_data_finish(arm11);
598 if (retval != ERROR_OK)
599 return retval;
600
601 /* spec says clear wDTR and rDTR; we assume they are clear as
602 otherwise our programming would be sloppy */
603 {
604 uint32_t DSCR;
605
606 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
607
608 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
609 {
610 /*
611 The wDTR/rDTR two registers that are used to send/receive data to/from
612 the core in tandem with corresponding instruction codes that are
613 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
614 registers hold data that was written by one side (CPU or JTAG) and not
615 read out by the other side.
616 */
617 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
618 return ERROR_FAIL;
619 }
620 }
621
622 retval = arm11_run_instr_data_prepare(arm11);
623 if (retval != ERROR_OK)
624 return retval;
625
626 /* restore original wDTR */
627
628 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
629 {
630 /* MCR p14,0,R0,c0,c5,0 */
631 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
632 if (retval != ERROR_OK)
633 return retval;
634 }
635
636 /* restore CPSR */
637
638 /* MSR CPSR,R0*/
639 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
640 if (retval != ERROR_OK)
641 return retval;
642
643
644 /* restore PC */
645
646 /* MOV PC,R0 */
647 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
648 if (retval != ERROR_OK)
649 return retval;
650
651
652 /* restore R0 */
653
654 /* MRC p14,0,r0,c0,c5,0 */
655 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
656
657 retval = arm11_run_instr_data_finish(arm11);
658 if (retval != ERROR_OK)
659 return retval;
660
661 /* restore DSCR */
662
663 arm11_write_DSCR(arm11, R(DSCR));
664
665 /* restore rDTR */
666
667 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
668 {
669 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
670
671 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
672
673 scan_field_t chain5_fields[3];
674
675 uint8_t Ready = 0; /* ignored */
676 uint8_t Valid = 0; /* ignored */
677
678 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
679 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
680 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
681
682 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
683 }
684
685 arm11_record_register_history(arm11);
686
687 return ERROR_OK;
688 }
689
690 void arm11_record_register_history(arm11_common_t * arm11)
691 {
692 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
693 {
694 arm11->reg_history[i].value = arm11->reg_values[i];
695 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
696
697 arm11->reg_list[i].valid = 0;
698 arm11->reg_list[i].dirty = 0;
699 }
700 }
701
702
703 /* poll current target status */
704 int arm11_poll(struct target_s *target)
705 {
706 FNC_INFO;
707 int retval;
708
709 arm11_common_t * arm11 = target->arch_info;
710
711 uint32_t dscr;
712
713 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
714
715 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
716
717 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
718
719 if (dscr & ARM11_DSCR_CORE_HALTED)
720 {
721 if (target->state != TARGET_HALTED)
722 {
723 enum target_state old_state = target->state;
724
725 LOG_DEBUG("enter TARGET_HALTED");
726 target->state = TARGET_HALTED;
727 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
728 retval = arm11_on_enter_debug_state(arm11);
729 if (retval != ERROR_OK)
730 return retval;
731
732 target_call_event_callbacks(target,
733 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
734 }
735 }
736 else
737 {
738 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
739 {
740 LOG_DEBUG("enter TARGET_RUNNING");
741 target->state = TARGET_RUNNING;
742 target->debug_reason = DBG_REASON_NOTHALTED;
743 }
744 }
745
746 return ERROR_OK;
747 }
748 /* architecture specific status reply */
749 int arm11_arch_state(struct target_s *target)
750 {
751 arm11_common_t * arm11 = target->arch_info;
752
753 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
754 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
755 R(CPSR),
756 R(PC));
757
758 return ERROR_OK;
759 }
760
761 /* target request support */
762 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
763 {
764 FNC_INFO_NOTIMPLEMENTED;
765
766 return ERROR_OK;
767 }
768
769 /* target execution control */
770 int arm11_halt(struct target_s *target)
771 {
772 FNC_INFO;
773
774 arm11_common_t * arm11 = target->arch_info;
775
776 LOG_DEBUG("target->state: %s",
777 target_state_name(target));
778
779 if (target->state == TARGET_UNKNOWN)
780 {
781 arm11->simulate_reset_on_next_halt = true;
782 }
783
784 if (target->state == TARGET_HALTED)
785 {
786 LOG_DEBUG("target was already halted");
787 return ERROR_OK;
788 }
789
790 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
791
792 CHECK_RETVAL(jtag_execute_queue());
793
794 uint32_t dscr;
795
796 int i = 0;
797 while (1)
798 {
799 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
800
801 if (dscr & ARM11_DSCR_CORE_HALTED)
802 break;
803
804
805 long long then = 0;
806 if (i == 1000)
807 {
808 then = timeval_ms();
809 }
810 if (i >= 1000)
811 {
812 if ((timeval_ms()-then) > 1000)
813 {
814 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
815 return ERROR_FAIL;
816 }
817 }
818 i++;
819 }
820
821 arm11_on_enter_debug_state(arm11);
822
823 enum target_state old_state = target->state;
824
825 target->state = TARGET_HALTED;
826 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
827
828 CHECK_RETVAL(
829 target_call_event_callbacks(target,
830 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
831
832 return ERROR_OK;
833 }
834
835 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
836 {
837 FNC_INFO;
838
839 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
840 // current, address, handle_breakpoints, debug_execution);
841
842 arm11_common_t * arm11 = target->arch_info;
843
844 LOG_DEBUG("target->state: %s",
845 target_state_name(target));
846
847
848 if (target->state != TARGET_HALTED)
849 {
850 LOG_ERROR("Target not halted");
851 return ERROR_TARGET_NOT_HALTED;
852 }
853
854 if (!current)
855 R(PC) = address;
856
857 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
858
859 /* clear breakpoints/watchpoints and VCR*/
860 arm11_sc7_clear_vbw(arm11);
861
862 /* Set up breakpoints */
863 if (!debug_execution)
864 {
865 /* check if one matches PC and step over it if necessary */
866
867 breakpoint_t * bp;
868
869 for (bp = target->breakpoints; bp; bp = bp->next)
870 {
871 if (bp->address == R(PC))
872 {
873 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
874 arm11_step(target, 1, 0, 0);
875 break;
876 }
877 }
878
879 /* set all breakpoints */
880
881 size_t brp_num = 0;
882
883 for (bp = target->breakpoints; bp; bp = bp->next)
884 {
885 arm11_sc7_action_t brp[2];
886
887 brp[0].write = 1;
888 brp[0].address = ARM11_SC7_BVR0 + brp_num;
889 brp[0].value = bp->address;
890 brp[1].write = 1;
891 brp[1].address = ARM11_SC7_BCR0 + brp_num;
892 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
893
894 arm11_sc7_run(arm11, brp, asizeof(brp));
895
896 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
897
898 brp_num++;
899 }
900
901 arm11_sc7_set_vcr(arm11, arm11_vcr);
902 }
903
904 arm11_leave_debug_state(arm11);
905
906 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
907
908 CHECK_RETVAL(jtag_execute_queue());
909
910 int i = 0;
911 while (1)
912 {
913 uint32_t dscr;
914
915 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
916
917 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
918
919 if (dscr & ARM11_DSCR_CORE_RESTARTED)
920 break;
921
922
923 long long then = 0;
924 if (i == 1000)
925 {
926 then = timeval_ms();
927 }
928 if (i >= 1000)
929 {
930 if ((timeval_ms()-then) > 1000)
931 {
932 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
933 return ERROR_FAIL;
934 }
935 }
936 i++;
937 }
938
939 if (!debug_execution)
940 {
941 target->state = TARGET_RUNNING;
942 target->debug_reason = DBG_REASON_NOTHALTED;
943
944 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
945 }
946 else
947 {
948 target->state = TARGET_DEBUG_RUNNING;
949 target->debug_reason = DBG_REASON_NOTHALTED;
950
951 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
952 }
953
954 return ERROR_OK;
955 }
956
957
958 static int armv4_5_to_arm11(int reg)
959 {
960 if (reg < 16)
961 return reg;
962 switch (reg)
963 {
964 case ARMV4_5_CPSR:
965 return ARM11_RC_CPSR;
966 case 16:
967 /* FIX!!! handle thumb better! */
968 return ARM11_RC_CPSR;
969 default:
970 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
971 exit(-1);
972 }
973 }
974
975
976 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
977 {
978 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
979
980 reg=armv4_5_to_arm11(reg);
981
982 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
983 }
984
985 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
986 {
987 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
988
989 reg=armv4_5_to_arm11(reg);
990
991 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
992 }
993
994 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
995 {
996 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
997
998 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
999 }
1000
1001 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
1002 {
1003 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1004
1005 /* FIX!!!! we should implement thumb for arm11 */
1006 return ARMV4_5_STATE_ARM;
1007 }
1008
1009 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
1010 {
1011 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1012
1013 /* FIX!!!! we should implement thumb for arm11 */
1014 LOG_ERROR("Not implemetned!");
1015 }
1016
1017
1018 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1019 {
1020 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1021
1022 /* FIX!!!! we should implement something that returns the current mode here!!! */
1023 return ARMV4_5_MODE_USR;
1024 }
1025
1026 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1027 {
1028 struct arm_sim_interface sim;
1029
1030 sim.user_data=target->arch_info;
1031 sim.get_reg=&arm11_sim_get_reg;
1032 sim.set_reg=&arm11_sim_set_reg;
1033 sim.get_reg_mode=&arm11_sim_get_reg;
1034 sim.set_reg_mode=&arm11_sim_set_reg;
1035 sim.get_cpsr=&arm11_sim_get_cpsr;
1036 sim.get_mode=&arm11_sim_get_mode;
1037 sim.get_state=&arm11_sim_get_state;
1038 sim.set_state=&arm11_sim_set_state;
1039
1040 return arm_simulate_step_core(target, dry_run_pc, &sim);
1041
1042 }
1043
1044 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1045 {
1046 FNC_INFO;
1047
1048 LOG_DEBUG("target->state: %s",
1049 target_state_name(target));
1050
1051 if (target->state != TARGET_HALTED)
1052 {
1053 LOG_WARNING("target was not halted");
1054 return ERROR_TARGET_NOT_HALTED;
1055 }
1056
1057 arm11_common_t * arm11 = target->arch_info;
1058
1059 if (!current)
1060 R(PC) = address;
1061
1062 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1063
1064
1065 /** \todo TODO: Thumb not supported here */
1066
1067 uint32_t next_instruction;
1068
1069 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1070
1071 /* skip over BKPT */
1072 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1073 {
1074 R(PC) += 4;
1075 arm11->reg_list[ARM11_RC_PC].valid = 1;
1076 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1077 LOG_DEBUG("Skipping BKPT");
1078 }
1079 /* skip over Wait for interrupt / Standby */
1080 /* mcr 15, 0, r?, cr7, cr0, {4} */
1081 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1082 {
1083 R(PC) += 4;
1084 arm11->reg_list[ARM11_RC_PC].valid = 1;
1085 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1086 LOG_DEBUG("Skipping WFI");
1087 }
1088 /* ignore B to self */
1089 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1090 {
1091 LOG_DEBUG("Not stepping jump to self");
1092 }
1093 else
1094 {
1095 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1096 * with this. */
1097
1098 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1099 * the VCR might be something worth looking into. */
1100
1101
1102 /* Set up breakpoint for stepping */
1103
1104 arm11_sc7_action_t brp[2];
1105
1106 brp[0].write = 1;
1107 brp[0].address = ARM11_SC7_BVR0;
1108 brp[1].write = 1;
1109 brp[1].address = ARM11_SC7_BCR0;
1110
1111 if (arm11_config_hardware_step)
1112 {
1113 /* hardware single stepping be used if possible or is it better to
1114 * always use the same code path? Hardware single stepping is not supported
1115 * on all hardware
1116 */
1117 brp[0].value = R(PC);
1118 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1119 } else
1120 {
1121 /* sets a breakpoint on the next PC(calculated by simulation),
1122 */
1123 uint32_t next_pc;
1124 int retval;
1125 retval = arm11_simulate_step(target, &next_pc);
1126 if (retval != ERROR_OK)
1127 return retval;
1128
1129 brp[0].value = next_pc;
1130 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1131 }
1132
1133 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1134
1135 /* resume */
1136
1137
1138 if (arm11_config_step_irq_enable)
1139 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1140 else
1141 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1142
1143
1144 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1145
1146 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1147
1148 CHECK_RETVAL(jtag_execute_queue());
1149
1150 /* wait for halt */
1151 int i = 0;
1152 while (1)
1153 {
1154 uint32_t dscr;
1155
1156 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1157
1158 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1159
1160 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1161 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1162 break;
1163
1164 long long then = 0;
1165 if (i == 1000)
1166 {
1167 then = timeval_ms();
1168 }
1169 if (i >= 1000)
1170 {
1171 if ((timeval_ms()-then) > 1000)
1172 {
1173 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1174 return ERROR_FAIL;
1175 }
1176 }
1177 i++;
1178 }
1179
1180 /* clear breakpoint */
1181 arm11_sc7_clear_vbw(arm11);
1182
1183 /* save state */
1184 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1185
1186 /* restore default state */
1187 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1188
1189 }
1190
1191 // target->state = TARGET_HALTED;
1192 target->debug_reason = DBG_REASON_SINGLESTEP;
1193
1194 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1195
1196 return ERROR_OK;
1197 }
1198
1199 int arm11_assert_reset(target_t *target)
1200 {
1201 FNC_INFO;
1202 int retval;
1203
1204 arm11_common_t * arm11 = target->arch_info;
1205 retval = arm11_check_init(arm11, NULL);
1206 if (retval != ERROR_OK)
1207 return retval;
1208
1209 target->state = TARGET_UNKNOWN;
1210
1211 /* we would very much like to reset into the halted, state,
1212 * but resetting and halting is second best... */
1213 if (target->reset_halt)
1214 {
1215 CHECK_RETVAL(target_halt(target));
1216 }
1217
1218
1219 /* srst is funny. We can not do *anything* else while it's asserted
1220 * and it has unkonwn side effects. Make sure no other code runs
1221 * meanwhile.
1222 *
1223 * Code below assumes srst:
1224 *
1225 * - Causes power-on-reset (but of what parts of the system?). Bug
1226 * in arm11?
1227 *
1228 * - Messes us TAP state without asserting trst.
1229 *
1230 * - There is another bug in the arm11 core. When you generate an access to
1231 * external logic (for example ddr controller via AHB bus) and that block
1232 * is not configured (perhaps it is still held in reset), that transaction
1233 * will never complete. This will hang arm11 core but it will also hang
1234 * JTAG controller. Nothing, short of srst assertion will bring it out of
1235 * this.
1236 *
1237 * Mysteries:
1238 *
1239 * - What should the PC be after an srst reset when starting in the halted
1240 * state?
1241 */
1242
1243 jtag_add_reset(0, 1);
1244 jtag_add_reset(0, 0);
1245
1246 /* How long do we have to wait? */
1247 jtag_add_sleep(5000);
1248
1249 /* un-mess up TAP state */
1250 jtag_add_tlr();
1251
1252 retval = jtag_execute_queue();
1253 if (retval != ERROR_OK)
1254 {
1255 return retval;
1256 }
1257
1258 return ERROR_OK;
1259 }
1260
1261 int arm11_deassert_reset(target_t *target)
1262 {
1263 return ERROR_OK;
1264 }
1265
1266 int arm11_soft_reset_halt(struct target_s *target)
1267 {
1268 FNC_INFO_NOTIMPLEMENTED;
1269
1270 return ERROR_OK;
1271 }
1272
1273 /* target register access for gdb */
1274 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1275 {
1276 FNC_INFO;
1277
1278 arm11_common_t * arm11 = target->arch_info;
1279
1280 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1281 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1282
1283 for (size_t i = 16; i < 24; i++)
1284 {
1285 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1286 }
1287
1288 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1289
1290 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1291 {
1292 if (arm11_reg_defs[i].gdb_num == -1)
1293 continue;
1294
1295 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1296 }
1297
1298 return ERROR_OK;
1299 }
1300
1301 /* target memory access
1302 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1303 * count: number of items of <size>
1304 *
1305 * arm11_config_memrw_no_increment - in the future we may want to be able
1306 * to read/write a range of data to a "port". a "port" is an action on
1307 * read memory address for some peripheral.
1308 */
1309 int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1310 bool arm11_config_memrw_no_increment)
1311 {
1312 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1313 int retval;
1314
1315 FNC_INFO;
1316
1317 if (target->state != TARGET_HALTED)
1318 {
1319 LOG_WARNING("target was not halted");
1320 return ERROR_TARGET_NOT_HALTED;
1321 }
1322
1323 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1324
1325 arm11_common_t * arm11 = target->arch_info;
1326
1327 retval = arm11_run_instr_data_prepare(arm11);
1328 if (retval != ERROR_OK)
1329 return retval;
1330
1331 /* MRC p14,0,r0,c0,c5,0 */
1332 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1333 if (retval != ERROR_OK)
1334 return retval;
1335
1336 switch (size)
1337 {
1338 case 1:
1339 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1340 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1341
1342 for (size_t i = 0; i < count; i++)
1343 {
1344 /* ldrb r1, [r0], #1 */
1345 /* ldrb r1, [r0] */
1346 arm11_run_instr_no_data1(arm11,
1347 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1348
1349 uint32_t res;
1350 /* MCR p14,0,R1,c0,c5,0 */
1351 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1352
1353 *buffer++ = res;
1354 }
1355
1356 break;
1357
1358 case 2:
1359 {
1360 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1361
1362 for (size_t i = 0; i < count; i++)
1363 {
1364 /* ldrh r1, [r0], #2 */
1365 arm11_run_instr_no_data1(arm11,
1366 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1367
1368 uint32_t res;
1369
1370 /* MCR p14,0,R1,c0,c5,0 */
1371 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1372
1373 uint16_t svalue = res;
1374 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1375 }
1376
1377 break;
1378 }
1379
1380 case 4:
1381 {
1382 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1383 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1384 uint32_t *words = (uint32_t *)buffer;
1385
1386 /* LDC p14,c5,[R0],#4 */
1387 /* LDC p14,c5,[R0] */
1388 arm11_run_instr_data_from_core(arm11, instr, words, count);
1389 break;
1390 }
1391 }
1392
1393 return arm11_run_instr_data_finish(arm11);
1394 }
1395
1396 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1397 {
1398 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1399 }
1400
1401 /*
1402 * arm11_config_memrw_no_increment - in the future we may want to be able
1403 * to read/write a range of data to a "port". a "port" is an action on
1404 * read memory address for some peripheral.
1405 */
1406 int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1407 bool arm11_config_memrw_no_increment)
1408 {
1409 int retval;
1410 FNC_INFO;
1411
1412 if (target->state != TARGET_HALTED)
1413 {
1414 LOG_WARNING("target was not halted");
1415 return ERROR_TARGET_NOT_HALTED;
1416 }
1417
1418 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1419
1420 arm11_common_t * arm11 = target->arch_info;
1421
1422 retval = arm11_run_instr_data_prepare(arm11);
1423 if (retval != ERROR_OK)
1424 return retval;
1425
1426 /* MRC p14,0,r0,c0,c5,0 */
1427 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1428 if (retval != ERROR_OK)
1429 return retval;
1430
1431 /* burst writes are not used for single words as those may well be
1432 * reset init script writes.
1433 *
1434 * The other advantage is that as burst writes are default, we'll
1435 * now exercise both burst and non-burst code paths with the
1436 * default settings, increasing code coverage.
1437 */
1438 bool burst = arm11_config_memwrite_burst && (count > 1);
1439
1440 switch (size)
1441 {
1442 case 1:
1443 {
1444 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1445
1446 for (size_t i = 0; i < count; i++)
1447 {
1448 /* MRC p14,0,r1,c0,c5,0 */
1449 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1450 if (retval != ERROR_OK)
1451 return retval;
1452
1453 /* strb r1, [r0], #1 */
1454 /* strb r1, [r0] */
1455 retval = arm11_run_instr_no_data1(arm11,
1456 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1457 if (retval != ERROR_OK)
1458 return retval;
1459 }
1460
1461 break;
1462 }
1463
1464 case 2:
1465 {
1466 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1467
1468 for (size_t i = 0; i < count; i++)
1469 {
1470 uint16_t value;
1471 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1472
1473 /* MRC p14,0,r1,c0,c5,0 */
1474 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1475 if (retval != ERROR_OK)
1476 return retval;
1477
1478 /* strh r1, [r0], #2 */
1479 /* strh r1, [r0] */
1480 retval = arm11_run_instr_no_data1(arm11,
1481 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1482 if (retval != ERROR_OK)
1483 return retval;
1484 }
1485
1486 break;
1487 }
1488
1489 case 4: {
1490 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1491
1492 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1493 uint32_t *words = (uint32_t*)buffer;
1494
1495 if (!burst)
1496 {
1497 /* STC p14,c5,[R0],#4 */
1498 /* STC p14,c5,[R0]*/
1499 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1500 if (retval != ERROR_OK)
1501 return retval;
1502 }
1503 else
1504 {
1505 /* STC p14,c5,[R0],#4 */
1506 /* STC p14,c5,[R0]*/
1507 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1508 if (retval != ERROR_OK)
1509 return retval;
1510 }
1511
1512 break;
1513 }
1514 }
1515
1516 /* r0 verification */
1517 if (!arm11_config_memrw_no_increment)
1518 {
1519 uint32_t r0;
1520
1521 /* MCR p14,0,R0,c0,c5,0 */
1522 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1523 if (retval != ERROR_OK)
1524 return retval;
1525
1526 if (address + size * count != r0)
1527 {
1528 LOG_ERROR("Data transfer failed. Expected end "
1529 "address 0x%08x, got 0x%08x",
1530 (unsigned) (address + size * count),
1531 (unsigned) r0);
1532
1533 if (burst)
1534 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1535
1536 if (arm11_config_memwrite_error_fatal)
1537 return ERROR_FAIL;
1538 }
1539 }
1540
1541 return arm11_run_instr_data_finish(arm11);
1542 }
1543
1544 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1545 {
1546 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1547 }
1548
1549 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1550 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1551 {
1552 FNC_INFO;
1553
1554 if (target->state != TARGET_HALTED)
1555 {
1556 LOG_WARNING("target was not halted");
1557 return ERROR_TARGET_NOT_HALTED;
1558 }
1559
1560 return arm11_write_memory(target, address, 4, count, buffer);
1561 }
1562
1563 /* here we have nothing target specific to contribute, so we fail and then the
1564 * fallback code will read data from the target and calculate the CRC on the
1565 * host.
1566 */
1567 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1568 {
1569 return ERROR_FAIL;
1570 }
1571
1572 /* target break-/watchpoint control
1573 * rw: 0 = write, 1 = read, 2 = access
1574 */
1575 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1576 {
1577 FNC_INFO;
1578
1579 arm11_common_t * arm11 = target->arch_info;
1580
1581 #if 0
1582 if (breakpoint->type == BKPT_SOFT)
1583 {
1584 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1585 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1586 }
1587 #endif
1588
1589 if (!arm11->free_brps)
1590 {
1591 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1592 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1593 }
1594
1595 if (breakpoint->length != 4)
1596 {
1597 LOG_DEBUG("only breakpoints of four bytes length supported");
1598 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1599 }
1600
1601 arm11->free_brps--;
1602
1603 return ERROR_OK;
1604 }
1605
1606 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1607 {
1608 FNC_INFO;
1609
1610 arm11_common_t * arm11 = target->arch_info;
1611
1612 arm11->free_brps++;
1613
1614 return ERROR_OK;
1615 }
1616
1617 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1618 {
1619 FNC_INFO_NOTIMPLEMENTED;
1620
1621 return ERROR_OK;
1622 }
1623
1624 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1625 {
1626 FNC_INFO_NOTIMPLEMENTED;
1627
1628 return ERROR_OK;
1629 }
1630
1631 // HACKHACKHACK - FIXME mode/state
1632 /* target algorithm support */
1633 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1634 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1635 int timeout_ms, void *arch_info)
1636 {
1637 arm11_common_t *arm11 = target->arch_info;
1638 // enum armv4_5_state core_state = arm11->core_state;
1639 // enum armv4_5_mode core_mode = arm11->core_mode;
1640 uint32_t context[16];
1641 uint32_t cpsr;
1642 int exit_breakpoint_size = 0;
1643 int retval = ERROR_OK;
1644 LOG_DEBUG("Running algorithm");
1645
1646
1647 if (target->state != TARGET_HALTED)
1648 {
1649 LOG_WARNING("target not halted");
1650 return ERROR_TARGET_NOT_HALTED;
1651 }
1652
1653 // FIXME
1654 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1655 // return ERROR_FAIL;
1656
1657 // Save regs
1658 for (unsigned i = 0; i < 16; i++)
1659 {
1660 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1661 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1662 }
1663
1664 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1665 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1666
1667 for (int i = 0; i < num_mem_params; i++)
1668 {
1669 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1670 }
1671
1672 // Set register parameters
1673 for (int i = 0; i < num_reg_params; i++)
1674 {
1675 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1676 if (!reg)
1677 {
1678 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1679 exit(-1);
1680 }
1681
1682 if (reg->size != reg_params[i].size)
1683 {
1684 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1685 exit(-1);
1686 }
1687 arm11_set_reg(reg,reg_params[i].value);
1688 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1689 }
1690
1691 exit_breakpoint_size = 4;
1692
1693 /* arm11->core_state = arm11_algorithm_info->core_state;
1694 if (arm11->core_state == ARMV4_5_STATE_ARM)
1695 exit_breakpoint_size = 4;
1696 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1697 exit_breakpoint_size = 2;
1698 else
1699 {
1700 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1701 exit(-1);
1702 }
1703 */
1704
1705
1706 /* arm11 at this point only supports ARM not THUMB mode
1707 however if this test needs to be reactivated the current state can be read back
1708 from CPSR */
1709 #if 0
1710 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1711 {
1712 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1713 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1714 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1715 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1716 }
1717 #endif
1718
1719 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1720 {
1721 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1722 retval = ERROR_TARGET_FAILURE;
1723 goto restore;
1724 }
1725
1726 // no debug, otherwise breakpoint is not set
1727 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1728
1729 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1730
1731 if (target->state != TARGET_HALTED)
1732 {
1733 CHECK_RETVAL(target_halt(target));
1734
1735 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1736
1737 retval = ERROR_TARGET_TIMEOUT;
1738
1739 goto del_breakpoint;
1740 }
1741
1742 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1743 {
1744 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1745 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1746 retval = ERROR_TARGET_TIMEOUT;
1747 goto del_breakpoint;
1748 }
1749
1750 for (int i = 0; i < num_mem_params; i++)
1751 {
1752 if (mem_params[i].direction != PARAM_OUT)
1753 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1754 }
1755
1756 for (int i = 0; i < num_reg_params; i++)
1757 {
1758 if (reg_params[i].direction != PARAM_OUT)
1759 {
1760 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1761 if (!reg)
1762 {
1763 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1764 exit(-1);
1765 }
1766
1767 if (reg->size != reg_params[i].size)
1768 {
1769 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1770 exit(-1);
1771 }
1772
1773 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1774 }
1775 }
1776
1777 del_breakpoint:
1778 breakpoint_remove(target, exit_point);
1779
1780 restore:
1781 // Restore context
1782 for (size_t i = 0; i < 16; i++)
1783 {
1784 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1785 arm11->reg_list[i].name, context[i]);
1786 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1787 }
1788 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1789 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1790
1791 // arm11->core_state = core_state;
1792 // arm11->core_mode = core_mode;
1793
1794 return retval;
1795 }
1796
1797 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1798 {
1799 FNC_INFO;
1800
1801 NEW(arm11_common_t, arm11, 1);
1802
1803 arm11->target = target;
1804
1805 if (target->tap == NULL)
1806 return ERROR_FAIL;
1807
1808 if (target->tap->ir_length != 5)
1809 {
1810 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1811 return ERROR_COMMAND_SYNTAX_ERROR;
1812 }
1813
1814 target->arch_info = arm11;
1815
1816 return ERROR_OK;
1817 }
1818
1819 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1820 {
1821 /* Initialize anything we can set up without talking to the target */
1822 return arm11_build_reg_cache(target);
1823 }
1824
1825 /* talk to the target and set things up */
1826 int arm11_examine(struct target_s *target)
1827 {
1828 int retval;
1829
1830 FNC_INFO;
1831
1832 arm11_common_t * arm11 = target->arch_info;
1833
1834 /* check IDCODE */
1835
1836 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1837
1838 scan_field_t idcode_field;
1839
1840 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1841
1842 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1843
1844 /* check DIDR */
1845
1846 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1847
1848 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1849
1850 scan_field_t chain0_fields[2];
1851
1852 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1853 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1854
1855 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1856
1857 CHECK_RETVAL(jtag_execute_queue());
1858
1859 switch (arm11->device_id & 0x0FFFF000)
1860 {
1861 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1862 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1863 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1864 default:
1865 {
1866 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1867 return ERROR_FAIL;
1868 }
1869 }
1870
1871 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1872
1873 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1874 arm11->debug_version != ARM11_DEBUG_V61)
1875 {
1876 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1877 return ERROR_FAIL;
1878 }
1879
1880 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1881 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1882
1883 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1884 arm11->free_brps = arm11->brp;
1885 arm11->free_wrps = arm11->wrp;
1886
1887 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1888 arm11->device_id,
1889 (int)(arm11->implementor),
1890 arm11->didr);
1891
1892 /* as a side-effect this reads DSCR and thus
1893 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1894 * as suggested by the spec.
1895 */
1896
1897 retval = arm11_check_init(arm11, NULL);
1898 if (retval != ERROR_OK)
1899 return retval;
1900
1901 target_set_examined(target);
1902
1903 return ERROR_OK;
1904 }
1905
1906
1907 /** Load a register that is marked !valid in the register cache */
1908 int arm11_get_reg(reg_t *reg)
1909 {
1910 FNC_INFO;
1911
1912 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1913
1914 if (target->state != TARGET_HALTED)
1915 {
1916 LOG_WARNING("target was not halted");
1917 return ERROR_TARGET_NOT_HALTED;
1918 }
1919
1920 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1921
1922 #if 0
1923 arm11_common_t *arm11 = target->arch_info;
1924 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1925 #endif
1926
1927 return ERROR_OK;
1928 }
1929
1930 /** Change a value in the register cache */
1931 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1932 {
1933 FNC_INFO;
1934
1935 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1936 arm11_common_t *arm11 = target->arch_info;
1937 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1938
1939 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1940 reg->valid = 1;
1941 reg->dirty = 1;
1942
1943 return ERROR_OK;
1944 }
1945
1946 int arm11_build_reg_cache(target_t *target)
1947 {
1948 arm11_common_t *arm11 = target->arch_info;
1949
1950 NEW(reg_cache_t, cache, 1);
1951 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1952 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1953
1954 if (arm11_regs_arch_type == -1)
1955 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1956
1957 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1958 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1959
1960 arm11->reg_list = reg_list;
1961
1962 /* Build the process context cache */
1963 cache->name = "arm11 registers";
1964 cache->next = NULL;
1965 cache->reg_list = reg_list;
1966 cache->num_regs = ARM11_REGCACHE_COUNT;
1967
1968 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1969 (*cache_p) = cache;
1970
1971 arm11->core_cache = cache;
1972 // armv7m->process_context = cache;
1973
1974 size_t i;
1975
1976 /* Not very elegant assertion */
1977 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1978 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1979 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1980 {
1981 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1982 exit(-1);
1983 }
1984
1985 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1986 {
1987 reg_t * r = reg_list + i;
1988 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1989 arm11_reg_state_t * rs = arm11_reg_states + i;
1990
1991 r->name = rd->name;
1992 r->size = 32;
1993 r->value = (uint8_t *)(arm11->reg_values + i);
1994 r->dirty = 0;
1995 r->valid = 0;
1996 r->bitfield_desc = NULL;
1997 r->num_bitfields = 0;
1998 r->arch_type = arm11_regs_arch_type;
1999 r->arch_info = rs;
2000
2001 rs->def_index = i;
2002 rs->target = target;
2003 }
2004
2005 return ERROR_OK;
2006 }
2007
2008 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
2009 {
2010 if (argc == 0)
2011 {
2012 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
2013 return ERROR_OK;
2014 }
2015
2016 if (argc != 1)
2017 return ERROR_COMMAND_SYNTAX_ERROR;
2018
2019 switch (args[0][0])
2020 {
2021 case '0': /* 0 */
2022 case 'f': /* false */
2023 case 'F':
2024 case 'd': /* disable */
2025 case 'D':
2026 *var = false;
2027 break;
2028
2029 case '1': /* 1 */
2030 case 't': /* true */
2031 case 'T':
2032 case 'e': /* enable */
2033 case 'E':
2034 *var = true;
2035 break;
2036 }
2037
2038 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2039
2040 return ERROR_OK;
2041 }
2042
2043 #define BOOL_WRAPPER(name, print_name) \
2044 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
2045 { \
2046 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
2047 }
2048
2049 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2050 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2051 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2052 BOOL_WRAPPER(hardware_step, "hardware single step")
2053
2054 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2055 {
2056 if (argc == 1)
2057 {
2058 arm11_vcr = strtoul(args[0], NULL, 0);
2059 }
2060 else if (argc != 0)
2061 {
2062 return ERROR_COMMAND_SYNTAX_ERROR;
2063 }
2064
2065 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2066 return ERROR_OK;
2067 }
2068
2069 const uint32_t arm11_coproc_instruction_limits[] =
2070 {
2071 15, /* coprocessor */
2072 7, /* opcode 1 */
2073 15, /* CRn */
2074 15, /* CRm */
2075 7, /* opcode 2 */
2076 0xFFFFFFFF, /* value */
2077 };
2078
2079 arm11_common_t * arm11_find_target(const char * arg)
2080 {
2081 jtag_tap_t * tap;
2082 target_t * t;
2083
2084 tap = jtag_tap_by_string(arg);
2085
2086 if (!tap)
2087 return 0;
2088
2089 for (t = all_targets; t; t = t->next)
2090 {
2091 if (t->tap != tap)
2092 continue;
2093
2094 /* if (t->type == arm11_target) */
2095 if (0 == strcmp(target_get_name(t), "arm11"))
2096 return t->arch_info;
2097 }
2098
2099 return 0;
2100 }
2101
2102 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2103 {
2104 int retval;
2105
2106 if (argc != (read ? 6 : 7))
2107 {
2108 LOG_ERROR("Invalid number of arguments.");
2109 return ERROR_COMMAND_SYNTAX_ERROR;
2110 }
2111
2112 arm11_common_t * arm11 = arm11_find_target(args[0]);
2113
2114 if (!arm11)
2115 {
2116 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2117 return ERROR_COMMAND_SYNTAX_ERROR;
2118 }
2119
2120 if (arm11->target->state != TARGET_HALTED)
2121 {
2122 LOG_WARNING("target was not halted");
2123 return ERROR_TARGET_NOT_HALTED;
2124 }
2125
2126 uint32_t values[6];
2127
2128 for (size_t i = 0; i < (read ? 5 : 6); i++)
2129 {
2130 values[i] = strtoul(args[i + 1], NULL, 0);
2131
2132 if (values[i] > arm11_coproc_instruction_limits[i])
2133 {
2134 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2135 (long)(i + 2),
2136 arm11_coproc_instruction_limits[i]);
2137 return ERROR_COMMAND_SYNTAX_ERROR;
2138 }
2139 }
2140
2141 uint32_t instr = 0xEE000010 |
2142 (values[0] << 8) |
2143 (values[1] << 21) |
2144 (values[2] << 16) |
2145 (values[3] << 0) |
2146 (values[4] << 5);
2147
2148 if (read)
2149 instr |= 0x00100000;
2150
2151 retval = arm11_run_instr_data_prepare(arm11);
2152 if (retval != ERROR_OK)
2153 return retval;
2154
2155 if (read)
2156 {
2157 uint32_t result;
2158 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2159 if (retval != ERROR_OK)
2160 return retval;
2161
2162 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2163 (int)(values[0]),
2164 (int)(values[1]),
2165 (int)(values[2]),
2166 (int)(values[3]),
2167 (int)(values[4]), result, result);
2168 }
2169 else
2170 {
2171 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2172 if (retval != ERROR_OK)
2173 return retval;
2174
2175 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2176 (int)(values[0]), (int)(values[1]),
2177 values[5],
2178 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2179 }
2180
2181 return arm11_run_instr_data_finish(arm11);
2182 }
2183
2184 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2185 {
2186 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2187 }
2188
2189 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2190 {
2191 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2192 }
2193
2194 int arm11_register_commands(struct command_context_s *cmd_ctx)
2195 {
2196 FNC_INFO;
2197
2198 command_t *top_cmd, *mw_cmd;
2199
2200 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2201 NULL, COMMAND_ANY, NULL);
2202
2203 /* "hardware_step" is only here to check if the default
2204 * simulate + breakpoint implementation is broken.
2205 * TEMPORARY! NOT DOCUMENTED!
2206 */
2207 register_command(cmd_ctx, top_cmd, "hardware_step",
2208 arm11_handle_bool_hardware_step, COMMAND_ANY,
2209 "DEBUG ONLY - Hardware single stepping"
2210 " (default: disabled)");
2211
2212 register_command(cmd_ctx, top_cmd, "mcr",
2213 arm11_handle_mcr, COMMAND_ANY,
2214 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2215
2216 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2217 NULL, COMMAND_ANY, NULL);
2218 register_command(cmd_ctx, mw_cmd, "burst",
2219 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2220 "Enable/Disable non-standard but fast burst mode"
2221 " (default: enabled)");
2222 register_command(cmd_ctx, mw_cmd, "error_fatal",
2223 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2224 "Terminate program if transfer error was found"
2225 " (default: enabled)");
2226
2227 register_command(cmd_ctx, top_cmd, "mrc",
2228 arm11_handle_mrc, COMMAND_ANY,
2229 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2230 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2231 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2232 "Enable interrupts while stepping"
2233 " (default: disabled)");
2234 register_command(cmd_ctx, top_cmd, "vcr",
2235 arm11_handle_vcr, COMMAND_ANY,
2236 "Control (Interrupt) Vector Catch Register");
2237
2238 return ERROR_OK;
2239 }
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