src/target/mips32.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
   8  *   drasko.draskovic@gmail.com                                            *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  22  ***************************************************************************/
  23
  24 #ifndef OPENOCD_TARGET_MIPS32_H
  25 #define OPENOCD_TARGET_MIPS32_H
  26
  27 #include "target.h"
  28 #include "mips32_pracc.h"
  29
  30 #define MIPS32_COMMON_MAGIC             0xB320B320
  31
  32 /**
  33  * Memory segments (32bit kernel mode addresses)
  34  * These are the traditional names used in the 32-bit universe.
  35  */
  36 #define KUSEG                   0x00000000
  37 #define KSEG0                   0x80000000
  38 #define KSEG1                   0xa0000000
  39 #define KSEG2                   0xc0000000
  40 #define KSEG3                   0xe0000000
  41
  42 /** Returns the kernel segment base of a given address */
  43 #define KSEGX(a)                ((a) & 0xe0000000)
  44
  45 /** CP0 CONFIG register fields */
  46 #define MIPS32_CONFIG0_KU_SHIFT 25
  47 #define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
  48
  49 #define MIPS32_CONFIG0_K0_SHIFT 0
  50 #define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)
  51
  52 #define MIPS32_CONFIG0_K23_SHIFT 28
  53 #define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)
  54
  55 #define MIPS32_CONFIG0_AR_SHIFT 10
  56 #define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
  57
  58 #define MIPS32_CONFIG1_DL_SHIFT 10
  59 #define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
  60
  61 #define MIPS32_CONFIG3_ISA_SHIFT        14
  62 #define MIPS32_CONFIG3_ISA_MASK         (3 << MIPS32_CONFIG3_ISA_SHIFT)
  63
  64 #define MIPS32_ARCH_REL1 0x0
  65 #define MIPS32_ARCH_REL2 0x1
  66
  67 #define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
  68
  69 /* offsets into mips32 core register cache */
  70 enum {
  71         MIPS32_PC = 37,
  72         MIPS32_FIR = 71,
  73         MIPS32NUMCOREREGS
  74 };
  75
  76 enum mips32_isa_mode {
  77         MIPS32_ISA_MIPS32 = 0,
  78         MIPS32_ISA_MIPS16E = 1,
  79         MIPS32_ISA_MMIPS32 = 3,
  80 };
  81
  82 enum mips32_isa_imp {
  83         MIPS32_ONLY = 0,
  84         MMIPS32_ONLY = 1,
  85         MIPS32_MIPS16 = 2,
  86         MIPS32_MMIPS32 = 3,
  87 };
  88
  89 struct mips32_comparator {
  90         int used;
  91         uint32_t bp_value;
  92         uint32_t reg_address;
  93 };
  94
  95 struct mips32_common {
  96         uint32_t common_magic;
  97         void *arch_info;
  98         struct reg_cache *core_cache;
  99         struct mips_ejtag ejtag_info;
 100         uint32_t core_regs[MIPS32NUMCOREREGS];
 101         enum mips32_isa_mode isa_mode;
 102         enum mips32_isa_imp isa_imp;
 103
 104         /* working area for fastdata access */
 105         struct working_area *fast_data_area;
 106
 107         int bp_scanned;
 108         int num_inst_bpoints;
 109         int num_data_bpoints;
 110         int num_inst_bpoints_avail;
 111         int num_data_bpoints_avail;
 112         struct mips32_comparator *inst_break_list;
 113         struct mips32_comparator *data_break_list;
 114
 115         /* register cache to processor synchronization */
 116         int (*read_core_reg)(struct target *target, unsigned int num);
 117         int (*write_core_reg)(struct target *target, unsigned int num);
 118 };
 119
 120 static inline struct mips32_common *
 121 target_to_mips32(struct target *target)
 122 {
 123         return target->arch_info;
 124 }
 125
 126 struct mips32_core_reg {
 127         uint32_t num;
 128         struct target *target;
 129         struct mips32_common *mips32_common;
 130 };
 131
 132 struct mips32_algorithm {
 133         int common_magic;
 134         enum mips32_isa_mode isa_mode;
 135 };
 136
 137 #define MIPS32_OP_ADDU  0x21u
 138 #define MIPS32_OP_ADDIU 0x09u
 139 #define MIPS32_OP_ANDI  0x0Cu
 140 #define MIPS32_OP_BEQ   0x04u
 141 #define MIPS32_OP_BGTZ  0x07u
 142 #define MIPS32_OP_BNE   0x05u
 143 #define MIPS32_OP_ADDI  0x08u
 144 #define MIPS32_OP_AND   0x24u
 145 #define MIPS32_OP_CACHE 0x2Fu
 146 #define MIPS32_OP_COP0  0x10u
 147 #define MIPS32_OP_J     0x02u
 148 #define MIPS32_OP_JR    0x08u
 149 #define MIPS32_OP_LUI   0x0Fu
 150 #define MIPS32_OP_LW    0x23u
 151 #define MIPS32_OP_LB    0x20u
 152 #define MIPS32_OP_LBU   0x24u
 153 #define MIPS32_OP_LHU   0x25u
 154 #define MIPS32_OP_MFHI  0x10u
 155 #define MIPS32_OP_MTHI  0x11u
 156 #define MIPS32_OP_MFLO  0x12u
 157 #define MIPS32_OP_MTLO  0x13u
 158 #define MIPS32_OP_RDHWR 0x3Bu
 159 #define MIPS32_OP_SB    0x28u
 160 #define MIPS32_OP_SH    0x29u
 161 #define MIPS32_OP_SW    0x2Bu
 162 #define MIPS32_OP_ORI   0x0Du
 163 #define MIPS32_OP_XORI  0x0Eu
 164 #define MIPS32_OP_XOR   0x26u
 165 #define MIPS32_OP_SLTU  0x2Bu
 166 #define MIPS32_OP_SRL   0x03u
 167 #define MIPS32_OP_SYNCI 0x1Fu
 168 #define MIPS32_OP_SLL   0x00u
 169 #define MIPS32_OP_SLTI  0x0Au
 170 #define MIPS32_OP_MOVN  0x0Bu
 171
 172 #define MIPS32_OP_REGIMM        0x01u
 173 #define MIPS32_OP_SDBBP 0x3Fu
 174 #define MIPS32_OP_SPECIAL       0x00u
 175 #define MIPS32_OP_SPECIAL2      0x07u
 176 #define MIPS32_OP_SPECIAL3      0x1Fu
 177
 178 #define MIPS32_COP0_MF  0x00u
 179 #define MIPS32_COP0_MT  0x04u
 180
 181 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
 182         (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
 183 #define MIPS32_I_INST(opcode, rs, rt, immd) \
 184         (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
 185 #define MIPS32_J_INST(opcode, addr)     (((opcode) << 26) | (addr))
 186
 187 #define MIPS32_ISA_NOP                          0
 188 #define MIPS32_ISA_ADDI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
 189 #define MIPS32_ISA_ADDIU(tar, src, val)         MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)
 190 #define MIPS32_ISA_ADDU(dst, src, tar)          MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)
 191 #define MIPS32_ISA_AND(dst, src, tar)           MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)
 192 #define MIPS32_ISA_ANDI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)
 193
 194 #define MIPS32_ISA_B(off)                       MIPS32_ISA_BEQ(0, 0, off)
 195 #define MIPS32_ISA_BEQ(src, tar, off)           MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 196 #define MIPS32_ISA_BGTZ(reg, off)               MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
 197 #define MIPS32_ISA_BNE(src, tar, off)           MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 198 #define MIPS32_ISA_CACHE(op, off, base)         MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
 199 #define MIPS32_ISA_J(tar)                       MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
 200 #define MIPS32_ISA_JR(reg)                      MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 201
 202 #define MIPS32_ISA_LB(reg, off, base)           MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)
 203 #define MIPS32_ISA_LBU(reg, off, base)          MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
 204 #define MIPS32_ISA_LHU(reg, off, base)          MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
 205 #define MIPS32_ISA_LUI(reg, val)                MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
 206 #define MIPS32_ISA_LW(reg, off, base)           MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
 207
 208 #define MIPS32_ISA_MFC0(gpr, cpr, sel)          MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 209 #define MIPS32_ISA_MTC0(gpr, cpr, sel)          MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 210 #define MIPS32_ISA_MFLO(reg)                    MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
 211 #define MIPS32_ISA_MFHI(reg)                    MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
 212 #define MIPS32_ISA_MTLO(reg)                    MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
 213 #define MIPS32_ISA_MTHI(reg)                    MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 214
 215 #define MIPS32_ISA_MOVN(dst, src, tar)          MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)
 216 #define MIPS32_ISA_ORI(tar, src, val)           MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 217 #define MIPS32_ISA_RDHWR(tar, dst)              MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
 218 #define MIPS32_ISA_SB(reg, off, base)           MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 219 #define MIPS32_ISA_SH(reg, off, base)           MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
 220 #define MIPS32_ISA_SW(reg, off, base)           MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
 221
 222 #define MIPS32_ISA_SLL(dst, src, sa)            MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
 223 #define MIPS32_ISA_SLTI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
 224 #define MIPS32_ISA_SLTU(dst, src, tar)          MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
 225 #define MIPS32_ISA_SRL(reg, src, off)           MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
 226 #define MIPS32_ISA_SYNC                         0xFu
 227 #define MIPS32_ISA_SYNCI(off, base)             MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
 228
 229 #define MIPS32_ISA_XOR(reg, val1, val2)         MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
 230 #define MIPS32_ISA_XORI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
 231
 232 #define MIPS32_ISA_SYNCI_STEP           0x1     /* reg num od address step size to be used with synci instruction */
 233
 234 /**
 235  * Cache operations definitions
 236  * Operation field is 5 bits long :
 237  * 1) bits 1..0 hold cache type
 238  * 2) bits 4..2 hold operation code
 239  */
 240 #define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))
 241 #define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))
 242
 243 /* ejtag specific instructions */
 244 #define MIPS32_ISA_DRET                         0x4200001Fu
 245 /* MIPS32_ISA_J_INST(MIPS32_ISA_OP_SPECIAL2, MIPS32_ISA_OP_SDBBP) */
 246 #define MIPS32_ISA_SDBBP                        0x7000003Fu
 247 #define MIPS16_ISA_SDBBP                        0xE801u
 248
 249 /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
 250 #define POOL32A                                 0X00u
 251 #define POOL32AXf                               0x3Cu
 252 #define POOL32B                                 0x08u
 253 #define POOL32I                                 0x10u
 254 #define MMIPS32_OP_ADDI                 0x04u
 255 #define MMIPS32_OP_ADDIU                0x0Cu
 256 #define MMIPS32_OP_ADDU                 0x150u
 257 #define MMIPS32_OP_AND                  0x250u
 258 #define MMIPS32_OP_ANDI                 0x34u
 259 #define MMIPS32_OP_BEQ                  0x25u
 260 #define MMIPS32_OP_BGTZ                 0x06u
 261 #define MMIPS32_OP_BNE                  0x2Du
 262 #define MMIPS32_OP_CACHE                0x06u
 263 #define MMIPS32_OP_J                    0x35u
 264 #define MMIPS32_OP_JALR                 0x03Cu
 265 #define MMIPS32_OP_LB                   0x07u
 266 #define MMIPS32_OP_LBU                  0x05u
 267 #define MMIPS32_OP_LHU                  0x0Du
 268 #define MMIPS32_OP_LUI                  0x0Du
 269 #define MMIPS32_OP_LW                   0x3Fu
 270 #define MMIPS32_OP_MFC0                 0x03u
 271 #define MMIPS32_OP_MTC0                 0x0Bu
 272 #define MMIPS32_OP_MFLO                 0x075u
 273 #define MMIPS32_OP_MFHI                 0x035u
 274 #define MMIPS32_OP_MTLO                 0x0F5u
 275 #define MMIPS32_OP_MTHI                 0x0B5u
 276 #define MMIPS32_OP_MOVN                 0x018u
 277 #define MMIPS32_OP_ORI                  0x14u
 278 #define MMIPS32_OP_RDHWR                0x1ACu
 279 #define MMIPS32_OP_SB                   0x06u
 280 #define MMIPS32_OP_SH                   0x0Eu
 281 #define MMIPS32_OP_SW                   0x3Eu
 282 #define MMIPS32_OP_SLTU                 0x390u
 283 #define MMIPS32_OP_SLL                  0x000u
 284 #define MMIPS32_OP_SLTI                 0x24u
 285 #define MMIPS32_OP_SRL                  0x040u
 286 #define MMIPS32_OP_SYNCI                0x10u
 287 #define MMIPS32_OP_XOR                  0x310u
 288 #define MMIPS32_OP_XORI                 0x1Cu
 289
 290 #define MMIPS32_ADDI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
 291 #define MMIPS32_ADDIU(tar, src, val)            MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
 292 #define MMIPS32_ADDU(dst, src, tar)             MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
 293 #define MMIPS32_AND(dst, src, tar)              MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
 294 #define MMIPS32_ANDI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
 295
 296 #define MMIPS32_B(off)                          MMIPS32_BEQ(0, 0, off)
 297 #define MMIPS32_BEQ(src, tar, off)              MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
 298 #define MMIPS32_BGTZ(reg, off)                  MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off)
 299 #define MMIPS32_BNE(src, tar, off)              MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
 300 #define MMIPS32_CACHE(op, off, base)            MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
 301
 302 #define MMIPS32_J(tar)                          MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
 303 #define MMIPS32_JR(reg)                         MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXf)
 304 #define MMIPS32_LB(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
 305 #define MMIPS32_LBU(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
 306 #define MMIPS32_LHU(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
 307 #define MMIPS32_LUI(reg, val)                   MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
 308 #define MMIPS32_LW(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
 309
 310 #define MMIPS32_MFC0(gpr, cpr, sel)             MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXf)
 311 #define MMIPS32_MFLO(reg)                       MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXf)
 312 #define MMIPS32_MFHI(reg)                       MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXf)
 313 #define MMIPS32_MTC0(gpr, cpr, sel)             MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXf)
 314 #define MMIPS32_MTLO(reg)                       MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXf)
 315 #define MMIPS32_MTHI(reg)                       MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXf)
 316
 317 #define MMIPS32_MOVN(dst, src, tar)             MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
 318 #define MMIPS32_NOP                             0
 319 #define MMIPS32_ORI(tar, src, val)              MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
 320 #define MMIPS32_RDHWR(tar, dst)                 MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXf)
 321 #define MMIPS32_SB(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
 322 #define MMIPS32_SH(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
 323 #define MMIPS32_SW(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
 324
 325 #define MMIPS32_SRL(reg, src, off)              MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
 326 #define MMIPS32_SLTU(dst, src, tar)             MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
 327 #define MMIPS32_SYNCI(off, base)                MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
 328 #define MMIPS32_SLL(dst, src, sa)               MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
 329 #define MMIPS32_SLTI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
 330 #define MMIPS32_SYNC                            0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXf) */
 331
 332 #define MMIPS32_XOR(reg, val1, val2)            MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
 333 #define MMIPS32_XORI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
 334
 335 #define MMIPS32_SYNCI_STEP      0x1u    /* reg num od address step size to be used with synci instruction */
 336
 337
 338 /* ejtag specific instructions */
 339 #define MMIPS32_DRET                    0x0000E37Cu     /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXf) */
 340 #define MMIPS32_SDBBP                   0x0000DB7Cu     /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXf) */
 341 #define MMIPS16_SDBBP                   0x46C0u         /* POOL16C instr */
 342
 343 /* instruction code with isa selection */
 344 #define MIPS32_NOP                              0       /* same for both isa's */
 345 #define MIPS32_ADDI(isa, tar, src, val)         (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))
 346 #define MIPS32_ADDIU(isa, tar, src, val)        (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))
 347 #define MIPS32_ADDU(isa, dst, src, tar)         (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))
 348 #define MIPS32_AND(isa, dst, src, tar)          (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))
 349 #define MIPS32_ANDI(isa, tar, src, val)         (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))
 350
 351 #define MIPS32_B(isa, off)                      (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))
 352 #define MIPS32_BEQ(isa, src, tar, off)          (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))
 353 #define MIPS32_BGTZ(isa, reg, off)              (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))
 354 #define MIPS32_BNE(isa, src, tar, off)          (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))
 355 #define MIPS32_CACHE(isa, op, off, base)        (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))
 356
 357 #define MIPS32_J(isa, tar)                      (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
 358 #define MIPS32_JR(isa, reg)                     (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
 359 #define MIPS32_LB(isa, reg, off, base)          (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))
 360 #define MIPS32_LBU(isa, reg, off, base)         (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
 361 #define MIPS32_LHU(isa, reg, off, base)         (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
 362 #define MIPS32_LW(isa, reg, off, base)          (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))
 363 #define MIPS32_LUI(isa, reg, val)               (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
 364
 365 #define MIPS32_MFC0(isa, gpr, cpr, sel)         (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))
 366 #define MIPS32_MTC0(isa, gpr, cpr, sel)         (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))
 367 #define MIPS32_MFLO(isa, reg)                   (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))
 368 #define MIPS32_MFHI(isa, reg)                   (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))
 369 #define MIPS32_MTLO(isa, reg)                   (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
 370 #define MIPS32_MTHI(isa, reg)                   (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))
 371
 372 #define MIPS32_MOVN(isa, dst, src, tar)         (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))
 373 #define MIPS32_ORI(isa, tar, src, val)          (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))
 374 #define MIPS32_RDHWR(isa, tar, dst)             (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))
 375 #define MIPS32_SB(isa, reg, off, base)          (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))
 376 #define MIPS32_SH(isa, reg, off, base)          (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))
 377 #define MIPS32_SW(isa, reg, off, base)          (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
 378
 379 #define MIPS32_SLL(isa, dst, src, sa)           (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
 380 #define MIPS32_SLTI(isa, tar, src, val)         (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))
 381 #define MIPS32_SLTU(isa, dst, src, tar)         (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))
 382 #define MIPS32_SRL(isa, reg, src, off)          (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))
 383
 384 #define MIPS32_SYNCI(isa, off, base)            (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))
 385 #define MIPS32_SYNC(isa)                        (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)
 386 #define MIPS32_XOR(isa, reg, val1, val2)        (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))
 387 #define MIPS32_XORI(isa, tar, src, val)         (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))
 388
 389 #define MIPS32_SYNCI_STEP                       0x1
 390
 391 /* ejtag specific instructions */
 392 #define MIPS32_DRET(isa)                        (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)
 393 #define MIPS32_SDBBP(isa)                       (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)
 394
 395 #define MIPS16_SDBBP(isa)                       (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
 396
 397 extern const struct command_registration mips32_command_handlers[];
 398
 399 int mips32_arch_state(struct target *target);
 400
 401 int mips32_init_arch_info(struct target *target,
 402                 struct mips32_common *mips32, struct jtag_tap *tap);
 403
 404 int mips32_restore_context(struct target *target);
 405 int mips32_save_context(struct target *target);
 406
 407 struct reg_cache *mips32_build_reg_cache(struct target *target);
 408
 409 int mips32_run_algorithm(struct target *target,
 410                 int num_mem_params, struct mem_param *mem_params,
 411                 int num_reg_params, struct reg_param *reg_params,
 412                 target_addr_t entry_point, target_addr_t exit_point,
 413                 int timeout_ms, void *arch_info);
 414
 415 int mips32_configure_break_unit(struct target *target);
 416
 417 int mips32_enable_interrupts(struct target *target, int enable);
 418
 419 int mips32_examine(struct target *target);
 420
 421 int mips32_read_config_regs(struct target *target);
 422
 423 int mips32_register_commands(struct command_context *cmd_ctx);
 424
 425 int mips32_get_gdb_reg_list(struct target *target,
 426                 struct reg **reg_list[], int *reg_list_size,
 427                 enum target_register_class reg_class);
 428 int mips32_checksum_memory(struct target *target, target_addr_t address,
 429                 uint32_t count, uint32_t *checksum);
 430 int mips32_blank_check_memory(struct target *target,
 431                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 432
 433 #endif /* OPENOCD_TARGET_MIPS32_H */