Add jtag_event_handler_t:
[openocd.git] / src / flash / at91sam7.h
blob5e652bf06d8da692ad145dcfaa26d1f902ed34fc
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2006 by Gheorghe Guran (atlas) *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
23 #ifndef AT91SAM7_H
24 #define AT91SAM7_H
26 #include "flash.h"
28 typedef struct at91sam7_flash_bank_s
30 /* chip id register */
31 u32 cidr;
32 u16 cidr_ext;
33 u16 cidr_nvptyp;
34 u16 cidr_arch;
35 u16 cidr_sramsiz;
36 u16 cidr_nvpsiz;
37 u16 cidr_nvpsiz2;
38 u16 cidr_eproc;
39 u16 cidr_version;
40 char *target_name;
42 /* flash auto-detection */
43 u8 flash_autodetection;
45 /* flash geometry */
46 u16 pages_per_sector;
47 u16 pagesize;
48 u16 pages_in_lockregion;
50 /* nv memory bits */
51 u16 num_lockbits_on;
52 u16 lockbits;
53 u16 num_nvmbits;
54 u16 num_nvmbits_on;
55 u16 nvmbits;
56 u8 securitybit;
58 /* 0: not init
59 * 1: fmcn for nvbits (1uS)
60 * 2: fmcn for flash (1.5uS) */
61 u8 flashmode;
63 /* main clock status */
64 u8 mck_valid;
65 u32 mck_freq;
67 /* external clock frequency */
68 u32 ext_freq;
70 } at91sam7_flash_bank_t;
73 /* AT91SAM7 control registers */
74 #define DBGU_CIDR 0xFFFFF240
75 #define CKGR_MCFR 0xFFFFFC24
76 #define CKGR_MOR 0xFFFFFC20
77 #define CKGR_MCFR_MAINRDY 0x10000
78 #define CKGR_PLLR 0xFFFFFC2c
79 #define CKGR_PLLR_DIV 0xff
80 #define CKGR_PLLR_MUL 0x07ff0000
81 #define PMC_MCKR 0xFFFFFC30
82 #define PMC_MCKR_CSS 0x03
83 #define PMC_MCKR_PRES 0x1c
85 /* Flash Controller Commands */
86 #define WP 0x01
87 #define SLB 0x02
88 #define WPL 0x03
89 #define CLB 0x04
90 #define EA 0x08
91 #define SGPB 0x0B
92 #define CGPB 0x0D
93 #define SSB 0x0F
95 /* MC_FSR bit definitions */
96 #define MC_FSR_FRDY 1
97 #define MC_FSR_EOL 2
99 /* AT91SAM7 constants */
100 #define RC_FREQ 32000
102 /* Flash timing modes */
103 #define FMR_TIMING_NONE 0
104 #define FMR_TIMING_NVBITS 1
105 #define FMR_TIMING_FLASH 2
107 /* Flash size constants */
108 #define FLASH_SIZE_8KB 1
109 #define FLASH_SIZE_16KB 2
110 #define FLASH_SIZE_32KB 3
111 #define FLASH_SIZE_64KB 5
112 #define FLASH_SIZE_128KB 7
113 #define FLASH_SIZE_256KB 9
114 #define FLASH_SIZE_512KB 10
115 #define FLASH_SIZE_1024KB 12
116 #define FLASH_SIZE_2048KB 14
118 #endif /* AT91SAM7_H */