Add RISC-V support.
[openocd.git] / src / target / nds32_v3m.h
blob1e7427c48b158c4ed4c4baeed5563cf3456cb71c
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_NDS32_V3M_H
20 #define OPENOCD_TARGET_NDS32_V3M_H
22 #include "nds32.h"
24 struct nds32_v3m_common {
25 struct nds32 nds32;
27 /** number of hardware breakpoints */
28 int32_t n_hbr;
30 /** number of hardware watchpoints */
31 int32_t n_hwp;
33 /** number of used hardware watchpoints */
34 int32_t used_n_wp;
36 /** next hardware breakpoint index */
37 /** for simple breakpoints, hardware breakpoints are inserted
38 * from high index to low index */
39 int32_t next_hbr_index;
41 /** next hardware watchpoint index */
42 /** increase from low index to high index */
43 int32_t next_hwp_index;
46 static inline struct nds32_v3m_common *target_to_nds32_v3m(struct target *target)
48 return container_of(target->arch_info, struct nds32_v3m_common, nds32);
51 #endif /* OPENOCD_TARGET_NDS32_V3M_H */