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Add RISC-V support.
[openocd.git] / src / target / cortex_m.c
blobdcb3ddd8264f14f60ec4ef4880ec1d89f20fd66b
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* clear any interrupt masking */
241 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
242
243 /* Enable features controlled by ITM and DWT blocks, and catch only
244 * the vectors we were told to pay attention to.
245 *
246 * Target firmware is responsible for all fault handling policy
247 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
248 * or manual updates to the NVIC SHCSR and CCR registers.
249 */
250 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
251 if (retval != ERROR_OK)
252 return retval;
253
254 /* Paranoia: evidently some (early?) chips don't preserve all the
255 * debug state (including FBP, DWT, etc) across reset...
256 */
257
258 /* Enable FPB */
259 retval = cortex_m_enable_fpb(target);
260 if (retval != ERROR_OK) {
261 LOG_ERROR("Failed to enable the FPB");
262 return retval;
263 }
264
265 cortex_m->fpb_enabled = 1;
266
267 /* Restore FPB registers */
268 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
269 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
270 if (retval != ERROR_OK)
271 return retval;
272 }
273
274 /* Restore DWT registers */
275 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
276 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
277 dwt_list[i].comp);
278 if (retval != ERROR_OK)
279 return retval;
280 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
281 dwt_list[i].mask);
282 if (retval != ERROR_OK)
283 return retval;
284 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
285 dwt_list[i].function);
286 if (retval != ERROR_OK)
287 return retval;
288 }
289 retval = dap_run(swjdp);
290 if (retval != ERROR_OK)
291 return retval;
292
293 register_cache_invalidate(armv7m->arm.core_cache);
294
295 /* make sure we have latest dhcsr flags */
296 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
297
298 return retval;
299 }
300
301 static int cortex_m_examine_debug_reason(struct target *target)
302 {
303 struct cortex_m_common *cortex_m = target_to_cm(target);
304
305 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
306 * only check the debug reason if we don't know it already */
307
308 if ((target->debug_reason != DBG_REASON_DBGRQ)
309 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
310 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
311 target->debug_reason = DBG_REASON_BREAKPOINT;
312 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
313 target->debug_reason = DBG_REASON_WPTANDBKPT;
314 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
315 target->debug_reason = DBG_REASON_WATCHPOINT;
316 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
317 target->debug_reason = DBG_REASON_BREAKPOINT;
318 else /* EXTERNAL, HALTED */
319 target->debug_reason = DBG_REASON_UNDEFINED;
320 }
321
322 return ERROR_OK;
323 }
324
325 static int cortex_m_examine_exception_reason(struct target *target)
326 {
327 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
328 struct armv7m_common *armv7m = target_to_armv7m(target);
329 struct adiv5_dap *swjdp = armv7m->arm.dap;
330 int retval;
331
332 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
333 if (retval != ERROR_OK)
334 return retval;
335 switch (armv7m->exception_number) {
336 case 2: /* NMI */
337 break;
338 case 3: /* Hard Fault */
339 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
340 if (retval != ERROR_OK)
341 return retval;
342 if (except_sr & 0x40000000) {
343 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
344 if (retval != ERROR_OK)
345 return retval;
346 }
347 break;
348 case 4: /* Memory Management */
349 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
350 if (retval != ERROR_OK)
351 return retval;
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
353 if (retval != ERROR_OK)
354 return retval;
355 break;
356 case 5: /* Bus Fault */
357 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
358 if (retval != ERROR_OK)
359 return retval;
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
361 if (retval != ERROR_OK)
362 return retval;
363 break;
364 case 6: /* Usage Fault */
365 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
366 if (retval != ERROR_OK)
367 return retval;
368 break;
369 case 11: /* SVCall */
370 break;
371 case 12: /* Debug Monitor */
372 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
373 if (retval != ERROR_OK)
374 return retval;
375 break;
376 case 14: /* PendSV */
377 break;
378 case 15: /* SysTick */
379 break;
380 default:
381 except_sr = 0;
382 break;
383 }
384 retval = dap_run(swjdp);
385 if (retval == ERROR_OK)
386 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
387 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
388 armv7m_exception_string(armv7m->exception_number),
389 shcsr, except_sr, cfsr, except_ar);
390 return retval;
391 }
392
393 static int cortex_m_debug_entry(struct target *target)
394 {
395 int i;
396 uint32_t xPSR;
397 int retval;
398 struct cortex_m_common *cortex_m = target_to_cm(target);
399 struct armv7m_common *armv7m = &cortex_m->armv7m;
400 struct arm *arm = &armv7m->arm;
401 struct reg *r;
402
403 LOG_DEBUG(" ");
404
405 cortex_m_clear_halt(target);
406 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
407 if (retval != ERROR_OK)
408 return retval;
409
410 retval = armv7m->examine_debug_reason(target);
411 if (retval != ERROR_OK)
412 return retval;
413
414 /* Examine target state and mode
415 * First load register accessible through core debug port */
416 int num_regs = arm->core_cache->num_regs;
417
418 for (i = 0; i < num_regs; i++) {
419 r = &armv7m->arm.core_cache->reg_list[i];
420 if (!r->valid)
421 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
422 }
423
424 r = arm->cpsr;
425 xPSR = buf_get_u32(r->value, 0, 32);
426
427 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
428 if (xPSR & 0xf00) {
429 r->dirty = r->valid;
430 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
431 }
432
433 /* Are we in an exception handler */
434 if (xPSR & 0x1FF) {
435 armv7m->exception_number = (xPSR & 0x1FF);
436
437 arm->core_mode = ARM_MODE_HANDLER;
438 arm->map = armv7m_msp_reg_map;
439 } else {
440 unsigned control = buf_get_u32(arm->core_cache
441 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
442
443 /* is this thread privileged? */
444 arm->core_mode = control & 1
445 ? ARM_MODE_USER_THREAD
446 : ARM_MODE_THREAD;
447
448 /* which stack is it using? */
449 if (control & 2)
450 arm->map = armv7m_psp_reg_map;
451 else
452 arm->map = armv7m_msp_reg_map;
453
454 armv7m->exception_number = 0;
455 }
456
457 if (armv7m->exception_number)
458 cortex_m_examine_exception_reason(target);
459
460 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
461 arm_mode_name(arm->core_mode),
462 buf_get_u32(arm->pc->value, 0, 32),
463 target_state_name(target));
464
465 if (armv7m->post_debug_entry) {
466 retval = armv7m->post_debug_entry(target);
467 if (retval != ERROR_OK)
468 return retval;
469 }
470
471 return ERROR_OK;
472 }
473
474 static int cortex_m_poll(struct target *target)
475 {
476 int detected_failure = ERROR_OK;
477 int retval = ERROR_OK;
478 enum target_state prev_target_state = target->state;
479 struct cortex_m_common *cortex_m = target_to_cm(target);
480 struct armv7m_common *armv7m = &cortex_m->armv7m;
481
482 /* Read from Debug Halting Control and Status Register */
483 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
484 if (retval != ERROR_OK) {
485 target->state = TARGET_UNKNOWN;
486 return retval;
487 }
488
489 /* Recover from lockup. See ARMv7-M architecture spec,
490 * section B1.5.15 "Unrecoverable exception cases".
491 */
492 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
493 LOG_ERROR("%s -- clearing lockup after double fault",
494 target_name(target));
495 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
496 target->debug_reason = DBG_REASON_DBGRQ;
497
498 /* We have to execute the rest (the "finally" equivalent, but
499 * still throw this exception again).
500 */
501 detected_failure = ERROR_FAIL;
502
503 /* refresh status bits */
504 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
505 if (retval != ERROR_OK)
506 return retval;
507 }
508
509 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
510 target->state = TARGET_RESET;
511 return ERROR_OK;
512 }
513
514 if (target->state == TARGET_RESET) {
515 /* Cannot switch context while running so endreset is
516 * called with target->state == TARGET_RESET
517 */
518 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
519 cortex_m->dcb_dhcsr);
520 retval = cortex_m_endreset_event(target);
521 if (retval != ERROR_OK) {
522 target->state = TARGET_UNKNOWN;
523 return retval;
524 }
525 target->state = TARGET_RUNNING;
526 prev_target_state = TARGET_RUNNING;
527 }
528
529 if (cortex_m->dcb_dhcsr & S_HALT) {
530 target->state = TARGET_HALTED;
531
532 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
533 retval = cortex_m_debug_entry(target);
534 if (retval != ERROR_OK)
535 return retval;
536
537 if (arm_semihosting(target, &retval) != 0)
538 return retval;
539
540 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
541 }
542 if (prev_target_state == TARGET_DEBUG_RUNNING) {
543 LOG_DEBUG(" ");
544 retval = cortex_m_debug_entry(target);
545 if (retval != ERROR_OK)
546 return retval;
547
548 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
549 }
550 }
551
552 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
553 * How best to model low power modes?
554 */
555
556 if (target->state == TARGET_UNKNOWN) {
557 /* check if processor is retiring instructions */
558 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
559 target->state = TARGET_RUNNING;
560 retval = ERROR_OK;
561 }
562 }
563
564 /* Did we detect a failure condition that we cleared? */
565 if (detected_failure != ERROR_OK)
566 retval = detected_failure;
567 return retval;
568 }
569
570 static int cortex_m_halt(struct target *target)
571 {
572 LOG_DEBUG("target->state: %s",
573 target_state_name(target));
574
575 if (target->state == TARGET_HALTED) {
576 LOG_DEBUG("target was already halted");
577 return ERROR_OK;
578 }
579
580 if (target->state == TARGET_UNKNOWN)
581 LOG_WARNING("target was in unknown state when halt was requested");
582
583 if (target->state == TARGET_RESET) {
584 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
585 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
586 return ERROR_TARGET_FAILURE;
587 } else {
588 /* we came here in a reset_halt or reset_init sequence
589 * debug entry was already prepared in cortex_m3_assert_reset()
590 */
591 target->debug_reason = DBG_REASON_DBGRQ;
592
593 return ERROR_OK;
594 }
595 }
596
597 /* Write to Debug Halting Control and Status Register */
598 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
599
600 target->debug_reason = DBG_REASON_DBGRQ;
601
602 return ERROR_OK;
603 }
604
605 static int cortex_m_soft_reset_halt(struct target *target)
606 {
607 struct cortex_m_common *cortex_m = target_to_cm(target);
608 struct armv7m_common *armv7m = &cortex_m->armv7m;
609 uint32_t dcb_dhcsr = 0;
610 int retval, timeout = 0;
611
612 /* soft_reset_halt is deprecated on cortex_m as the same functionality
613 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
614 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
615 * core, not the peripherals */
616 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
617
618 /* Enter debug state on reset; restore DEMCR in endreset_event() */
619 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
620 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
621 if (retval != ERROR_OK)
622 return retval;
623
624 /* Request a core-only reset */
625 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
626 AIRCR_VECTKEY | AIRCR_VECTRESET);
627 if (retval != ERROR_OK)
628 return retval;
629 target->state = TARGET_RESET;
630
631 /* registers are now invalid */
632 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
633
634 while (timeout < 100) {
635 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
636 if (retval == ERROR_OK) {
637 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
638 &cortex_m->nvic_dfsr);
639 if (retval != ERROR_OK)
640 return retval;
641 if ((dcb_dhcsr & S_HALT)
642 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
643 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
644 "DFSR 0x%08x",
645 (unsigned) dcb_dhcsr,
646 (unsigned) cortex_m->nvic_dfsr);
647 cortex_m_poll(target);
648 /* FIXME restore user's vector catch config */
649 return ERROR_OK;
650 } else
651 LOG_DEBUG("waiting for system reset-halt, "
652 "DHCSR 0x%08x, %d ms",
653 (unsigned) dcb_dhcsr, timeout);
654 }
655 timeout++;
656 alive_sleep(1);
657 }
658
659 return ERROR_OK;
660 }
661
662 void cortex_m_enable_breakpoints(struct target *target)
663 {
664 struct breakpoint *breakpoint = target->breakpoints;
665
666 /* set any pending breakpoints */
667 while (breakpoint) {
668 if (!breakpoint->set)
669 cortex_m_set_breakpoint(target, breakpoint);
670 breakpoint = breakpoint->next;
671 }
672 }
673
674 static int cortex_m_resume(struct target *target, int current,
675 target_addr_t address, int handle_breakpoints, int debug_execution)
676 {
677 struct armv7m_common *armv7m = target_to_armv7m(target);
678 struct breakpoint *breakpoint = NULL;
679 uint32_t resume_pc;
680 struct reg *r;
681
682 if (target->state != TARGET_HALTED) {
683 LOG_WARNING("target not halted");
684 return ERROR_TARGET_NOT_HALTED;
685 }
686
687 if (!debug_execution) {
688 target_free_all_working_areas(target);
689 cortex_m_enable_breakpoints(target);
690 cortex_m_enable_watchpoints(target);
691 }
692
693 if (debug_execution) {
694 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
695
696 /* Disable interrupts */
697 /* We disable interrupts in the PRIMASK register instead of
698 * masking with C_MASKINTS. This is probably the same issue
699 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
700 * in parallel with disabled interrupts can cause local faults
701 * to not be taken.
702 *
703 * REVISIT this clearly breaks non-debug execution, since the
704 * PRIMASK register state isn't saved/restored... workaround
705 * by never resuming app code after debug execution.
706 */
707 buf_set_u32(r->value, 0, 1, 1);
708 r->dirty = true;
709 r->valid = true;
710
711 /* Make sure we are in Thumb mode */
712 r = armv7m->arm.cpsr;
713 buf_set_u32(r->value, 24, 1, 1);
714 r->dirty = true;
715 r->valid = true;
716 }
717
718 /* current = 1: continue on current pc, otherwise continue at <address> */
719 r = armv7m->arm.pc;
720 if (!current) {
721 buf_set_u32(r->value, 0, 32, address);
722 r->dirty = true;
723 r->valid = true;
724 }
725
726 /* if we halted last time due to a bkpt instruction
727 * then we have to manually step over it, otherwise
728 * the core will break again */
729
730 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
731 && !debug_execution)
732 armv7m_maybe_skip_bkpt_inst(target, NULL);
733
734 resume_pc = buf_get_u32(r->value, 0, 32);
735
736 armv7m_restore_context(target);
737
738 /* the front-end may request us not to handle breakpoints */
739 if (handle_breakpoints) {
740 /* Single step past breakpoint at current address */
741 breakpoint = breakpoint_find(target, resume_pc);
742 if (breakpoint) {
743 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
744 breakpoint->address,
745 breakpoint->unique_id);
746 cortex_m_unset_breakpoint(target, breakpoint);
747 cortex_m_single_step_core(target);
748 cortex_m_set_breakpoint(target, breakpoint);
749 }
750 }
751
752 /* Restart core */
753 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
754
755 target->debug_reason = DBG_REASON_NOTHALTED;
756
757 /* registers are now invalid */
758 register_cache_invalidate(armv7m->arm.core_cache);
759
760 if (!debug_execution) {
761 target->state = TARGET_RUNNING;
762 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
763 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
764 } else {
765 target->state = TARGET_DEBUG_RUNNING;
766 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
767 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
768 }
769
770 return ERROR_OK;
771 }
772
773 /* int irqstepcount = 0; */
774 static int cortex_m_step(struct target *target, int current,
775 target_addr_t address, int handle_breakpoints)
776 {
777 struct cortex_m_common *cortex_m = target_to_cm(target);
778 struct armv7m_common *armv7m = &cortex_m->armv7m;
779 struct breakpoint *breakpoint = NULL;
780 struct reg *pc = armv7m->arm.pc;
781 bool bkpt_inst_found = false;
782 int retval;
783 bool isr_timed_out = false;
784
785 if (target->state != TARGET_HALTED) {
786 LOG_WARNING("target not halted");
787 return ERROR_TARGET_NOT_HALTED;
788 }
789
790 /* current = 1: continue on current pc, otherwise continue at <address> */
791 if (!current)
792 buf_set_u32(pc->value, 0, 32, address);
793
794 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
795
796 /* the front-end may request us not to handle breakpoints */
797 if (handle_breakpoints) {
798 breakpoint = breakpoint_find(target, pc_value);
799 if (breakpoint)
800 cortex_m_unset_breakpoint(target, breakpoint);
801 }
802
803 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
804
805 target->debug_reason = DBG_REASON_SINGLESTEP;
806
807 armv7m_restore_context(target);
808
809 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
810
811 /* if no bkpt instruction is found at pc then we can perform
812 * a normal step, otherwise we have to manually step over the bkpt
813 * instruction - as such simulate a step */
814 if (bkpt_inst_found == false) {
815 /* Automatic ISR masking mode off: Just step over the next instruction */
816 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
817 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
818 else {
819 /* Process interrupts during stepping in a way they don't interfere
820 * debugging.
821 *
822 * Principle:
823 *
824 * Set a temporary break point at the current pc and let the core run
825 * with interrupts enabled. Pending interrupts get served and we run
826 * into the breakpoint again afterwards. Then we step over the next
827 * instruction with interrupts disabled.
828 *
829 * If the pending interrupts don't complete within time, we leave the
830 * core running. This may happen if the interrupts trigger faster
831 * than the core can process them or the handler doesn't return.
832 *
833 * If no more breakpoints are available we simply do a step with
834 * interrupts enabled.
835 *
836 */
837
838 /* 2012-09-29 ph
839 *
840 * If a break point is already set on the lower half word then a break point on
841 * the upper half word will not break again when the core is restarted. So we
842 * just step over the instruction with interrupts disabled.
843 *
844 * The documentation has no information about this, it was found by observation
845 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
846 * suffer from this problem.
847 *
848 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
849 * address has it always cleared. The former is done to indicate thumb mode
850 * to gdb.
851 *
852 */
853 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
854 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
855 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
856 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
857 /* Re-enable interrupts */
858 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
859 }
860 else {
861
862 /* Set a temporary break point */
863 if (breakpoint)
864 retval = cortex_m_set_breakpoint(target, breakpoint);
865 else
866 retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
867 bool tmp_bp_set = (retval == ERROR_OK);
868
869 /* No more breakpoints left, just do a step */
870 if (!tmp_bp_set)
871 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
872 else {
873 /* Start the core */
874 LOG_DEBUG("Starting core to serve pending interrupts");
875 int64_t t_start = timeval_ms();
876 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
877
878 /* Wait for pending handlers to complete or timeout */
879 do {
880 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
881 DCB_DHCSR,
882 &cortex_m->dcb_dhcsr);
883 if (retval != ERROR_OK) {
884 target->state = TARGET_UNKNOWN;
885 return retval;
886 }
887 isr_timed_out = ((timeval_ms() - t_start) > 500);
888 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
889
890 /* only remove breakpoint if we created it */
891 if (breakpoint)
892 cortex_m_unset_breakpoint(target, breakpoint);
893 else {
894 /* Remove the temporary breakpoint */
895 breakpoint_remove(target, pc_value);
896 }
897
898 if (isr_timed_out) {
899 LOG_DEBUG("Interrupt handlers didn't complete within time, "
900 "leaving target running");
901 } else {
902 /* Step over next instruction with interrupts disabled */
903 cortex_m_write_debug_halt_mask(target,
904 C_HALT | C_MASKINTS,
905 0);
906 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
907 /* Re-enable interrupts */
908 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
909 }
910 }
911 }
912 }
913 }
914
915 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
916 if (retval != ERROR_OK)
917 return retval;
918
919 /* registers are now invalid */
920 register_cache_invalidate(armv7m->arm.core_cache);
921
922 if (breakpoint)
923 cortex_m_set_breakpoint(target, breakpoint);
924
925 if (isr_timed_out) {
926 /* Leave the core running. The user has to stop execution manually. */
927 target->debug_reason = DBG_REASON_NOTHALTED;
928 target->state = TARGET_RUNNING;
929 return ERROR_OK;
930 }
931
932 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
933 " nvic_icsr = 0x%" PRIx32,
934 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
935
936 retval = cortex_m_debug_entry(target);
937 if (retval != ERROR_OK)
938 return retval;
939 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
940
941 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
942 " nvic_icsr = 0x%" PRIx32,
943 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
944
945 return ERROR_OK;
946 }
947
948 static int cortex_m_assert_reset(struct target *target)
949 {
950 struct cortex_m_common *cortex_m = target_to_cm(target);
951 struct armv7m_common *armv7m = &cortex_m->armv7m;
952 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
953
954 LOG_DEBUG("target->state: %s",
955 target_state_name(target));
956
957 enum reset_types jtag_reset_config = jtag_get_reset_config();
958
959 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
960 /* allow scripts to override the reset event */
961
962 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
963 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
964 target->state = TARGET_RESET;
965
966 return ERROR_OK;
967 }
968
969 /* some cores support connecting while srst is asserted
970 * use that mode is it has been configured */
971
972 bool srst_asserted = false;
973
974 if (!target_was_examined(target)) {
975 if (jtag_reset_config & RESET_HAS_SRST) {
976 adapter_assert_reset();
977 if (target->reset_halt)
978 LOG_ERROR("Target not examined, will not halt after reset!");
979 return ERROR_OK;
980 } else {
981 LOG_ERROR("Target not examined, reset NOT asserted!");
982 return ERROR_FAIL;
983 }
984 }
985
986 if ((jtag_reset_config & RESET_HAS_SRST) &&
987 (jtag_reset_config & RESET_SRST_NO_GATING)) {
988 adapter_assert_reset();
989 srst_asserted = true;
990 }
991
992 /* Enable debug requests */
993 int retval;
994 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
995 /* Store important errors instead of failing and proceed to reset assert */
996
997 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
998 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
999
1000 /* If the processor is sleeping in a WFI or WFE instruction, the
1001 * C_HALT bit must be asserted to regain control */
1002 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1003 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1004
1005 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1006 /* Ignore less important errors */
1007
1008 if (!target->reset_halt) {
1009 /* Set/Clear C_MASKINTS in a separate operation */
1010 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1011 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1012
1013 /* clear any debug flags before resuming */
1014 cortex_m_clear_halt(target);
1015
1016 /* clear C_HALT in dhcsr reg */
1017 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1018 } else {
1019 /* Halt in debug on reset; endreset_event() restores DEMCR.
1020 *
1021 * REVISIT catching BUSERR presumably helps to defend against
1022 * bad vector table entries. Should this include MMERR or
1023 * other flags too?
1024 */
1025 int retval2;
1026 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1027 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1028 if (retval != ERROR_OK || retval2 != ERROR_OK)
1029 LOG_INFO("AP write error, reset will not halt");
1030 }
1031
1032 if (jtag_reset_config & RESET_HAS_SRST) {
1033 /* default to asserting srst */
1034 if (!srst_asserted)
1035 adapter_assert_reset();
1036
1037 /* srst is asserted, ignore AP access errors */
1038 retval = ERROR_OK;
1039 } else {
1040 /* Use a standard Cortex-M3 software reset mechanism.
1041 * We default to using VECRESET as it is supported on all current cores.
1042 * This has the disadvantage of not resetting the peripherals, so a
1043 * reset-init event handler is needed to perform any peripheral resets.
1044 */
1045 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1046 ? "SYSRESETREQ" : "VECTRESET");
1047
1048 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1049 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1050 "handler to reset any peripherals or configure hardware srst support.");
1051 }
1052
1053 int retval3;
1054 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1055 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1056 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1057 if (retval3 != ERROR_OK)
1058 LOG_DEBUG("Ignoring AP write error right after reset");
1059
1060 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1061 if (retval3 != ERROR_OK)
1062 LOG_ERROR("DP initialisation failed");
1063
1064 else {
1065 /* I do not know why this is necessary, but it
1066 * fixes strange effects (step/resume cause NMI
1067 * after reset) on LM3S6918 -- Michael Schwingen
1068 */
1069 uint32_t tmp;
1070 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1071 }
1072 }
1073
1074 target->state = TARGET_RESET;
1075 jtag_add_sleep(50000);
1076
1077 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1078
1079 /* now return stored error code if any */
1080 if (retval != ERROR_OK)
1081 return retval;
1082
1083 if (target->reset_halt) {
1084 retval = target_halt(target);
1085 if (retval != ERROR_OK)
1086 return retval;
1087 }
1088
1089 return ERROR_OK;
1090 }
1091
1092 static int cortex_m_deassert_reset(struct target *target)
1093 {
1094 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1095
1096 LOG_DEBUG("target->state: %s",
1097 target_state_name(target));
1098
1099 /* deassert reset lines */
1100 adapter_deassert_reset();
1101
1102 enum reset_types jtag_reset_config = jtag_get_reset_config();
1103
1104 if ((jtag_reset_config & RESET_HAS_SRST) &&
1105 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1106 target_was_examined(target)) {
1107 int retval = dap_dp_init(armv7m->debug_ap->dap);
1108 if (retval != ERROR_OK) {
1109 LOG_ERROR("DP initialisation failed");
1110 return retval;
1111 }
1112 }
1113
1114 return ERROR_OK;
1115 }
1116
1117 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1118 {
1119 int retval;
1120 int fp_num = 0;
1121 struct cortex_m_common *cortex_m = target_to_cm(target);
1122 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1123
1124 if (breakpoint->set) {
1125 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1126 return ERROR_OK;
1127 }
1128
1129 if (breakpoint->type == BKPT_HARD) {
1130 uint32_t fpcr_value;
1131 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1132 fp_num++;
1133 if (fp_num >= cortex_m->fp_num_code) {
1134 LOG_ERROR("Can not find free FPB Comparator!");
1135 return ERROR_FAIL;
1136 }
1137 breakpoint->set = fp_num + 1;
1138 fpcr_value = breakpoint->address | 1;
1139 if (cortex_m->fp_rev == 0) {
1140 if (breakpoint->address > 0x1FFFFFFF) {
1141 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1142 return ERROR_FAIL;
1143 }
1144 uint32_t hilo;
1145 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1146 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1147 } else if (cortex_m->fp_rev > 1) {
1148 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1149 return ERROR_FAIL;
1150 }
1151 comparator_list[fp_num].used = 1;
1152 comparator_list[fp_num].fpcr_value = fpcr_value;
1153 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1154 comparator_list[fp_num].fpcr_value);
1155 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1156 fp_num,
1157 comparator_list[fp_num].fpcr_value);
1158 if (!cortex_m->fpb_enabled) {
1159 LOG_DEBUG("FPB wasn't enabled, do it now");
1160 retval = cortex_m_enable_fpb(target);
1161 if (retval != ERROR_OK) {
1162 LOG_ERROR("Failed to enable the FPB");
1163 return retval;
1164 }
1165
1166 cortex_m->fpb_enabled = 1;
1167 }
1168 } else if (breakpoint->type == BKPT_SOFT) {
1169 uint8_t code[4];
1170
1171 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1172 * semihosting; don't use that. Otherwise the BKPT
1173 * parameter is arbitrary.
1174 */
1175 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1176 retval = target_read_memory(target,
1177 breakpoint->address & 0xFFFFFFFE,
1178 breakpoint->length, 1,
1179 breakpoint->orig_instr);
1180 if (retval != ERROR_OK)
1181 return retval;
1182 retval = target_write_memory(target,
1183 breakpoint->address & 0xFFFFFFFE,
1184 breakpoint->length, 1,
1185 code);
1186 if (retval != ERROR_OK)
1187 return retval;
1188 breakpoint->set = true;
1189 }
1190
1191 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1192 breakpoint->unique_id,
1193 (int)(breakpoint->type),
1194 breakpoint->address,
1195 breakpoint->length,
1196 breakpoint->set);
1197
1198 return ERROR_OK;
1199 }
1200
1201 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1202 {
1203 int retval;
1204 struct cortex_m_common *cortex_m = target_to_cm(target);
1205 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1206
1207 if (!breakpoint->set) {
1208 LOG_WARNING("breakpoint not set");
1209 return ERROR_OK;
1210 }
1211
1212 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1213 breakpoint->unique_id,
1214 (int)(breakpoint->type),
1215 breakpoint->address,
1216 breakpoint->length,
1217 breakpoint->set);
1218
1219 if (breakpoint->type == BKPT_HARD) {
1220 int fp_num = breakpoint->set - 1;
1221 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1222 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1223 return ERROR_OK;
1224 }
1225 comparator_list[fp_num].used = 0;
1226 comparator_list[fp_num].fpcr_value = 0;
1227 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1228 comparator_list[fp_num].fpcr_value);
1229 } else {
1230 /* restore original instruction (kept in target endianness) */
1231 if (breakpoint->length == 4) {
1232 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1233 breakpoint->orig_instr);
1234 if (retval != ERROR_OK)
1235 return retval;
1236 } else {
1237 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1238 breakpoint->orig_instr);
1239 if (retval != ERROR_OK)
1240 return retval;
1241 }
1242 }
1243 breakpoint->set = false;
1244
1245 return ERROR_OK;
1246 }
1247
1248 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1249 {
1250 struct cortex_m_common *cortex_m = target_to_cm(target);
1251
1252 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1253 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1254 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1255 }
1256
1257 if (breakpoint->length == 3) {
1258 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1259 breakpoint->length = 2;
1260 }
1261
1262 if ((breakpoint->length != 2)) {
1263 LOG_INFO("only breakpoints of two bytes length supported");
1264 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1265 }
1266
1267 if (breakpoint->type == BKPT_HARD)
1268 cortex_m->fp_code_available--;
1269
1270 return cortex_m_set_breakpoint(target, breakpoint);
1271 }
1272
1273 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1274 {
1275 struct cortex_m_common *cortex_m = target_to_cm(target);
1276
1277 /* REVISIT why check? FBP can be updated with core running ... */
1278 if (target->state != TARGET_HALTED) {
1279 LOG_WARNING("target not halted");
1280 return ERROR_TARGET_NOT_HALTED;
1281 }
1282
1283 if (breakpoint->set)
1284 cortex_m_unset_breakpoint(target, breakpoint);
1285
1286 if (breakpoint->type == BKPT_HARD)
1287 cortex_m->fp_code_available++;
1288
1289 return ERROR_OK;
1290 }
1291
1292 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1293 {
1294 int dwt_num = 0;
1295 uint32_t mask, temp;
1296 struct cortex_m_common *cortex_m = target_to_cm(target);
1297
1298 /* watchpoint params were validated earlier */
1299 mask = 0;
1300 temp = watchpoint->length;
1301 while (temp) {
1302 temp >>= 1;
1303 mask++;
1304 }
1305 mask--;
1306
1307 /* REVISIT Don't fully trust these "not used" records ... users
1308 * may set up breakpoints by hand, e.g. dual-address data value
1309 * watchpoint using comparator #1; comparator #0 matching cycle
1310 * count; send data trace info through ITM and TPIU; etc
1311 */
1312 struct cortex_m_dwt_comparator *comparator;
1313
1314 for (comparator = cortex_m->dwt_comparator_list;
1315 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1316 comparator++, dwt_num++)
1317 continue;
1318 if (dwt_num >= cortex_m->dwt_num_comp) {
1319 LOG_ERROR("Can not find free DWT Comparator");
1320 return ERROR_FAIL;
1321 }
1322 comparator->used = 1;
1323 watchpoint->set = dwt_num + 1;
1324
1325 comparator->comp = watchpoint->address;
1326 target_write_u32(target, comparator->dwt_comparator_address + 0,
1327 comparator->comp);
1328
1329 comparator->mask = mask;
1330 target_write_u32(target, comparator->dwt_comparator_address + 4,
1331 comparator->mask);
1332
1333 switch (watchpoint->rw) {
1334 case WPT_READ:
1335 comparator->function = 5;
1336 break;
1337 case WPT_WRITE:
1338 comparator->function = 6;
1339 break;
1340 case WPT_ACCESS:
1341 comparator->function = 7;
1342 break;
1343 }
1344 target_write_u32(target, comparator->dwt_comparator_address + 8,
1345 comparator->function);
1346
1347 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1348 watchpoint->unique_id, dwt_num,
1349 (unsigned) comparator->comp,
1350 (unsigned) comparator->mask,
1351 (unsigned) comparator->function);
1352 return ERROR_OK;
1353 }
1354
1355 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1356 {
1357 struct cortex_m_common *cortex_m = target_to_cm(target);
1358 struct cortex_m_dwt_comparator *comparator;
1359 int dwt_num;
1360
1361 if (!watchpoint->set) {
1362 LOG_WARNING("watchpoint (wpid: %d) not set",
1363 watchpoint->unique_id);
1364 return ERROR_OK;
1365 }
1366
1367 dwt_num = watchpoint->set - 1;
1368
1369 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1370 watchpoint->unique_id, dwt_num,
1371 (unsigned) watchpoint->address);
1372
1373 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1374 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1375 return ERROR_OK;
1376 }
1377
1378 comparator = cortex_m->dwt_comparator_list + dwt_num;
1379 comparator->used = 0;
1380 comparator->function = 0;
1381 target_write_u32(target, comparator->dwt_comparator_address + 8,
1382 comparator->function);
1383
1384 watchpoint->set = false;
1385
1386 return ERROR_OK;
1387 }
1388
1389 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1390 {
1391 struct cortex_m_common *cortex_m = target_to_cm(target);
1392
1393 if (cortex_m->dwt_comp_available < 1) {
1394 LOG_DEBUG("no comparators?");
1395 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1396 }
1397
1398 /* hardware doesn't support data value masking */
1399 if (watchpoint->mask != ~(uint32_t)0) {
1400 LOG_DEBUG("watchpoint value masks not supported");
1401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1402 }
1403
1404 /* hardware allows address masks of up to 32K */
1405 unsigned mask;
1406
1407 for (mask = 0; mask < 16; mask++) {
1408 if ((1u << mask) == watchpoint->length)
1409 break;
1410 }
1411 if (mask == 16) {
1412 LOG_DEBUG("unsupported watchpoint length");
1413 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1414 }
1415 if (watchpoint->address & ((1 << mask) - 1)) {
1416 LOG_DEBUG("watchpoint address is unaligned");
1417 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1418 }
1419
1420 /* Caller doesn't seem to be able to describe watching for data
1421 * values of zero; that flags "no value".
1422 *
1423 * REVISIT This DWT may well be able to watch for specific data
1424 * values. Requires comparator #1 to set DATAVMATCH and match
1425 * the data, and another comparator (DATAVADDR0) matching addr.
1426 */
1427 if (watchpoint->value) {
1428 LOG_DEBUG("data value watchpoint not YET supported");
1429 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1430 }
1431
1432 cortex_m->dwt_comp_available--;
1433 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1434
1435 return ERROR_OK;
1436 }
1437
1438 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1439 {
1440 struct cortex_m_common *cortex_m = target_to_cm(target);
1441
1442 /* REVISIT why check? DWT can be updated with core running ... */
1443 if (target->state != TARGET_HALTED) {
1444 LOG_WARNING("target not halted");
1445 return ERROR_TARGET_NOT_HALTED;
1446 }
1447
1448 if (watchpoint->set)
1449 cortex_m_unset_watchpoint(target, watchpoint);
1450
1451 cortex_m->dwt_comp_available++;
1452 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1453
1454 return ERROR_OK;
1455 }
1456
1457 void cortex_m_enable_watchpoints(struct target *target)
1458 {
1459 struct watchpoint *watchpoint = target->watchpoints;
1460
1461 /* set any pending watchpoints */
1462 while (watchpoint) {
1463 if (!watchpoint->set)
1464 cortex_m_set_watchpoint(target, watchpoint);
1465 watchpoint = watchpoint->next;
1466 }
1467 }
1468
1469 static int cortex_m_load_core_reg_u32(struct target *target,
1470 uint32_t num, uint32_t *value)
1471 {
1472 int retval;
1473
1474 /* NOTE: we "know" here that the register identifiers used
1475 * in the v7m header match the Cortex-M3 Debug Core Register
1476 * Selector values for R0..R15, xPSR, MSP, and PSP.
1477 */
1478 switch (num) {
1479 case 0 ... 18:
1480 /* read a normal core register */
1481 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1482
1483 if (retval != ERROR_OK) {
1484 LOG_ERROR("JTAG failure %i", retval);
1485 return ERROR_JTAG_DEVICE_ERROR;
1486 }
1487 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1488 break;
1489
1490 case ARMV7M_FPSCR:
1491 /* Floating-point Status and Registers */
1492 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1493 if (retval != ERROR_OK)
1494 return retval;
1495 retval = target_read_u32(target, DCB_DCRDR, value);
1496 if (retval != ERROR_OK)
1497 return retval;
1498 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1499 break;
1500
1501 case ARMV7M_S0 ... ARMV7M_S31:
1502 /* Floating-point Status and Registers */
1503 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1504 if (retval != ERROR_OK)
1505 return retval;
1506 retval = target_read_u32(target, DCB_DCRDR, value);
1507 if (retval != ERROR_OK)
1508 return retval;
1509 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1510 (int)(num - ARMV7M_S0), *value);
1511 break;
1512
1513 case ARMV7M_PRIMASK:
1514 case ARMV7M_BASEPRI:
1515 case ARMV7M_FAULTMASK:
1516 case ARMV7M_CONTROL:
1517 /* Cortex-M3 packages these four registers as bitfields
1518 * in one Debug Core register. So say r0 and r2 docs;
1519 * it was removed from r1 docs, but still works.
1520 */
1521 cortexm_dap_read_coreregister_u32(target, value, 20);
1522
1523 switch (num) {
1524 case ARMV7M_PRIMASK:
1525 *value = buf_get_u32((uint8_t *)value, 0, 1);
1526 break;
1527
1528 case ARMV7M_BASEPRI:
1529 *value = buf_get_u32((uint8_t *)value, 8, 8);
1530 break;
1531
1532 case ARMV7M_FAULTMASK:
1533 *value = buf_get_u32((uint8_t *)value, 16, 1);
1534 break;
1535
1536 case ARMV7M_CONTROL:
1537 *value = buf_get_u32((uint8_t *)value, 24, 2);
1538 break;
1539 }
1540
1541 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1542 break;
1543
1544 default:
1545 return ERROR_COMMAND_SYNTAX_ERROR;
1546 }
1547
1548 return ERROR_OK;
1549 }
1550
1551 static int cortex_m_store_core_reg_u32(struct target *target,
1552 uint32_t num, uint32_t value)
1553 {
1554 int retval;
1555 uint32_t reg;
1556 struct armv7m_common *armv7m = target_to_armv7m(target);
1557
1558 /* NOTE: we "know" here that the register identifiers used
1559 * in the v7m header match the Cortex-M3 Debug Core Register
1560 * Selector values for R0..R15, xPSR, MSP, and PSP.
1561 */
1562 switch (num) {
1563 case 0 ... 18:
1564 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1565 if (retval != ERROR_OK) {
1566 struct reg *r;
1567
1568 LOG_ERROR("JTAG failure");
1569 r = armv7m->arm.core_cache->reg_list + num;
1570 r->dirty = r->valid;
1571 return ERROR_JTAG_DEVICE_ERROR;
1572 }
1573 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1574 break;
1575
1576 case ARMV7M_FPSCR:
1577 /* Floating-point Status and Registers */
1578 retval = target_write_u32(target, DCB_DCRDR, value);
1579 if (retval != ERROR_OK)
1580 return retval;
1581 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1582 if (retval != ERROR_OK)
1583 return retval;
1584 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1585 break;
1586
1587 case ARMV7M_S0 ... ARMV7M_S31:
1588 /* Floating-point Status and Registers */
1589 retval = target_write_u32(target, DCB_DCRDR, value);
1590 if (retval != ERROR_OK)
1591 return retval;
1592 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1593 if (retval != ERROR_OK)
1594 return retval;
1595 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1596 (int)(num - ARMV7M_S0), value);
1597 break;
1598
1599 case ARMV7M_PRIMASK:
1600 case ARMV7M_BASEPRI:
1601 case ARMV7M_FAULTMASK:
1602 case ARMV7M_CONTROL:
1603 /* Cortex-M3 packages these four registers as bitfields
1604 * in one Debug Core register. So say r0 and r2 docs;
1605 * it was removed from r1 docs, but still works.
1606 */
1607 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1608
1609 switch (num) {
1610 case ARMV7M_PRIMASK:
1611 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1612 break;
1613
1614 case ARMV7M_BASEPRI:
1615 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1616 break;
1617
1618 case ARMV7M_FAULTMASK:
1619 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1620 break;
1621
1622 case ARMV7M_CONTROL:
1623 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1624 break;
1625 }
1626
1627 cortexm_dap_write_coreregister_u32(target, reg, 20);
1628
1629 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1630 break;
1631
1632 default:
1633 return ERROR_COMMAND_SYNTAX_ERROR;
1634 }
1635
1636 return ERROR_OK;
1637 }
1638
1639 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1640 uint32_t size, uint32_t count, uint8_t *buffer)
1641 {
1642 struct armv7m_common *armv7m = target_to_armv7m(target);
1643
1644 if (armv7m->arm.is_armv6m) {
1645 /* armv6m does not handle unaligned memory access */
1646 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1647 return ERROR_TARGET_UNALIGNED_ACCESS;
1648 }
1649
1650 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1651 }
1652
1653 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1654 uint32_t size, uint32_t count, const uint8_t *buffer)
1655 {
1656 struct armv7m_common *armv7m = target_to_armv7m(target);
1657
1658 if (armv7m->arm.is_armv6m) {
1659 /* armv6m does not handle unaligned memory access */
1660 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1661 return ERROR_TARGET_UNALIGNED_ACCESS;
1662 }
1663
1664 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1665 }
1666
1667 static int cortex_m_init_target(struct command_context *cmd_ctx,
1668 struct target *target)
1669 {
1670 armv7m_build_reg_cache(target);
1671 arm_semihosting_init(target);
1672 return ERROR_OK;
1673 }
1674
1675 void cortex_m_deinit_target(struct target *target)
1676 {
1677 struct cortex_m_common *cortex_m = target_to_cm(target);
1678
1679 free(cortex_m->fp_comparator_list);
1680
1681 cortex_m_dwt_free(target);
1682 armv7m_free_reg_cache(target);
1683
1684 free(target->private_config);
1685 free(cortex_m);
1686 }
1687
1688 int cortex_m_profiling(struct target *target, uint32_t *samples,
1689 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1690 {
1691 struct timeval timeout, now;
1692 struct armv7m_common *armv7m = target_to_armv7m(target);
1693 uint32_t reg_value;
1694 bool use_pcsr = false;
1695 int retval = ERROR_OK;
1696 struct reg *reg;
1697
1698 gettimeofday(&timeout, NULL);
1699 timeval_add_time(&timeout, seconds, 0);
1700
1701 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1702 if (retval != ERROR_OK) {
1703 LOG_ERROR("Error while reading PCSR");
1704 return retval;
1705 }
1706
1707 if (reg_value != 0) {
1708 use_pcsr = true;
1709 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1710 } else {
1711 LOG_INFO("Starting profiling. Halting and resuming the"
1712 " target as often as we can...");
1713 reg = register_get_by_name(target->reg_cache, "pc", 1);
1714 }
1715
1716 /* Make sure the target is running */
1717 target_poll(target);
1718 if (target->state == TARGET_HALTED)
1719 retval = target_resume(target, 1, 0, 0, 0);
1720
1721 if (retval != ERROR_OK) {
1722 LOG_ERROR("Error while resuming target");
1723 return retval;
1724 }
1725
1726 uint32_t sample_count = 0;
1727
1728 for (;;) {
1729 if (use_pcsr) {
1730 if (armv7m && armv7m->debug_ap) {
1731 uint32_t read_count = max_num_samples - sample_count;
1732 if (read_count > 1024)
1733 read_count = 1024;
1734
1735 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1736 (void *)&samples[sample_count],
1737 4, read_count, DWT_PCSR);
1738 sample_count += read_count;
1739 } else {
1740 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1741 }
1742 } else {
1743 target_poll(target);
1744 if (target->state == TARGET_HALTED) {
1745 reg_value = buf_get_u32(reg->value, 0, 32);
1746 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1747 retval = target_resume(target, 1, 0, 0, 0);
1748 samples[sample_count++] = reg_value;
1749 target_poll(target);
1750 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1751 } else if (target->state == TARGET_RUNNING) {
1752 /* We want to quickly sample the PC. */
1753 retval = target_halt(target);
1754 } else {
1755 LOG_INFO("Target not halted or running");
1756 retval = ERROR_OK;
1757 break;
1758 }
1759 }
1760
1761 if (retval != ERROR_OK) {
1762 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1763 return retval;
1764 }
1765
1766
1767 gettimeofday(&now, NULL);
1768 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1769 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1770 break;
1771 }
1772 }
1773
1774 *num_samples = sample_count;
1775 return retval;
1776 }
1777
1778
1779 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1780 * on r/w if the core is not running, and clear on resume or reset ... or
1781 * at least, in a post_restore_context() method.
1782 */
1783
1784 struct dwt_reg_state {
1785 struct target *target;
1786 uint32_t addr;
1787 uint8_t value[4]; /* scratch/cache */
1788 };
1789
1790 static int cortex_m_dwt_get_reg(struct reg *reg)
1791 {
1792 struct dwt_reg_state *state = reg->arch_info;
1793
1794 uint32_t tmp;
1795 int retval = target_read_u32(state->target, state->addr, &tmp);
1796 if (retval != ERROR_OK)
1797 return retval;
1798
1799 buf_set_u32(state->value, 0, 32, tmp);
1800 return ERROR_OK;
1801 }
1802
1803 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1804 {
1805 struct dwt_reg_state *state = reg->arch_info;
1806
1807 return target_write_u32(state->target, state->addr,
1808 buf_get_u32(buf, 0, reg->size));
1809 }
1810
1811 struct dwt_reg {
1812 uint32_t addr;
1813 const char *name;
1814 unsigned size;
1815 };
1816
1817 static const struct dwt_reg dwt_base_regs[] = {
1818 { DWT_CTRL, "dwt_ctrl", 32, },
1819 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1820 * increments while the core is asleep.
1821 */
1822 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1823 /* plus some 8 bit counters, useful for profiling with TPIU */
1824 };
1825
1826 static const struct dwt_reg dwt_comp[] = {
1827 #define DWT_COMPARATOR(i) \
1828 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1829 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1830 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1831 DWT_COMPARATOR(0),
1832 DWT_COMPARATOR(1),
1833 DWT_COMPARATOR(2),
1834 DWT_COMPARATOR(3),
1835 DWT_COMPARATOR(4),
1836 DWT_COMPARATOR(5),
1837 DWT_COMPARATOR(6),
1838 DWT_COMPARATOR(7),
1839 DWT_COMPARATOR(8),
1840 DWT_COMPARATOR(9),
1841 DWT_COMPARATOR(10),
1842 DWT_COMPARATOR(11),
1843 DWT_COMPARATOR(12),
1844 DWT_COMPARATOR(13),
1845 DWT_COMPARATOR(14),
1846 DWT_COMPARATOR(15),
1847 #undef DWT_COMPARATOR
1848 };
1849
1850 static const struct reg_arch_type dwt_reg_type = {
1851 .get = cortex_m_dwt_get_reg,
1852 .set = cortex_m_dwt_set_reg,
1853 };
1854
1855 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1856 {
1857 struct dwt_reg_state *state;
1858
1859 state = calloc(1, sizeof *state);
1860 if (!state)
1861 return;
1862 state->addr = d->addr;
1863 state->target = t;
1864
1865 r->name = d->name;
1866 r->size = d->size;
1867 r->value = state->value;
1868 r->arch_info = state;
1869 r->type = &dwt_reg_type;
1870 }
1871
1872 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1873 {
1874 uint32_t dwtcr;
1875 struct reg_cache *cache;
1876 struct cortex_m_dwt_comparator *comparator;
1877 int reg, i;
1878
1879 target_read_u32(target, DWT_CTRL, &dwtcr);
1880 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1881 if (!dwtcr) {
1882 LOG_DEBUG("no DWT");
1883 return;
1884 }
1885
1886 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1887 cm->dwt_comp_available = cm->dwt_num_comp;
1888 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1889 sizeof(struct cortex_m_dwt_comparator));
1890 if (!cm->dwt_comparator_list) {
1891 fail0:
1892 cm->dwt_num_comp = 0;
1893 LOG_ERROR("out of mem");
1894 return;
1895 }
1896
1897 cache = calloc(1, sizeof *cache);
1898 if (!cache) {
1899 fail1:
1900 free(cm->dwt_comparator_list);
1901 goto fail0;
1902 }
1903 cache->name = "Cortex-M DWT registers";
1904 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1905 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1906 if (!cache->reg_list) {
1907 free(cache);
1908 goto fail1;
1909 }
1910
1911 for (reg = 0; reg < 2; reg++)
1912 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1913 dwt_base_regs + reg);
1914
1915 comparator = cm->dwt_comparator_list;
1916 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1917 int j;
1918
1919 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1920 for (j = 0; j < 3; j++, reg++)
1921 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1922 dwt_comp + 3 * i + j);
1923
1924 /* make sure we clear any watchpoints enabled on the target */
1925 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1926 }
1927
1928 *register_get_last_cache_p(&target->reg_cache) = cache;
1929 cm->dwt_cache = cache;
1930
1931 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1932 dwtcr, cm->dwt_num_comp,
1933 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1934
1935 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1936 * implement single-address data value watchpoints ... so we
1937 * won't need to check it later, when asked to set one up.
1938 */
1939 }
1940
1941 static void cortex_m_dwt_free(struct target *target)
1942 {
1943 struct cortex_m_common *cm = target_to_cm(target);
1944 struct reg_cache *cache = cm->dwt_cache;
1945
1946 free(cm->dwt_comparator_list);
1947 cm->dwt_comparator_list = NULL;
1948 cm->dwt_num_comp = 0;
1949
1950 if (cache) {
1951 register_unlink_cache(&target->reg_cache, cache);
1952
1953 if (cache->reg_list) {
1954 for (size_t i = 0; i < cache->num_regs; i++)
1955 free(cache->reg_list[i].arch_info);
1956 free(cache->reg_list);
1957 }
1958 free(cache);
1959 }
1960 cm->dwt_cache = NULL;
1961 }
1962
1963 #define MVFR0 0xe000ef40
1964 #define MVFR1 0xe000ef44
1965
1966 #define MVFR0_DEFAULT_M4 0x10110021
1967 #define MVFR1_DEFAULT_M4 0x11000011
1968
1969 #define MVFR0_DEFAULT_M7_SP 0x10110021
1970 #define MVFR0_DEFAULT_M7_DP 0x10110221
1971 #define MVFR1_DEFAULT_M7_SP 0x11000011
1972 #define MVFR1_DEFAULT_M7_DP 0x12000011
1973
1974 int cortex_m_examine(struct target *target)
1975 {
1976 int retval;
1977 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1978 int i;
1979 struct cortex_m_common *cortex_m = target_to_cm(target);
1980 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1981 struct armv7m_common *armv7m = target_to_armv7m(target);
1982
1983 /* stlink shares the examine handler but does not support
1984 * all its calls */
1985 if (!armv7m->stlink) {
1986 if (cortex_m->apsel < 0) {
1987 /* Search for the MEM-AP */
1988 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
1989 if (retval != ERROR_OK) {
1990 LOG_ERROR("Could not find MEM-AP to control the core");
1991 return retval;
1992 }
1993 } else {
1994 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1995 }
1996
1997 /* Leave (only) generic DAP stuff for debugport_init(); */
1998 armv7m->debug_ap->memaccess_tck = 8;
1999
2000 retval = mem_ap_init(armv7m->debug_ap);
2001 if (retval != ERROR_OK)
2002 return retval;
2003 }
2004
2005 if (!target_was_examined(target)) {
2006 target_set_examined(target);
2007
2008 /* Read from Device Identification Registers */
2009 retval = target_read_u32(target, CPUID, &cpuid);
2010 if (retval != ERROR_OK)
2011 return retval;
2012
2013 /* Get CPU Type */
2014 i = (cpuid >> 4) & 0xf;
2015
2016 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2017 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2018 if (i == 7) {
2019 uint8_t rev, patch;
2020 rev = (cpuid >> 20) & 0xf;
2021 patch = (cpuid >> 0) & 0xf;
2022 if ((rev == 0) && (patch < 2))
2023 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2024 }
2025 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2026
2027 if (i == 4) {
2028 target_read_u32(target, MVFR0, &mvfr0);
2029 target_read_u32(target, MVFR1, &mvfr1);
2030
2031 /* test for floating point feature on Cortex-M4 */
2032 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2033 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2034 armv7m->fp_feature = FPv4_SP;
2035 }
2036 } else if (i == 7) {
2037 target_read_u32(target, MVFR0, &mvfr0);
2038 target_read_u32(target, MVFR1, &mvfr1);
2039
2040 /* test for floating point features on Cortex-M7 */
2041 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2042 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2043 armv7m->fp_feature = FPv5_SP;
2044 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2045 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2046 armv7m->fp_feature = FPv5_DP;
2047 }
2048 } else if (i == 0) {
2049 /* Cortex-M0 does not support unaligned memory access */
2050 armv7m->arm.is_armv6m = true;
2051 }
2052
2053 if (armv7m->fp_feature == FP_NONE &&
2054 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2055 /* free unavailable FPU registers */
2056 size_t idx;
2057
2058 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2059 idx < armv7m->arm.core_cache->num_regs;
2060 idx++) {
2061 free(armv7m->arm.core_cache->reg_list[idx].value);
2062 free(armv7m->arm.core_cache->reg_list[idx].feature);
2063 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2064 }
2065 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2066 }
2067
2068 if (!armv7m->stlink) {
2069 if (i == 3 || i == 4)
2070 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2071 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2072 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2073 else if (i == 7)
2074 /* Cortex-M7 has only 1024 bytes autoincrement range */
2075 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2076 }
2077
2078 /* Configure trace modules */
2079 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2080 if (retval != ERROR_OK)
2081 return retval;
2082
2083 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2084 armv7m_trace_tpiu_config(target);
2085 armv7m_trace_itm_config(target);
2086 }
2087
2088 /* NOTE: FPB and DWT are both optional. */
2089
2090 /* Setup FPB */
2091 target_read_u32(target, FP_CTRL, &fpcr);
2092 /* bits [14:12] and [7:4] */
2093 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2094 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2095 cortex_m->fp_code_available = cortex_m->fp_num_code;
2096 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2097 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2098 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2099 free(cortex_m->fp_comparator_list);
2100 cortex_m->fp_comparator_list = calloc(
2101 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2102 sizeof(struct cortex_m_fp_comparator));
2103 cortex_m->fpb_enabled = fpcr & 1;
2104 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2105 cortex_m->fp_comparator_list[i].type =
2106 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2107 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2108
2109 /* make sure we clear any breakpoints enabled on the target */
2110 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2111 }
2112 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2113 fpcr,
2114 cortex_m->fp_num_code,
2115 cortex_m->fp_num_lit);
2116
2117 /* Setup DWT */
2118 cortex_m_dwt_free(target);
2119 cortex_m_dwt_setup(cortex_m, target);
2120
2121 /* These hardware breakpoints only work for code in flash! */
2122 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2123 target_name(target),
2124 cortex_m->fp_num_code,
2125 cortex_m->dwt_num_comp);
2126 }
2127
2128 return ERROR_OK;
2129 }
2130
2131 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2132 {
2133 struct armv7m_common *armv7m = target_to_armv7m(target);
2134 uint16_t dcrdr;
2135 uint8_t buf[2];
2136 int retval;
2137
2138 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2139 if (retval != ERROR_OK)
2140 return retval;
2141
2142 dcrdr = target_buffer_get_u16(target, buf);
2143 *ctrl = (uint8_t)dcrdr;
2144 *value = (uint8_t)(dcrdr >> 8);
2145
2146 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2147
2148 /* write ack back to software dcc register
2149 * signify we have read data */
2150 if (dcrdr & (1 << 0)) {
2151 target_buffer_set_u16(target, buf, 0);
2152 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2153 if (retval != ERROR_OK)
2154 return retval;
2155 }
2156
2157 return ERROR_OK;
2158 }
2159
2160 static int cortex_m_target_request_data(struct target *target,
2161 uint32_t size, uint8_t *buffer)
2162 {
2163 uint8_t data;
2164 uint8_t ctrl;
2165 uint32_t i;
2166
2167 for (i = 0; i < (size * 4); i++) {
2168 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2169 if (retval != ERROR_OK)
2170 return retval;
2171 buffer[i] = data;
2172 }
2173
2174 return ERROR_OK;
2175 }
2176
2177 static int cortex_m_handle_target_request(void *priv)
2178 {
2179 struct target *target = priv;
2180 if (!target_was_examined(target))
2181 return ERROR_OK;
2182
2183 if (!target->dbg_msg_enabled)
2184 return ERROR_OK;
2185
2186 if (target->state == TARGET_RUNNING) {
2187 uint8_t data;
2188 uint8_t ctrl;
2189 int retval;
2190
2191 retval = cortex_m_dcc_read(target, &data, &ctrl);
2192 if (retval != ERROR_OK)
2193 return retval;
2194
2195 /* check if we have data */
2196 if (ctrl & (1 << 0)) {
2197 uint32_t request;
2198
2199 /* we assume target is quick enough */
2200 request = data;
2201 for (int i = 1; i <= 3; i++) {
2202 retval = cortex_m_dcc_read(target, &data, &ctrl);
2203 if (retval != ERROR_OK)
2204 return retval;
2205 request |= ((uint32_t)data << (i * 8));
2206 }
2207 target_request(target, request);
2208 }
2209 }
2210
2211 return ERROR_OK;
2212 }
2213
2214 static int cortex_m_init_arch_info(struct target *target,
2215 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2216 {
2217 struct armv7m_common *armv7m = &cortex_m->armv7m;
2218
2219 armv7m_init_arch_info(target, armv7m);
2220
2221 /* default reset mode is to use srst if fitted
2222 * if not it will use CORTEX_M3_RESET_VECTRESET */
2223 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2224
2225 armv7m->arm.dap = dap;
2226
2227 /* register arch-specific functions */
2228 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2229
2230 armv7m->post_debug_entry = NULL;
2231
2232 armv7m->pre_restore_context = NULL;
2233
2234 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2235 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2236
2237 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2238
2239 return ERROR_OK;
2240 }
2241
2242 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2243 {
2244 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2245 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2246 struct adiv5_private_config *pc;
2247
2248 pc = (struct adiv5_private_config *)target->private_config;
2249 if (adiv5_verify_config(pc) != ERROR_OK)
2250 return ERROR_FAIL;
2251
2252 cortex_m->apsel = pc->ap_num;
2253
2254 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2255
2256 return ERROR_OK;
2257 }
2258
2259 /*--------------------------------------------------------------------------*/
2260
2261 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2262 struct cortex_m_common *cm)
2263 {
2264 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2265 command_print(cmd_ctx, "target is not a Cortex-M");
2266 return ERROR_TARGET_INVALID;
2267 }
2268 return ERROR_OK;
2269 }
2270
2271 /*
2272 * Only stuff below this line should need to verify that its target
2273 * is a Cortex-M3. Everything else should have indirected through the
2274 * cortexm3_target structure, which is only used with CM3 targets.
2275 */
2276
2277 static const struct {
2278 char name[10];
2279 unsigned mask;
2280 } vec_ids[] = {
2281 { "hard_err", VC_HARDERR, },
2282 { "int_err", VC_INTERR, },
2283 { "bus_err", VC_BUSERR, },
2284 { "state_err", VC_STATERR, },
2285 { "chk_err", VC_CHKERR, },
2286 { "nocp_err", VC_NOCPERR, },
2287 { "mm_err", VC_MMERR, },
2288 { "reset", VC_CORERESET, },
2289 };
2290
2291 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2292 {
2293 struct target *target = get_current_target(CMD_CTX);
2294 struct cortex_m_common *cortex_m = target_to_cm(target);
2295 struct armv7m_common *armv7m = &cortex_m->armv7m;
2296 uint32_t demcr = 0;
2297 int retval;
2298
2299 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2300 if (retval != ERROR_OK)
2301 return retval;
2302
2303 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2304 if (retval != ERROR_OK)
2305 return retval;
2306
2307 if (CMD_ARGC > 0) {
2308 unsigned catch = 0;
2309
2310 if (CMD_ARGC == 1) {
2311 if (strcmp(CMD_ARGV[0], "all") == 0) {
2312 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2313 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2314 | VC_MMERR | VC_CORERESET;
2315 goto write;
2316 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2317 goto write;
2318 }
2319 while (CMD_ARGC-- > 0) {
2320 unsigned i;
2321 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2322 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2323 continue;
2324 catch |= vec_ids[i].mask;
2325 break;
2326 }
2327 if (i == ARRAY_SIZE(vec_ids)) {
2328 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2329 return ERROR_COMMAND_SYNTAX_ERROR;
2330 }
2331 }
2332 write:
2333 /* For now, armv7m->demcr only stores vector catch flags. */
2334 armv7m->demcr = catch;
2335
2336 demcr &= ~0xffff;
2337 demcr |= catch;
2338
2339 /* write, but don't assume it stuck (why not??) */
2340 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2341 if (retval != ERROR_OK)
2342 return retval;
2343 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2344 if (retval != ERROR_OK)
2345 return retval;
2346
2347 /* FIXME be sure to clear DEMCR on clean server shutdown.
2348 * Otherwise the vector catch hardware could fire when there's
2349 * no debugger hooked up, causing much confusion...
2350 */
2351 }
2352
2353 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2354 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2355 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2356 }
2357
2358 return ERROR_OK;
2359 }
2360
2361 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2362 {
2363 struct target *target = get_current_target(CMD_CTX);
2364 struct cortex_m_common *cortex_m = target_to_cm(target);
2365 int retval;
2366
2367 static const Jim_Nvp nvp_maskisr_modes[] = {
2368 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2369 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2370 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2371 { .name = NULL, .value = -1 },
2372 };
2373 const Jim_Nvp *n;
2374
2375
2376 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2377 if (retval != ERROR_OK)
2378 return retval;
2379
2380 if (target->state != TARGET_HALTED) {
2381 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2382 return ERROR_OK;
2383 }
2384
2385 if (CMD_ARGC > 0) {
2386 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2387 if (n->name == NULL)
2388 return ERROR_COMMAND_SYNTAX_ERROR;
2389 cortex_m->isrmasking_mode = n->value;
2390
2391
2392 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2393 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2394 else
2395 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2396 }
2397
2398 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2399 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2400
2401 return ERROR_OK;
2402 }
2403
2404 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2405 {
2406 struct target *target = get_current_target(CMD_CTX);
2407 struct cortex_m_common *cortex_m = target_to_cm(target);
2408 int retval;
2409 char *reset_config;
2410
2411 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2412 if (retval != ERROR_OK)
2413 return retval;
2414
2415 if (CMD_ARGC > 0) {
2416 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2417 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2418 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2419 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2420 }
2421
2422 switch (cortex_m->soft_reset_config) {
2423 case CORTEX_M_RESET_SYSRESETREQ:
2424 reset_config = "sysresetreq";
2425 break;
2426
2427 case CORTEX_M_RESET_VECTRESET:
2428 reset_config = "vectreset";
2429 break;
2430
2431 default:
2432 reset_config = "unknown";
2433 break;
2434 }
2435
2436 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2437
2438 return ERROR_OK;
2439 }
2440
2441 static const struct command_registration cortex_m_exec_command_handlers[] = {
2442 {
2443 .name = "maskisr",
2444 .handler = handle_cortex_m_mask_interrupts_command,
2445 .mode = COMMAND_EXEC,
2446 .help = "mask cortex_m interrupts",
2447 .usage = "['auto'|'on'|'off']",
2448 },
2449 {
2450 .name = "vector_catch",
2451 .handler = handle_cortex_m_vector_catch_command,
2452 .mode = COMMAND_EXEC,
2453 .help = "configure hardware vectors to trigger debug entry",
2454 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2455 },
2456 {
2457 .name = "reset_config",
2458 .handler = handle_cortex_m_reset_config_command,
2459 .mode = COMMAND_ANY,
2460 .help = "configure software reset handling",
2461 .usage = "['srst'|'sysresetreq'|'vectreset']",
2462 },
2463 COMMAND_REGISTRATION_DONE
2464 };
2465 static const struct command_registration cortex_m_command_handlers[] = {
2466 {
2467 .chain = armv7m_command_handlers,
2468 },
2469 {
2470 .chain = armv7m_trace_command_handlers,
2471 },
2472 {
2473 .name = "cortex_m",
2474 .mode = COMMAND_EXEC,
2475 .help = "Cortex-M command group",
2476 .usage = "",
2477 .chain = cortex_m_exec_command_handlers,
2478 },
2479 COMMAND_REGISTRATION_DONE
2480 };
2481
2482 struct target_type cortexm_target = {
2483 .name = "cortex_m",
2484 .deprecated_name = "cortex_m3",
2485
2486 .poll = cortex_m_poll,
2487 .arch_state = armv7m_arch_state,
2488
2489 .target_request_data = cortex_m_target_request_data,
2490
2491 .halt = cortex_m_halt,
2492 .resume = cortex_m_resume,
2493 .step = cortex_m_step,
2494
2495 .assert_reset = cortex_m_assert_reset,
2496 .deassert_reset = cortex_m_deassert_reset,
2497 .soft_reset_halt = cortex_m_soft_reset_halt,
2498
2499 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2500
2501 .read_memory = cortex_m_read_memory,
2502 .write_memory = cortex_m_write_memory,
2503 .checksum_memory = armv7m_checksum_memory,
2504 .blank_check_memory = armv7m_blank_check_memory,
2505
2506 .run_algorithm = armv7m_run_algorithm,
2507 .start_algorithm = armv7m_start_algorithm,
2508 .wait_algorithm = armv7m_wait_algorithm,
2509
2510 .add_breakpoint = cortex_m_add_breakpoint,
2511 .remove_breakpoint = cortex_m_remove_breakpoint,
2512 .add_watchpoint = cortex_m_add_watchpoint,
2513 .remove_watchpoint = cortex_m_remove_watchpoint,
2514
2515 .commands = cortex_m_command_handlers,
2516 .target_create = cortex_m_target_create,
2517 .target_jim_configure = adiv5_jim_configure,
2518 .init_target = cortex_m_init_target,
2519 .examine = cortex_m_examine,
2520 .deinit_target = cortex_m_deinit_target,
2521
2522 .profiling = cortex_m_profiling,
2523 };
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