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Add RISC-V support.
[openocd.git] / src / target / cortex_a.c
blob21ce4fae83ee9bc8e7c444a891bffcfc3e2df566
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
16 * *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
19 * *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
22 * *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
25 * *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
30 * *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
35 * *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
38 * *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
43 * *
44 ***************************************************************************/
45
46 #ifdef HAVE_CONFIG_H
47 #include "config.h"
48 #endif
49
50 #include "breakpoints.h"
51 #include "cortex_a.h"
52 #include "register.h"
53 #include "target_request.h"
54 #include "target_type.h"
55 #include "arm_opcodes.h"
56 #include "arm_semihosting.h"
57 #include "transport/transport.h"
58 #include <helper/time_support.h>
59
60 static int cortex_a_poll(struct target *target);
61 static int cortex_a_debug_entry(struct target *target);
62 static int cortex_a_restore_context(struct target *target, bool bpwp);
63 static int cortex_a_set_breakpoint(struct target *target,
64 struct breakpoint *breakpoint, uint8_t matchmode);
65 static int cortex_a_set_context_breakpoint(struct target *target,
66 struct breakpoint *breakpoint, uint8_t matchmode);
67 static int cortex_a_set_hybrid_breakpoint(struct target *target,
68 struct breakpoint *breakpoint);
69 static int cortex_a_unset_breakpoint(struct target *target,
70 struct breakpoint *breakpoint);
71 static int cortex_a_dap_read_coreregister_u32(struct target *target,
72 uint32_t *value, int regnum);
73 static int cortex_a_dap_write_coreregister_u32(struct target *target,
74 uint32_t value, int regnum);
75 static int cortex_a_mmu(struct target *target, int *enabled);
76 static int cortex_a_mmu_modify(struct target *target, int enable);
77 static int cortex_a_virt2phys(struct target *target,
78 target_addr_t virt, target_addr_t *phys);
79 static int cortex_a_read_cpu_memory(struct target *target,
80 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
81
82
83 /* restore cp15_control_reg at resume */
84 static int cortex_a_restore_cp15_control_reg(struct target *target)
85 {
86 int retval = ERROR_OK;
87 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
88 struct armv7a_common *armv7a = target_to_armv7a(target);
89
90 if (cortex_a->cp15_control_reg != cortex_a->cp15_control_reg_curr) {
91 cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
92 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
93 retval = armv7a->arm.mcr(target, 15,
94 0, 0, /* op1, op2 */
95 1, 0, /* CRn, CRm */
96 cortex_a->cp15_control_reg);
97 }
98 return retval;
99 }
100
101 /*
102 * Set up ARM core for memory access.
103 * If !phys_access, switch to SVC mode and make sure MMU is on
104 * If phys_access, switch off mmu
105 */
106 static int cortex_a_prep_memaccess(struct target *target, int phys_access)
107 {
108 struct armv7a_common *armv7a = target_to_armv7a(target);
109 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
110 int mmu_enabled = 0;
111
112 if (phys_access == 0) {
113 dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
114 cortex_a_mmu(target, &mmu_enabled);
115 if (mmu_enabled)
116 cortex_a_mmu_modify(target, 1);
117 if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
118 /* overwrite DACR to all-manager */
119 armv7a->arm.mcr(target, 15,
120 0, 0, 3, 0,
121 0xFFFFFFFF);
122 }
123 } else {
124 cortex_a_mmu(target, &mmu_enabled);
125 if (mmu_enabled)
126 cortex_a_mmu_modify(target, 0);
127 }
128 return ERROR_OK;
129 }
130
131 /*
132 * Restore ARM core after memory access.
133 * If !phys_access, switch to previous mode
134 * If phys_access, restore MMU setting
135 */
136 static int cortex_a_post_memaccess(struct target *target, int phys_access)
137 {
138 struct armv7a_common *armv7a = target_to_armv7a(target);
139 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
140
141 if (phys_access == 0) {
142 if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
143 /* restore */
144 armv7a->arm.mcr(target, 15,
145 0, 0, 3, 0,
146 cortex_a->cp15_dacr_reg);
147 }
148 dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
149 } else {
150 int mmu_enabled = 0;
151 cortex_a_mmu(target, &mmu_enabled);
152 if (mmu_enabled)
153 cortex_a_mmu_modify(target, 1);
154 }
155 return ERROR_OK;
156 }
157
158
159 /* modify cp15_control_reg in order to enable or disable mmu for :
160 * - virt2phys address conversion
161 * - read or write memory in phys or virt address */
162 static int cortex_a_mmu_modify(struct target *target, int enable)
163 {
164 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
165 struct armv7a_common *armv7a = target_to_armv7a(target);
166 int retval = ERROR_OK;
167 int need_write = 0;
168
169 if (enable) {
170 /* if mmu enabled at target stop and mmu not enable */
171 if (!(cortex_a->cp15_control_reg & 0x1U)) {
172 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
173 return ERROR_FAIL;
174 }
175 if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0) {
176 cortex_a->cp15_control_reg_curr |= 0x1U;
177 need_write = 1;
178 }
179 } else {
180 if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0x1U) {
181 cortex_a->cp15_control_reg_curr &= ~0x1U;
182 need_write = 1;
183 }
184 }
185
186 if (need_write) {
187 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32,
188 enable ? "enable mmu" : "disable mmu",
189 cortex_a->cp15_control_reg_curr);
190
191 retval = armv7a->arm.mcr(target, 15,
192 0, 0, /* op1, op2 */
193 1, 0, /* CRn, CRm */
194 cortex_a->cp15_control_reg_curr);
195 }
196 return retval;
197 }
198
199 /*
200 * Cortex-A Basic debug access, very low level assumes state is saved
201 */
202 static int cortex_a_init_debug_access(struct target *target)
203 {
204 struct armv7a_common *armv7a = target_to_armv7a(target);
205 int retval;
206
207 /* lock memory-mapped access to debug registers to prevent
208 * software interference */
209 retval = mem_ap_write_u32(armv7a->debug_ap,
210 armv7a->debug_base + CPUDBG_LOCKACCESS, 0);
211 if (retval != ERROR_OK)
212 return retval;
213
214 /* Disable cacheline fills and force cache write-through in debug state */
215 retval = mem_ap_write_u32(armv7a->debug_ap,
216 armv7a->debug_base + CPUDBG_DSCCR, 0);
217 if (retval != ERROR_OK)
218 return retval;
219
220 /* Disable TLB lookup and refill/eviction in debug state */
221 retval = mem_ap_write_u32(armv7a->debug_ap,
222 armv7a->debug_base + CPUDBG_DSMCR, 0);
223 if (retval != ERROR_OK)
224 return retval;
225
226 retval = dap_run(armv7a->debug_ap->dap);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enabling of instruction execution in debug mode is done in debug_entry code */
231
232 /* Resync breakpoint registers */
233
234 /* Since this is likely called from init or reset, update target state information*/
235 return cortex_a_poll(target);
236 }
237
238 static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force)
239 {
240 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
241 * Writes final value of DSCR into *dscr. Pass force to force always
242 * reading DSCR at least once. */
243 struct armv7a_common *armv7a = target_to_armv7a(target);
244 int64_t then = timeval_ms();
245 while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
246 force = false;
247 int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
248 armv7a->debug_base + CPUDBG_DSCR, dscr);
249 if (retval != ERROR_OK) {
250 LOG_ERROR("Could not read DSCR register");
251 return retval;
252 }
253 if (timeval_ms() > then + 1000) {
254 LOG_ERROR("Timeout waiting for InstrCompl=1");
255 return ERROR_FAIL;
256 }
257 }
258 return ERROR_OK;
259 }
260
261 /* To reduce needless round-trips, pass in a pointer to the current
262 * DSCR value. Initialize it to zero if you just need to know the
263 * value on return from this function; or DSCR_INSTR_COMP if you
264 * happen to know that no instruction is pending.
265 */
266 static int cortex_a_exec_opcode(struct target *target,
267 uint32_t opcode, uint32_t *dscr_p)
268 {
269 uint32_t dscr;
270 int retval;
271 struct armv7a_common *armv7a = target_to_armv7a(target);
272
273 dscr = dscr_p ? *dscr_p : 0;
274
275 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
276
277 /* Wait for InstrCompl bit to be set */
278 retval = cortex_a_wait_instrcmpl(target, dscr_p, false);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = mem_ap_write_u32(armv7a->debug_ap,
283 armv7a->debug_base + CPUDBG_ITR, opcode);
284 if (retval != ERROR_OK)
285 return retval;
286
287 int64_t then = timeval_ms();
288 do {
289 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
290 armv7a->debug_base + CPUDBG_DSCR, &dscr);
291 if (retval != ERROR_OK) {
292 LOG_ERROR("Could not read DSCR register");
293 return retval;
294 }
295 if (timeval_ms() > then + 1000) {
296 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
297 return ERROR_FAIL;
298 }
299 } while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
300
301 if (dscr_p)
302 *dscr_p = dscr;
303
304 return retval;
305 }
306
307 /**************************************************************************
308 Read core register with very few exec_opcode, fast but needs work_area.
309 This can cause problems with MMU active.
310 **************************************************************************/
311 static int cortex_a_read_regs_through_mem(struct target *target, uint32_t address,
312 uint32_t *regfile)
313 {
314 int retval = ERROR_OK;
315 struct armv7a_common *armv7a = target_to_armv7a(target);
316
317 retval = cortex_a_dap_read_coreregister_u32(target, regfile, 0);
318 if (retval != ERROR_OK)
319 return retval;
320 retval = cortex_a_dap_write_coreregister_u32(target, address, 0);
321 if (retval != ERROR_OK)
322 return retval;
323 retval = cortex_a_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
324 if (retval != ERROR_OK)
325 return retval;
326
327 retval = mem_ap_read_buf(armv7a->memory_ap,
328 (uint8_t *)(&regfile[1]), 4, 15, address);
329
330 return retval;
331 }
332
333 static int cortex_a_dap_read_coreregister_u32(struct target *target,
334 uint32_t *value, int regnum)
335 {
336 int retval = ERROR_OK;
337 uint8_t reg = regnum&0xFF;
338 uint32_t dscr = 0;
339 struct armv7a_common *armv7a = target_to_armv7a(target);
340
341 if (reg > 17)
342 return retval;
343
344 if (reg < 15) {
345 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
346 retval = cortex_a_exec_opcode(target,
347 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
348 &dscr);
349 if (retval != ERROR_OK)
350 return retval;
351 } else if (reg == 15) {
352 /* "MOV r0, r15"; then move r0 to DCCTX */
353 retval = cortex_a_exec_opcode(target, 0xE1A0000F, &dscr);
354 if (retval != ERROR_OK)
355 return retval;
356 retval = cortex_a_exec_opcode(target,
357 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
358 &dscr);
359 if (retval != ERROR_OK)
360 return retval;
361 } else {
362 /* "MRS r0, CPSR" or "MRS r0, SPSR"
363 * then move r0 to DCCTX
364 */
365 retval = cortex_a_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
366 if (retval != ERROR_OK)
367 return retval;
368 retval = cortex_a_exec_opcode(target,
369 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
370 &dscr);
371 if (retval != ERROR_OK)
372 return retval;
373 }
374
375 /* Wait for DTRRXfull then read DTRRTX */
376 int64_t then = timeval_ms();
377 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
378 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
379 armv7a->debug_base + CPUDBG_DSCR, &dscr);
380 if (retval != ERROR_OK)
381 return retval;
382 if (timeval_ms() > then + 1000) {
383 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
384 return ERROR_FAIL;
385 }
386 }
387
388 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
389 armv7a->debug_base + CPUDBG_DTRTX, value);
390 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
391
392 return retval;
393 }
394
395 static int cortex_a_dap_write_coreregister_u32(struct target *target,
396 uint32_t value, int regnum)
397 {
398 int retval = ERROR_OK;
399 uint8_t Rd = regnum&0xFF;
400 uint32_t dscr;
401 struct armv7a_common *armv7a = target_to_armv7a(target);
402
403 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
404
405 /* Check that DCCRX is not full */
406 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
407 armv7a->debug_base + CPUDBG_DSCR, &dscr);
408 if (retval != ERROR_OK)
409 return retval;
410 if (dscr & DSCR_DTR_RX_FULL) {
411 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
412 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
413 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
414 &dscr);
415 if (retval != ERROR_OK)
416 return retval;
417 }
418
419 if (Rd > 17)
420 return retval;
421
422 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
423 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
424 retval = mem_ap_write_u32(armv7a->debug_ap,
425 armv7a->debug_base + CPUDBG_DTRRX, value);
426 if (retval != ERROR_OK)
427 return retval;
428
429 if (Rd < 15) {
430 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
431 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
432 &dscr);
433
434 if (retval != ERROR_OK)
435 return retval;
436 } else if (Rd == 15) {
437 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
438 * then "mov r15, r0"
439 */
440 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
441 &dscr);
442 if (retval != ERROR_OK)
443 return retval;
444 retval = cortex_a_exec_opcode(target, 0xE1A0F000, &dscr);
445 if (retval != ERROR_OK)
446 return retval;
447 } else {
448 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
449 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
450 */
451 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
452 &dscr);
453 if (retval != ERROR_OK)
454 return retval;
455 retval = cortex_a_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
456 &dscr);
457 if (retval != ERROR_OK)
458 return retval;
459
460 /* "Prefetch flush" after modifying execution status in CPSR */
461 if (Rd == 16) {
462 retval = cortex_a_exec_opcode(target,
463 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
464 &dscr);
465 if (retval != ERROR_OK)
466 return retval;
467 }
468 }
469
470 return retval;
471 }
472
473 /* Write to memory mapped registers directly with no cache or mmu handling */
474 static int cortex_a_dap_write_memap_register_u32(struct target *target,
475 uint32_t address,
476 uint32_t value)
477 {
478 int retval;
479 struct armv7a_common *armv7a = target_to_armv7a(target);
480
481 retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
482
483 return retval;
484 }
485
486 /*
487 * Cortex-A implementation of Debug Programmer's Model
488 *
489 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
490 * so there's no need to poll for it before executing an instruction.
491 *
492 * NOTE that in several of these cases the "stall" mode might be useful.
493 * It'd let us queue a few operations together... prepare/finish might
494 * be the places to enable/disable that mode.
495 */
496
497 static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
498 {
499 return container_of(dpm, struct cortex_a_common, armv7a_common.dpm);
500 }
501
502 static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
503 {
504 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
505 return mem_ap_write_u32(a->armv7a_common.debug_ap,
506 a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
507 }
508
509 static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
510 uint32_t *dscr_p)
511 {
512 uint32_t dscr = DSCR_INSTR_COMP;
513 int retval;
514
515 if (dscr_p)
516 dscr = *dscr_p;
517
518 /* Wait for DTRRXfull */
519 int64_t then = timeval_ms();
520 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
521 retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
522 a->armv7a_common.debug_base + CPUDBG_DSCR,
523 &dscr);
524 if (retval != ERROR_OK)
525 return retval;
526 if (timeval_ms() > then + 1000) {
527 LOG_ERROR("Timeout waiting for read dcc");
528 return ERROR_FAIL;
529 }
530 }
531
532 retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
533 a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
534 if (retval != ERROR_OK)
535 return retval;
536 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
537
538 if (dscr_p)
539 *dscr_p = dscr;
540
541 return retval;
542 }
543
544 static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
545 {
546 struct cortex_a_common *a = dpm_to_a(dpm);
547 uint32_t dscr;
548 int retval;
549
550 /* set up invariant: INSTR_COMP is set after ever DPM operation */
551 int64_t then = timeval_ms();
552 for (;; ) {
553 retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
554 a->armv7a_common.debug_base + CPUDBG_DSCR,
555 &dscr);
556 if (retval != ERROR_OK)
557 return retval;
558 if ((dscr & DSCR_INSTR_COMP) != 0)
559 break;
560 if (timeval_ms() > then + 1000) {
561 LOG_ERROR("Timeout waiting for dpm prepare");
562 return ERROR_FAIL;
563 }
564 }
565
566 /* this "should never happen" ... */
567 if (dscr & DSCR_DTR_RX_FULL) {
568 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
569 /* Clear DCCRX */
570 retval = cortex_a_exec_opcode(
571 a->armv7a_common.arm.target,
572 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
573 &dscr);
574 if (retval != ERROR_OK)
575 return retval;
576 }
577
578 return retval;
579 }
580
581 static int cortex_a_dpm_finish(struct arm_dpm *dpm)
582 {
583 /* REVISIT what could be done here? */
584 return ERROR_OK;
585 }
586
587 static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm,
588 uint32_t opcode, uint32_t data)
589 {
590 struct cortex_a_common *a = dpm_to_a(dpm);
591 int retval;
592 uint32_t dscr = DSCR_INSTR_COMP;
593
594 retval = cortex_a_write_dcc(a, data);
595 if (retval != ERROR_OK)
596 return retval;
597
598 return cortex_a_exec_opcode(
599 a->armv7a_common.arm.target,
600 opcode,
601 &dscr);
602 }
603
604 static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
605 uint32_t opcode, uint32_t data)
606 {
607 struct cortex_a_common *a = dpm_to_a(dpm);
608 uint32_t dscr = DSCR_INSTR_COMP;
609 int retval;
610
611 retval = cortex_a_write_dcc(a, data);
612 if (retval != ERROR_OK)
613 return retval;
614
615 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
616 retval = cortex_a_exec_opcode(
617 a->armv7a_common.arm.target,
618 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
619 &dscr);
620 if (retval != ERROR_OK)
621 return retval;
622
623 /* then the opcode, taking data from R0 */
624 retval = cortex_a_exec_opcode(
625 a->armv7a_common.arm.target,
626 opcode,
627 &dscr);
628
629 return retval;
630 }
631
632 static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
633 {
634 struct target *target = dpm->arm->target;
635 uint32_t dscr = DSCR_INSTR_COMP;
636
637 /* "Prefetch flush" after modifying execution status in CPSR */
638 return cortex_a_exec_opcode(target,
639 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
640 &dscr);
641 }
642
643 static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm,
644 uint32_t opcode, uint32_t *data)
645 {
646 struct cortex_a_common *a = dpm_to_a(dpm);
647 int retval;
648 uint32_t dscr = DSCR_INSTR_COMP;
649
650 /* the opcode, writing data to DCC */
651 retval = cortex_a_exec_opcode(
652 a->armv7a_common.arm.target,
653 opcode,
654 &dscr);
655 if (retval != ERROR_OK)
656 return retval;
657
658 return cortex_a_read_dcc(a, data, &dscr);
659 }
660
661
662 static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
663 uint32_t opcode, uint32_t *data)
664 {
665 struct cortex_a_common *a = dpm_to_a(dpm);
666 uint32_t dscr = DSCR_INSTR_COMP;
667 int retval;
668
669 /* the opcode, writing data to R0 */
670 retval = cortex_a_exec_opcode(
671 a->armv7a_common.arm.target,
672 opcode,
673 &dscr);
674 if (retval != ERROR_OK)
675 return retval;
676
677 /* write R0 to DCC */
678 retval = cortex_a_exec_opcode(
679 a->armv7a_common.arm.target,
680 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
681 &dscr);
682 if (retval != ERROR_OK)
683 return retval;
684
685 return cortex_a_read_dcc(a, data, &dscr);
686 }
687
688 static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
689 uint32_t addr, uint32_t control)
690 {
691 struct cortex_a_common *a = dpm_to_a(dpm);
692 uint32_t vr = a->armv7a_common.debug_base;
693 uint32_t cr = a->armv7a_common.debug_base;
694 int retval;
695
696 switch (index_t) {
697 case 0 ... 15: /* breakpoints */
698 vr += CPUDBG_BVR_BASE;
699 cr += CPUDBG_BCR_BASE;
700 break;
701 case 16 ... 31: /* watchpoints */
702 vr += CPUDBG_WVR_BASE;
703 cr += CPUDBG_WCR_BASE;
704 index_t -= 16;
705 break;
706 default:
707 return ERROR_FAIL;
708 }
709 vr += 4 * index_t;
710 cr += 4 * index_t;
711
712 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
713 (unsigned) vr, (unsigned) cr);
714
715 retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
716 vr, addr);
717 if (retval != ERROR_OK)
718 return retval;
719 retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
720 cr, control);
721 return retval;
722 }
723
724 static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
725 {
726 struct cortex_a_common *a = dpm_to_a(dpm);
727 uint32_t cr;
728
729 switch (index_t) {
730 case 0 ... 15:
731 cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE;
732 break;
733 case 16 ... 31:
734 cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE;
735 index_t -= 16;
736 break;
737 default:
738 return ERROR_FAIL;
739 }
740 cr += 4 * index_t;
741
742 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
743
744 /* clear control register */
745 return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
746 }
747
748 static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
749 {
750 struct arm_dpm *dpm = &a->armv7a_common.dpm;
751 int retval;
752
753 dpm->arm = &a->armv7a_common.arm;
754 dpm->didr = didr;
755
756 dpm->prepare = cortex_a_dpm_prepare;
757 dpm->finish = cortex_a_dpm_finish;
758
759 dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
760 dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
761 dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
762
763 dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
764 dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
765
766 dpm->bpwp_enable = cortex_a_bpwp_enable;
767 dpm->bpwp_disable = cortex_a_bpwp_disable;
768
769 retval = arm_dpm_setup(dpm);
770 if (retval == ERROR_OK)
771 retval = arm_dpm_initialize(dpm);
772
773 return retval;
774 }
775 static struct target *get_cortex_a(struct target *target, int32_t coreid)
776 {
777 struct target_list *head;
778 struct target *curr;
779
780 head = target->head;
781 while (head != (struct target_list *)NULL) {
782 curr = head->target;
783 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
784 return curr;
785 head = head->next;
786 }
787 return target;
788 }
789 static int cortex_a_halt(struct target *target);
790
791 static int cortex_a_halt_smp(struct target *target)
792 {
793 int retval = 0;
794 struct target_list *head;
795 struct target *curr;
796 head = target->head;
797 while (head != (struct target_list *)NULL) {
798 curr = head->target;
799 if ((curr != target) && (curr->state != TARGET_HALTED)
800 && target_was_examined(curr))
801 retval += cortex_a_halt(curr);
802 head = head->next;
803 }
804 return retval;
805 }
806
807 static int update_halt_gdb(struct target *target)
808 {
809 int retval = 0;
810 if (target->gdb_service && target->gdb_service->core[0] == -1) {
811 target->gdb_service->target = target;
812 target->gdb_service->core[0] = target->coreid;
813 retval += cortex_a_halt_smp(target);
814 }
815 return retval;
816 }
817
818 /*
819 * Cortex-A Run control
820 */
821
822 static int cortex_a_poll(struct target *target)
823 {
824 int retval = ERROR_OK;
825 uint32_t dscr;
826 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
827 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
828 enum target_state prev_target_state = target->state;
829 /* toggle to another core is done by gdb as follow */
830 /* maint packet J core_id */
831 /* continue */
832 /* the next polling trigger an halt event sent to gdb */
833 if ((target->state == TARGET_HALTED) && (target->smp) &&
834 (target->gdb_service) &&
835 (target->gdb_service->target == NULL)) {
836 target->gdb_service->target =
837 get_cortex_a(target, target->gdb_service->core[1]);
838 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
839 return retval;
840 }
841 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
842 armv7a->debug_base + CPUDBG_DSCR, &dscr);
843 if (retval != ERROR_OK)
844 return retval;
845 cortex_a->cpudbg_dscr = dscr;
846
847 if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
848 if (prev_target_state != TARGET_HALTED) {
849 /* We have a halting debug event */
850 LOG_DEBUG("Target halted");
851 target->state = TARGET_HALTED;
852 if ((prev_target_state == TARGET_RUNNING)
853 || (prev_target_state == TARGET_UNKNOWN)
854 || (prev_target_state == TARGET_RESET)) {
855 retval = cortex_a_debug_entry(target);
856 if (retval != ERROR_OK)
857 return retval;
858 if (target->smp) {
859 retval = update_halt_gdb(target);
860 if (retval != ERROR_OK)
861 return retval;
862 }
863
864 if (arm_semihosting(target, &retval) != 0)
865 return retval;
866
867 target_call_event_callbacks(target,
868 TARGET_EVENT_HALTED);
869 }
870 if (prev_target_state == TARGET_DEBUG_RUNNING) {
871 LOG_DEBUG(" ");
872
873 retval = cortex_a_debug_entry(target);
874 if (retval != ERROR_OK)
875 return retval;
876 if (target->smp) {
877 retval = update_halt_gdb(target);
878 if (retval != ERROR_OK)
879 return retval;
880 }
881
882 target_call_event_callbacks(target,
883 TARGET_EVENT_DEBUG_HALTED);
884 }
885 }
886 } else
887 target->state = TARGET_RUNNING;
888
889 return retval;
890 }
891
892 static int cortex_a_halt(struct target *target)
893 {
894 int retval = ERROR_OK;
895 uint32_t dscr;
896 struct armv7a_common *armv7a = target_to_armv7a(target);
897
898 /*
899 * Tell the core to be halted by writing DRCR with 0x1
900 * and then wait for the core to be halted.
901 */
902 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
903 armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
904 if (retval != ERROR_OK)
905 return retval;
906
907 /*
908 * enter halting debug mode
909 */
910 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
911 armv7a->debug_base + CPUDBG_DSCR, &dscr);
912 if (retval != ERROR_OK)
913 return retval;
914
915 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
916 armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
917 if (retval != ERROR_OK)
918 return retval;
919
920 int64_t then = timeval_ms();
921 for (;; ) {
922 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
923 armv7a->debug_base + CPUDBG_DSCR, &dscr);
924 if (retval != ERROR_OK)
925 return retval;
926 if ((dscr & DSCR_CORE_HALTED) != 0)
927 break;
928 if (timeval_ms() > then + 1000) {
929 LOG_ERROR("Timeout waiting for halt");
930 return ERROR_FAIL;
931 }
932 }
933
934 target->debug_reason = DBG_REASON_DBGRQ;
935
936 return ERROR_OK;
937 }
938
939 static int cortex_a_internal_restore(struct target *target, int current,
940 target_addr_t *address, int handle_breakpoints, int debug_execution)
941 {
942 struct armv7a_common *armv7a = target_to_armv7a(target);
943 struct arm *arm = &armv7a->arm;
944 int retval;
945 uint32_t resume_pc;
946
947 if (!debug_execution)
948 target_free_all_working_areas(target);
949
950 #if 0
951 if (debug_execution) {
952 /* Disable interrupts */
953 /* We disable interrupts in the PRIMASK register instead of
954 * masking with C_MASKINTS,
955 * This is probably the same issue as Cortex-M3 Errata 377493:
956 * C_MASKINTS in parallel with disabled interrupts can cause
957 * local faults to not be taken. */
958 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
959 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
960 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
961
962 /* Make sure we are in Thumb mode */
963 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
964 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
965 32) | (1 << 24));
966 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
967 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
968 }
969 #endif
970
971 /* current = 1: continue on current pc, otherwise continue at <address> */
972 resume_pc = buf_get_u32(arm->pc->value, 0, 32);
973 if (!current)
974 resume_pc = *address;
975 else
976 *address = resume_pc;
977
978 /* Make sure that the Armv7 gdb thumb fixups does not
979 * kill the return address
980 */
981 switch (arm->core_state) {
982 case ARM_STATE_ARM:
983 resume_pc &= 0xFFFFFFFC;
984 break;
985 case ARM_STATE_THUMB:
986 case ARM_STATE_THUMB_EE:
987 /* When the return address is loaded into PC
988 * bit 0 must be 1 to stay in Thumb state
989 */
990 resume_pc |= 0x1;
991 break;
992 case ARM_STATE_JAZELLE:
993 LOG_ERROR("How do I resume into Jazelle state??");
994 return ERROR_FAIL;
995 case ARM_STATE_AARCH64:
996 LOG_ERROR("Shoudn't be in AARCH64 state");
997 return ERROR_FAIL;
998 }
999 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
1000 buf_set_u32(arm->pc->value, 0, 32, resume_pc);
1001 arm->pc->dirty = 1;
1002 arm->pc->valid = 1;
1003
1004 /* restore dpm_mode at system halt */
1005 dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
1006 /* called it now before restoring context because it uses cpu
1007 * register r0 for restoring cp15 control register */
1008 retval = cortex_a_restore_cp15_control_reg(target);
1009 if (retval != ERROR_OK)
1010 return retval;
1011 retval = cortex_a_restore_context(target, handle_breakpoints);
1012 if (retval != ERROR_OK)
1013 return retval;
1014 target->debug_reason = DBG_REASON_NOTHALTED;
1015 target->state = TARGET_RUNNING;
1016
1017 /* registers are now invalid */
1018 register_cache_invalidate(arm->core_cache);
1019
1020 #if 0
1021 /* the front-end may request us not to handle breakpoints */
1022 if (handle_breakpoints) {
1023 /* Single step past breakpoint at current address */
1024 breakpoint = breakpoint_find(target, resume_pc);
1025 if (breakpoint) {
1026 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1027 cortex_m3_unset_breakpoint(target, breakpoint);
1028 cortex_m3_single_step_core(target);
1029 cortex_m3_set_breakpoint(target, breakpoint);
1030 }
1031 }
1032
1033 #endif
1034 return retval;
1035 }
1036
1037 static int cortex_a_internal_restart(struct target *target)
1038 {
1039 struct armv7a_common *armv7a = target_to_armv7a(target);
1040 struct arm *arm = &armv7a->arm;
1041 int retval;
1042 uint32_t dscr;
1043 /*
1044 * * Restart core and wait for it to be started. Clear ITRen and sticky
1045 * * exception flags: see ARMv7 ARM, C5.9.
1046 *
1047 * REVISIT: for single stepping, we probably want to
1048 * disable IRQs by default, with optional override...
1049 */
1050
1051 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1052 armv7a->debug_base + CPUDBG_DSCR, &dscr);
1053 if (retval != ERROR_OK)
1054 return retval;
1055
1056 if ((dscr & DSCR_INSTR_COMP) == 0)
1057 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1058
1059 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1060 armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
1061 if (retval != ERROR_OK)
1062 return retval;
1063
1064 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1065 armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
1066 DRCR_CLEAR_EXCEPTIONS);
1067 if (retval != ERROR_OK)
1068 return retval;
1069
1070 int64_t then = timeval_ms();
1071 for (;; ) {
1072 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1073 armv7a->debug_base + CPUDBG_DSCR, &dscr);
1074 if (retval != ERROR_OK)
1075 return retval;
1076 if ((dscr & DSCR_CORE_RESTARTED) != 0)
1077 break;
1078 if (timeval_ms() > then + 1000) {
1079 LOG_ERROR("Timeout waiting for resume");
1080 return ERROR_FAIL;
1081 }
1082 }
1083
1084 target->debug_reason = DBG_REASON_NOTHALTED;
1085 target->state = TARGET_RUNNING;
1086
1087 /* registers are now invalid */
1088 register_cache_invalidate(arm->core_cache);
1089
1090 return ERROR_OK;
1091 }
1092
1093 static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
1094 {
1095 int retval = 0;
1096 struct target_list *head;
1097 struct target *curr;
1098 target_addr_t address;
1099 head = target->head;
1100 while (head != (struct target_list *)NULL) {
1101 curr = head->target;
1102 if ((curr != target) && (curr->state != TARGET_RUNNING)
1103 && target_was_examined(curr)) {
1104 /* resume current address , not in step mode */
1105 retval += cortex_a_internal_restore(curr, 1, &address,
1106 handle_breakpoints, 0);
1107 retval += cortex_a_internal_restart(curr);
1108 }
1109 head = head->next;
1110
1111 }
1112 return retval;
1113 }
1114
1115 static int cortex_a_resume(struct target *target, int current,
1116 target_addr_t address, int handle_breakpoints, int debug_execution)
1117 {
1118 int retval = 0;
1119 /* dummy resume for smp toggle in order to reduce gdb impact */
1120 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
1121 /* simulate a start and halt of target */
1122 target->gdb_service->target = NULL;
1123 target->gdb_service->core[0] = target->gdb_service->core[1];
1124 /* fake resume at next poll we play the target core[1], see poll*/
1125 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1126 return 0;
1127 }
1128 cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
1129 if (target->smp) {
1130 target->gdb_service->core[0] = -1;
1131 retval = cortex_a_restore_smp(target, handle_breakpoints);
1132 if (retval != ERROR_OK)
1133 return retval;
1134 }
1135 cortex_a_internal_restart(target);
1136
1137 if (!debug_execution) {
1138 target->state = TARGET_RUNNING;
1139 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1140 LOG_DEBUG("target resumed at " TARGET_ADDR_FMT, address);
1141 } else {
1142 target->state = TARGET_DEBUG_RUNNING;
1143 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1144 LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT, address);
1145 }
1146
1147 return ERROR_OK;
1148 }
1149
1150 static int cortex_a_debug_entry(struct target *target)
1151 {
1152 int i;
1153 uint32_t regfile[16], cpsr, spsr, dscr;
1154 int retval = ERROR_OK;
1155 struct working_area *regfile_working_area = NULL;
1156 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1157 struct armv7a_common *armv7a = target_to_armv7a(target);
1158 struct arm *arm = &armv7a->arm;
1159 struct reg *reg;
1160
1161 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
1162
1163 /* REVISIT surely we should not re-read DSCR !! */
1164 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1165 armv7a->debug_base + CPUDBG_DSCR, &dscr);
1166 if (retval != ERROR_OK)
1167 return retval;
1168
1169 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1170 * imprecise data aborts get discarded by issuing a Data
1171 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1172 */
1173
1174 /* Enable the ITR execution once we are in debug mode */
1175 dscr |= DSCR_ITR_EN;
1176 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1177 armv7a->debug_base + CPUDBG_DSCR, dscr);
1178 if (retval != ERROR_OK)
1179 return retval;
1180
1181 /* Examine debug reason */
1182 arm_dpm_report_dscr(&armv7a->dpm, cortex_a->cpudbg_dscr);
1183
1184 /* save address of instruction that triggered the watchpoint? */
1185 if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1186 uint32_t wfar;
1187
1188 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1189 armv7a->debug_base + CPUDBG_WFAR,
1190 &wfar);
1191 if (retval != ERROR_OK)
1192 return retval;
1193 arm_dpm_report_wfar(&armv7a->dpm, wfar);
1194 }
1195
1196 /* REVISIT fast_reg_read is never set ... */
1197
1198 /* Examine target state and mode */
1199 if (cortex_a->fast_reg_read)
1200 target_alloc_working_area(target, 64, &regfile_working_area);
1201
1202
1203 /* First load register acessible through core debug port*/
1204 if (!regfile_working_area)
1205 retval = arm_dpm_read_current_registers(&armv7a->dpm);
1206 else {
1207 retval = cortex_a_read_regs_through_mem(target,
1208 regfile_working_area->address, regfile);
1209
1210 target_free_working_area(target, regfile_working_area);
1211 if (retval != ERROR_OK)
1212 return retval;
1213
1214 /* read Current PSR */
1215 retval = cortex_a_dap_read_coreregister_u32(target, &cpsr, 16);
1216 /* store current cpsr */
1217 if (retval != ERROR_OK)
1218 return retval;
1219
1220 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
1221
1222 arm_set_cpsr(arm, cpsr);
1223
1224 /* update cache */
1225 for (i = 0; i <= ARM_PC; i++) {
1226 reg = arm_reg_current(arm, i);
1227
1228 buf_set_u32(reg->value, 0, 32, regfile[i]);
1229 reg->valid = 1;
1230 reg->dirty = 0;
1231 }
1232
1233 /* Fixup PC Resume Address */
1234 if (cpsr & (1 << 5)) {
1235 /* T bit set for Thumb or ThumbEE state */
1236 regfile[ARM_PC] -= 4;
1237 } else {
1238 /* ARM state */
1239 regfile[ARM_PC] -= 8;
1240 }
1241
1242 reg = arm->pc;
1243 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
1244 reg->dirty = reg->valid;
1245 }
1246
1247 if (arm->spsr) {
1248 /* read Saved PSR */
1249 retval = cortex_a_dap_read_coreregister_u32(target, &spsr, 17);
1250 /* store current spsr */
1251 if (retval != ERROR_OK)
1252 return retval;
1253
1254 reg = arm->spsr;
1255 buf_set_u32(reg->value, 0, 32, spsr);
1256 reg->valid = 1;
1257 reg->dirty = 0;
1258 }
1259
1260 #if 0
1261 /* TODO, Move this */
1262 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
1263 cortex_a_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
1264 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
1265
1266 cortex_a_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
1267 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
1268
1269 cortex_a_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
1270 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
1271 #endif
1272
1273 /* Are we in an exception handler */
1274 /* armv4_5->exception_number = 0; */
1275 if (armv7a->post_debug_entry) {
1276 retval = armv7a->post_debug_entry(target);
1277 if (retval != ERROR_OK)
1278 return retval;
1279 }
1280
1281 return retval;
1282 }
1283
1284 static int cortex_a_post_debug_entry(struct target *target)
1285 {
1286 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1287 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1288 int retval;
1289
1290 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1291 retval = armv7a->arm.mrc(target, 15,
1292 0, 0, /* op1, op2 */
1293 1, 0, /* CRn, CRm */
1294 &cortex_a->cp15_control_reg);
1295 if (retval != ERROR_OK)
1296 return retval;
1297 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
1298 cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
1299
1300 if (!armv7a->is_armv7r)
1301 armv7a_read_ttbcr(target);
1302
1303 if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
1304 armv7a_identify_cache(target);
1305
1306 if (armv7a->is_armv7r) {
1307 armv7a->armv7a_mmu.mmu_enabled = 0;
1308 } else {
1309 armv7a->armv7a_mmu.mmu_enabled =
1310 (cortex_a->cp15_control_reg & 0x1U) ? 1 : 0;
1311 }
1312 armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
1313 (cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
1314 armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled =
1315 (cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
1316 cortex_a->curr_mode = armv7a->arm.core_mode;
1317
1318 /* switch to SVC mode to read DACR */
1319 dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
1320 armv7a->arm.mrc(target, 15,
1321 0, 0, 3, 0,
1322 &cortex_a->cp15_dacr_reg);
1323
1324 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
1325 cortex_a->cp15_dacr_reg);
1326
1327 dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
1328 return ERROR_OK;
1329 }
1330
1331 int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
1332 {
1333 struct armv7a_common *armv7a = target_to_armv7a(target);
1334 uint32_t dscr;
1335
1336 /* Read DSCR */
1337 int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1338 armv7a->debug_base + CPUDBG_DSCR, &dscr);
1339 if (ERROR_OK != retval)
1340 return retval;
1341
1342 /* clear bitfield */
1343 dscr &= ~bit_mask;
1344 /* put new value */
1345 dscr |= value & bit_mask;
1346
1347 /* write new DSCR */
1348 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1349 armv7a->debug_base + CPUDBG_DSCR, dscr);
1350 return retval;
1351 }
1352
1353 static int cortex_a_step(struct target *target, int current, target_addr_t address,
1354 int handle_breakpoints)
1355 {
1356 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1357 struct armv7a_common *armv7a = target_to_armv7a(target);
1358 struct arm *arm = &armv7a->arm;
1359 struct breakpoint *breakpoint = NULL;
1360 struct breakpoint stepbreakpoint;
1361 struct reg *r;
1362 int retval;
1363
1364 if (target->state != TARGET_HALTED) {
1365 LOG_WARNING("target not halted");
1366 return ERROR_TARGET_NOT_HALTED;
1367 }
1368
1369 /* current = 1: continue on current pc, otherwise continue at <address> */
1370 r = arm->pc;
1371 if (!current)
1372 buf_set_u32(r->value, 0, 32, address);
1373 else
1374 address = buf_get_u32(r->value, 0, 32);
1375
1376 /* The front-end may request us not to handle breakpoints.
1377 * But since Cortex-A uses breakpoint for single step,
1378 * we MUST handle breakpoints.
1379 */
1380 handle_breakpoints = 1;
1381 if (handle_breakpoints) {
1382 breakpoint = breakpoint_find(target, address);
1383 if (breakpoint)
1384 cortex_a_unset_breakpoint(target, breakpoint);
1385 }
1386
1387 /* Setup single step breakpoint */
1388 stepbreakpoint.address = address;
1389 stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB)
1390 ? 2 : 4;
1391 stepbreakpoint.type = BKPT_HARD;
1392 stepbreakpoint.set = 0;
1393
1394 /* Disable interrupts during single step if requested */
1395 if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
1396 retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, DSCR_INT_DIS);
1397 if (ERROR_OK != retval)
1398 return retval;
1399 }
1400
1401 /* Break on IVA mismatch */
1402 cortex_a_set_breakpoint(target, &stepbreakpoint, 0x04);
1403
1404 target->debug_reason = DBG_REASON_SINGLESTEP;
1405
1406 retval = cortex_a_resume(target, 1, address, 0, 0);
1407 if (retval != ERROR_OK)
1408 return retval;
1409
1410 int64_t then = timeval_ms();
1411 while (target->state != TARGET_HALTED) {
1412 retval = cortex_a_poll(target);
1413 if (retval != ERROR_OK)
1414 return retval;
1415 if (timeval_ms() > then + 1000) {
1416 LOG_ERROR("timeout waiting for target halt");
1417 return ERROR_FAIL;
1418 }
1419 }
1420
1421 cortex_a_unset_breakpoint(target, &stepbreakpoint);
1422
1423 /* Re-enable interrupts if they were disabled */
1424 if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
1425 retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, 0);
1426 if (ERROR_OK != retval)
1427 return retval;
1428 }
1429
1430
1431 target->debug_reason = DBG_REASON_BREAKPOINT;
1432
1433 if (breakpoint)
1434 cortex_a_set_breakpoint(target, breakpoint, 0);
1435
1436 if (target->state != TARGET_HALTED)
1437 LOG_DEBUG("target stepped");
1438
1439 return ERROR_OK;
1440 }
1441
1442 static int cortex_a_restore_context(struct target *target, bool bpwp)
1443 {
1444 struct armv7a_common *armv7a = target_to_armv7a(target);
1445
1446 LOG_DEBUG(" ");
1447
1448 if (armv7a->pre_restore_context)
1449 armv7a->pre_restore_context(target);
1450
1451 return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
1452 }
1453
1454 /*
1455 * Cortex-A Breakpoint and watchpoint functions
1456 */
1457
1458 /* Setup hardware Breakpoint Register Pair */
1459 static int cortex_a_set_breakpoint(struct target *target,
1460 struct breakpoint *breakpoint, uint8_t matchmode)
1461 {
1462 int retval;
1463 int brp_i = 0;
1464 uint32_t control;
1465 uint8_t byte_addr_select = 0x0F;
1466 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1467 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1468 struct cortex_a_brp *brp_list = cortex_a->brp_list;
1469
1470 if (breakpoint->set) {
1471 LOG_WARNING("breakpoint already set");
1472 return ERROR_OK;
1473 }
1474
1475 if (breakpoint->type == BKPT_HARD) {
1476 while (brp_list[brp_i].used && (brp_i < cortex_a->brp_num))
1477 brp_i++;
1478 if (brp_i >= cortex_a->brp_num) {
1479 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1480 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1481 }
1482 breakpoint->set = brp_i + 1;
1483 if (breakpoint->length == 2)
1484 byte_addr_select = (3 << (breakpoint->address & 0x02));
1485 control = ((matchmode & 0x7) << 20)
1486 | (byte_addr_select << 5)
1487 | (3 << 1) | 1;
1488 brp_list[brp_i].used = 1;
1489 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1490 brp_list[brp_i].control = control;
1491 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1492 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1493 brp_list[brp_i].value);
1494 if (retval != ERROR_OK)
1495 return retval;
1496 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1497 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1498 brp_list[brp_i].control);
1499 if (retval != ERROR_OK)
1500 return retval;
1501 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1502 brp_list[brp_i].control,
1503 brp_list[brp_i].value);
1504 } else if (breakpoint->type == BKPT_SOFT) {
1505 uint8_t code[4];
1506 /* length == 2: Thumb breakpoint */
1507 if (breakpoint->length == 2)
1508 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1509 else
1510 /* length == 3: Thumb-2 breakpoint, actual encoding is
1511 * a regular Thumb BKPT instruction but we replace a
1512 * 32bit Thumb-2 instruction, so fix-up the breakpoint
1513 * length
1514 */
1515 if (breakpoint->length == 3) {
1516 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1517 breakpoint->length = 4;
1518 } else
1519 /* length == 4, normal ARM breakpoint */
1520 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1521
1522 retval = target_read_memory(target,
1523 breakpoint->address & 0xFFFFFFFE,
1524 breakpoint->length, 1,
1525 breakpoint->orig_instr);
1526 if (retval != ERROR_OK)
1527 return retval;
1528
1529 /* make sure data cache is cleaned & invalidated down to PoC */
1530 if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) {
1531 armv7a_cache_flush_virt(target, breakpoint->address,
1532 breakpoint->length);
1533 }
1534
1535 retval = target_write_memory(target,
1536 breakpoint->address & 0xFFFFFFFE,
1537 breakpoint->length, 1, code);
1538 if (retval != ERROR_OK)
1539 return retval;
1540
1541 /* update i-cache at breakpoint location */
1542 armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
1543 breakpoint->length);
1544 armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
1545 breakpoint->length);
1546
1547 breakpoint->set = 0x11; /* Any nice value but 0 */
1548 }
1549
1550 return ERROR_OK;
1551 }
1552
1553 static int cortex_a_set_context_breakpoint(struct target *target,
1554 struct breakpoint *breakpoint, uint8_t matchmode)
1555 {
1556 int retval = ERROR_FAIL;
1557 int brp_i = 0;
1558 uint32_t control;
1559 uint8_t byte_addr_select = 0x0F;
1560 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1561 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1562 struct cortex_a_brp *brp_list = cortex_a->brp_list;
1563
1564 if (breakpoint->set) {
1565 LOG_WARNING("breakpoint already set");
1566 return retval;
1567 }
1568 /*check available context BRPs*/
1569 while ((brp_list[brp_i].used ||
1570 (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a->brp_num))
1571 brp_i++;
1572
1573 if (brp_i >= cortex_a->brp_num) {
1574 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1575 return ERROR_FAIL;
1576 }
1577
1578 breakpoint->set = brp_i + 1;
1579 control = ((matchmode & 0x7) << 20)
1580 | (byte_addr_select << 5)
1581 | (3 << 1) | 1;
1582 brp_list[brp_i].used = 1;
1583 brp_list[brp_i].value = (breakpoint->asid);
1584 brp_list[brp_i].control = control;
1585 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1586 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1587 brp_list[brp_i].value);
1588 if (retval != ERROR_OK)
1589 return retval;
1590 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1591 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1592 brp_list[brp_i].control);
1593 if (retval != ERROR_OK)
1594 return retval;
1595 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1596 brp_list[brp_i].control,
1597 brp_list[brp_i].value);
1598 return ERROR_OK;
1599
1600 }
1601
1602 static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
1603 {
1604 int retval = ERROR_FAIL;
1605 int brp_1 = 0; /* holds the contextID pair */
1606 int brp_2 = 0; /* holds the IVA pair */
1607 uint32_t control_CTX, control_IVA;
1608 uint8_t CTX_byte_addr_select = 0x0F;
1609 uint8_t IVA_byte_addr_select = 0x0F;
1610 uint8_t CTX_machmode = 0x03;
1611 uint8_t IVA_machmode = 0x01;
1612 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1613 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1614 struct cortex_a_brp *brp_list = cortex_a->brp_list;
1615
1616 if (breakpoint->set) {
1617 LOG_WARNING("breakpoint already set");
1618 return retval;
1619 }
1620 /*check available context BRPs*/
1621 while ((brp_list[brp_1].used ||
1622 (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num))
1623 brp_1++;
1624
1625 printf("brp(CTX) found num: %d\n", brp_1);
1626 if (brp_1 >= cortex_a->brp_num) {
1627 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1628 return ERROR_FAIL;
1629 }
1630
1631 while ((brp_list[brp_2].used ||
1632 (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a->brp_num))
1633 brp_2++;
1634
1635 printf("brp(IVA) found num: %d\n", brp_2);
1636 if (brp_2 >= cortex_a->brp_num) {
1637 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1638 return ERROR_FAIL;
1639 }
1640
1641 breakpoint->set = brp_1 + 1;
1642 breakpoint->linked_BRP = brp_2;
1643 control_CTX = ((CTX_machmode & 0x7) << 20)
1644 | (brp_2 << 16)
1645 | (0 << 14)
1646 | (CTX_byte_addr_select << 5)
1647 | (3 << 1) | 1;
1648 brp_list[brp_1].used = 1;
1649 brp_list[brp_1].value = (breakpoint->asid);
1650 brp_list[brp_1].control = control_CTX;
1651 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1652 + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
1653 brp_list[brp_1].value);
1654 if (retval != ERROR_OK)
1655 return retval;
1656 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1657 + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
1658 brp_list[brp_1].control);
1659 if (retval != ERROR_OK)
1660 return retval;
1661
1662 control_IVA = ((IVA_machmode & 0x7) << 20)
1663 | (brp_1 << 16)
1664 | (IVA_byte_addr_select << 5)
1665 | (3 << 1) | 1;
1666 brp_list[brp_2].used = 1;
1667 brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
1668 brp_list[brp_2].control = control_IVA;
1669 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1670 + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
1671 brp_list[brp_2].value);
1672 if (retval != ERROR_OK)
1673 return retval;
1674 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1675 + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
1676 brp_list[brp_2].control);
1677 if (retval != ERROR_OK)
1678 return retval;
1679
1680 return ERROR_OK;
1681 }
1682
1683 static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1684 {
1685 int retval;
1686 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1687 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1688 struct cortex_a_brp *brp_list = cortex_a->brp_list;
1689
1690 if (!breakpoint->set) {
1691 LOG_WARNING("breakpoint not set");
1692 return ERROR_OK;
1693 }
1694
1695 if (breakpoint->type == BKPT_HARD) {
1696 if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1697 int brp_i = breakpoint->set - 1;
1698 int brp_j = breakpoint->linked_BRP;
1699 if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
1700 LOG_DEBUG("Invalid BRP number in breakpoint");
1701 return ERROR_OK;
1702 }
1703 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1704 brp_list[brp_i].control, brp_list[brp_i].value);
1705 brp_list[brp_i].used = 0;
1706 brp_list[brp_i].value = 0;
1707 brp_list[brp_i].control = 0;
1708 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1709 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1710 brp_list[brp_i].control);
1711 if (retval != ERROR_OK)
1712 return retval;
1713 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1714 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1715 brp_list[brp_i].value);
1716 if (retval != ERROR_OK)
1717 return retval;
1718 if ((brp_j < 0) || (brp_j >= cortex_a->brp_num)) {
1719 LOG_DEBUG("Invalid BRP number in breakpoint");
1720 return ERROR_OK;
1721 }
1722 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
1723 brp_list[brp_j].control, brp_list[brp_j].value);
1724 brp_list[brp_j].used = 0;
1725 brp_list[brp_j].value = 0;
1726 brp_list[brp_j].control = 0;
1727 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1728 + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn,
1729 brp_list[brp_j].control);
1730 if (retval != ERROR_OK)
1731 return retval;
1732 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1733 + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn,
1734 brp_list[brp_j].value);
1735 if (retval != ERROR_OK)
1736 return retval;
1737 breakpoint->linked_BRP = 0;
1738 breakpoint->set = 0;
1739 return ERROR_OK;
1740
1741 } else {
1742 int brp_i = breakpoint->set - 1;
1743 if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
1744 LOG_DEBUG("Invalid BRP number in breakpoint");
1745 return ERROR_OK;
1746 }
1747 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1748 brp_list[brp_i].control, brp_list[brp_i].value);
1749 brp_list[brp_i].used = 0;
1750 brp_list[brp_i].value = 0;
1751 brp_list[brp_i].control = 0;
1752 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1753 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1754 brp_list[brp_i].control);
1755 if (retval != ERROR_OK)
1756 return retval;
1757 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1758 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1759 brp_list[brp_i].value);
1760 if (retval != ERROR_OK)
1761 return retval;
1762 breakpoint->set = 0;
1763 return ERROR_OK;
1764 }
1765 } else {
1766
1767 /* make sure data cache is cleaned & invalidated down to PoC */
1768 if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) {
1769 armv7a_cache_flush_virt(target, breakpoint->address,
1770 breakpoint->length);
1771 }
1772
1773 /* restore original instruction (kept in target endianness) */
1774 if (breakpoint->length == 4) {
1775 retval = target_write_memory(target,
1776 breakpoint->address & 0xFFFFFFFE,
1777 4, 1, breakpoint->orig_instr);
1778 if (retval != ERROR_OK)
1779 return retval;
1780 } else {
1781 retval = target_write_memory(target,
1782 breakpoint->address & 0xFFFFFFFE,
1783 2, 1, breakpoint->orig_instr);
1784 if (retval != ERROR_OK)
1785 return retval;
1786 }
1787
1788 /* update i-cache at breakpoint location */
1789 armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
1790 breakpoint->length);
1791 armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
1792 breakpoint->length);
1793 }
1794 breakpoint->set = 0;
1795
1796 return ERROR_OK;
1797 }
1798
1799 static int cortex_a_add_breakpoint(struct target *target,
1800 struct breakpoint *breakpoint)
1801 {
1802 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1803
1804 if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1805 LOG_INFO("no hardware breakpoint available");
1806 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1807 }
1808
1809 if (breakpoint->type == BKPT_HARD)
1810 cortex_a->brp_num_available--;
1811
1812 return cortex_a_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1813 }
1814
1815 static int cortex_a_add_context_breakpoint(struct target *target,
1816 struct breakpoint *breakpoint)
1817 {
1818 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1819
1820 if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1821 LOG_INFO("no hardware breakpoint available");
1822 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1823 }
1824
1825 if (breakpoint->type == BKPT_HARD)
1826 cortex_a->brp_num_available--;
1827
1828 return cortex_a_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
1829 }
1830
1831 static int cortex_a_add_hybrid_breakpoint(struct target *target,
1832 struct breakpoint *breakpoint)
1833 {
1834 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1835
1836 if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1837 LOG_INFO("no hardware breakpoint available");
1838 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1839 }
1840
1841 if (breakpoint->type == BKPT_HARD)
1842 cortex_a->brp_num_available--;
1843
1844 return cortex_a_set_hybrid_breakpoint(target, breakpoint); /* ??? */
1845 }
1846
1847
1848 static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1849 {
1850 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1851
1852 #if 0
1853 /* It is perfectly possible to remove breakpoints while the target is running */
1854 if (target->state != TARGET_HALTED) {
1855 LOG_WARNING("target not halted");
1856 return ERROR_TARGET_NOT_HALTED;
1857 }
1858 #endif
1859
1860 if (breakpoint->set) {
1861 cortex_a_unset_breakpoint(target, breakpoint);
1862 if (breakpoint->type == BKPT_HARD)
1863 cortex_a->brp_num_available++;
1864 }
1865
1866
1867 return ERROR_OK;
1868 }
1869
1870 /*
1871 * Cortex-A Reset functions
1872 */
1873
1874 static int cortex_a_assert_reset(struct target *target)
1875 {
1876 struct armv7a_common *armv7a = target_to_armv7a(target);
1877
1878 LOG_DEBUG(" ");
1879
1880 /* FIXME when halt is requested, make it work somehow... */
1881
1882 /* This function can be called in "target not examined" state */
1883
1884 /* Issue some kind of warm reset. */
1885 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
1886 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1887 else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1888 /* REVISIT handle "pulls" cases, if there's
1889 * hardware that needs them to work.
1890 */
1891
1892 /*
1893 * FIXME: fix reset when transport is SWD. This is a temporary
1894 * work-around for release v0.10 that is not intended to stay!
1895 */
1896 if (transport_is_swd() ||
1897 (target->reset_halt && (jtag_get_reset_config() & RESET_SRST_NO_GATING)))
1898 jtag_add_reset(0, 1);
1899
1900 } else {
1901 LOG_ERROR("%s: how to reset?", target_name(target));
1902 return ERROR_FAIL;
1903 }
1904
1905 /* registers are now invalid */
1906 if (target_was_examined(target))
1907 register_cache_invalidate(armv7a->arm.core_cache);
1908
1909 target->state = TARGET_RESET;
1910
1911 return ERROR_OK;
1912 }
1913
1914 static int cortex_a_deassert_reset(struct target *target)
1915 {
1916 int retval;
1917
1918 LOG_DEBUG(" ");
1919
1920 /* be certain SRST is off */
1921 jtag_add_reset(0, 0);
1922
1923 if (target_was_examined(target)) {
1924 retval = cortex_a_poll(target);
1925 if (retval != ERROR_OK)
1926 return retval;
1927 }
1928
1929 if (target->reset_halt) {
1930 if (target->state != TARGET_HALTED) {
1931 LOG_WARNING("%s: ran after reset and before halt ...",
1932 target_name(target));
1933 if (target_was_examined(target)) {
1934 retval = target_halt(target);
1935 if (retval != ERROR_OK)
1936 return retval;
1937 } else
1938 target->state = TARGET_UNKNOWN;
1939 }
1940 }
1941
1942 return ERROR_OK;
1943 }
1944
1945 static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t *dscr)
1946 {
1947 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1948 * New desired mode must be in mode. Current value of DSCR must be in
1949 * *dscr, which is updated with new value.
1950 *
1951 * This function elides actually sending the mode-change over the debug
1952 * interface if the mode is already set as desired.
1953 */
1954 uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
1955 if (new_dscr != *dscr) {
1956 struct armv7a_common *armv7a = target_to_armv7a(target);
1957 int retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1958 armv7a->debug_base + CPUDBG_DSCR, new_dscr);
1959 if (retval == ERROR_OK)
1960 *dscr = new_dscr;
1961 return retval;
1962 } else {
1963 return ERROR_OK;
1964 }
1965 }
1966
1967 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
1968 uint32_t value, uint32_t *dscr)
1969 {
1970 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1971 struct armv7a_common *armv7a = target_to_armv7a(target);
1972 int64_t then = timeval_ms();
1973 int retval;
1974
1975 while ((*dscr & mask) != value) {
1976 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1977 armv7a->debug_base + CPUDBG_DSCR, dscr);
1978 if (retval != ERROR_OK)
1979 return retval;
1980 if (timeval_ms() > then + 1000) {
1981 LOG_ERROR("timeout waiting for DSCR bit change");
1982 return ERROR_FAIL;
1983 }
1984 }
1985 return ERROR_OK;
1986 }
1987
1988 static int cortex_a_read_copro(struct target *target, uint32_t opcode,
1989 uint32_t *data, uint32_t *dscr)
1990 {
1991 int retval;
1992 struct armv7a_common *armv7a = target_to_armv7a(target);
1993
1994 /* Move from coprocessor to R0. */
1995 retval = cortex_a_exec_opcode(target, opcode, dscr);
1996 if (retval != ERROR_OK)
1997 return retval;
1998
1999 /* Move from R0 to DTRTX. */
2000 retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr);
2001 if (retval != ERROR_OK)
2002 return retval;
2003
2004 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2005 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2006 * must also check TXfull_l). Most of the time this will be free
2007 * because TXfull_l will be set immediately and cached in dscr. */
2008 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRTX_FULL_LATCHED,
2009 DSCR_DTRTX_FULL_LATCHED, dscr);
2010 if (retval != ERROR_OK)
2011 return retval;
2012
2013 /* Read the value transferred to DTRTX. */
2014 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2015 armv7a->debug_base + CPUDBG_DTRTX, data);
2016 if (retval != ERROR_OK)
2017 return retval;
2018
2019 return ERROR_OK;
2020 }
2021
2022 static int cortex_a_read_dfar_dfsr(struct target *target, uint32_t *dfar,
2023 uint32_t *dfsr, uint32_t *dscr)
2024 {
2025 int retval;
2026
2027 if (dfar) {
2028 retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar, dscr);
2029 if (retval != ERROR_OK)
2030 return retval;
2031 }
2032
2033 if (dfsr) {
2034 retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr, dscr);
2035 if (retval != ERROR_OK)
2036 return retval;
2037 }
2038
2039 return ERROR_OK;
2040 }
2041
2042 static int cortex_a_write_copro(struct target *target, uint32_t opcode,
2043 uint32_t data, uint32_t *dscr)
2044 {
2045 int retval;
2046 struct armv7a_common *armv7a = target_to_armv7a(target);
2047
2048 /* Write the value into DTRRX. */
2049 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2050 armv7a->debug_base + CPUDBG_DTRRX, data);
2051 if (retval != ERROR_OK)
2052 return retval;
2053
2054 /* Move from DTRRX to R0. */
2055 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr);
2056 if (retval != ERROR_OK)
2057 return retval;
2058
2059 /* Move from R0 to coprocessor. */
2060 retval = cortex_a_exec_opcode(target, opcode, dscr);
2061 if (retval != ERROR_OK)
2062 return retval;
2063
2064 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2065 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2066 * check RXfull_l). Most of the time this will be free because RXfull_l
2067 * will be cleared immediately and cached in dscr. */
2068 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRRX_FULL_LATCHED, 0, dscr);
2069 if (retval != ERROR_OK)
2070 return retval;
2071
2072 return ERROR_OK;
2073 }
2074
2075 static int cortex_a_write_dfar_dfsr(struct target *target, uint32_t dfar,
2076 uint32_t dfsr, uint32_t *dscr)
2077 {
2078 int retval;
2079
2080 retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar, dscr);
2081 if (retval != ERROR_OK)
2082 return retval;
2083
2084 retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr, dscr);
2085 if (retval != ERROR_OK)
2086 return retval;
2087
2088 return ERROR_OK;
2089 }
2090
2091 static int cortex_a_dfsr_to_error_code(uint32_t dfsr)
2092 {
2093 uint32_t status, upper4;
2094
2095 if (dfsr & (1 << 9)) {
2096 /* LPAE format. */
2097 status = dfsr & 0x3f;
2098 upper4 = status >> 2;
2099 if (upper4 == 1 || upper4 == 2 || upper4 == 3 || upper4 == 15)
2100 return ERROR_TARGET_TRANSLATION_FAULT;
2101 else if (status == 33)
2102 return ERROR_TARGET_UNALIGNED_ACCESS;
2103 else
2104 return ERROR_TARGET_DATA_ABORT;
2105 } else {
2106 /* Normal format. */
2107 status = ((dfsr >> 6) & 0x10) | (dfsr & 0xf);
2108 if (status == 1)
2109 return ERROR_TARGET_UNALIGNED_ACCESS;
2110 else if (status == 5 || status == 7 || status == 3 || status == 6 ||
2111 status == 9 || status == 11 || status == 13 || status == 15)
2112 return ERROR_TARGET_TRANSLATION_FAULT;
2113 else
2114 return ERROR_TARGET_DATA_ABORT;
2115 }
2116 }
2117
2118 static int cortex_a_write_cpu_memory_slow(struct target *target,
2119 uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2120 {
2121 /* Writes count objects of size size from *buffer. Old value of DSCR must
2122 * be in *dscr; updated to new value. This is slow because it works for
2123 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2124 * the address is aligned, cortex_a_write_cpu_memory_fast should be
2125 * preferred.
2126 * Preconditions:
2127 * - Address is in R0.
2128 * - R0 is marked dirty.
2129 */
2130 struct armv7a_common *armv7a = target_to_armv7a(target);
2131 struct arm *arm = &armv7a->arm;
2132 int retval;
2133
2134 /* Mark register R1 as dirty, to use for transferring data. */
2135 arm_reg_current(arm, 1)->dirty = true;
2136
2137 /* Switch to non-blocking mode if not already in that mode. */
2138 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2139 if (retval != ERROR_OK)
2140 return retval;
2141
2142 /* Go through the objects. */
2143 while (count) {
2144 /* Write the value to store into DTRRX. */
2145 uint32_t data, opcode;
2146 if (size == 1)
2147 data = *buffer;
2148 else if (size == 2)
2149 data = target_buffer_get_u16(target, buffer);
2150 else
2151 data = target_buffer_get_u32(target, buffer);
2152 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2153 armv7a->debug_base + CPUDBG_DTRRX, data);
2154 if (retval != ERROR_OK)
2155 return retval;
2156
2157 /* Transfer the value from DTRRX to R1. */
2158 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr);
2159 if (retval != ERROR_OK)
2160 return retval;
2161
2162 /* Write the value transferred to R1 into memory. */
2163 if (size == 1)
2164 opcode = ARMV4_5_STRB_IP(1, 0);
2165 else if (size == 2)
2166 opcode = ARMV4_5_STRH_IP(1, 0);
2167 else
2168 opcode = ARMV4_5_STRW_IP(1, 0);
2169 retval = cortex_a_exec_opcode(target, opcode, dscr);
2170 if (retval != ERROR_OK)
2171 return retval;
2172
2173 /* Check for faults and return early. */
2174 if (*dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE))
2175 return ERROR_OK; /* A data fault is not considered a system failure. */
2176
2177 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2178 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2179 * must also check RXfull_l). Most of the time this will be free
2180 * because RXfull_l will be cleared immediately and cached in dscr. */
2181 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRRX_FULL_LATCHED, 0, dscr);
2182 if (retval != ERROR_OK)
2183 return retval;
2184
2185 /* Advance. */
2186 buffer += size;
2187 --count;
2188 }
2189
2190 return ERROR_OK;
2191 }
2192
2193 static int cortex_a_write_cpu_memory_fast(struct target *target,
2194 uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2195 {
2196 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2197 * in *dscr; updated to new value. This is fast but only works for
2198 * word-sized objects at aligned addresses.
2199 * Preconditions:
2200 * - Address is in R0 and must be a multiple of 4.
2201 * - R0 is marked dirty.
2202 */
2203 struct armv7a_common *armv7a = target_to_armv7a(target);
2204 int retval;
2205
2206 /* Switch to fast mode if not already in that mode. */
2207 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_FAST_MODE, dscr);
2208 if (retval != ERROR_OK)
2209 return retval;
2210
2211 /* Latch STC instruction. */
2212 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2213 armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2214 if (retval != ERROR_OK)
2215 return retval;
2216
2217 /* Transfer all the data and issue all the instructions. */
2218 return mem_ap_write_buf_noincr(armv7a->debug_ap, buffer,
2219 4, count, armv7a->debug_base + CPUDBG_DTRRX);
2220 }
2221
2222 static int cortex_a_write_cpu_memory(struct target *target,
2223 uint32_t address, uint32_t size,
2224 uint32_t count, const uint8_t *buffer)
2225 {
2226 /* Write memory through the CPU. */
2227 int retval, final_retval;
2228 struct armv7a_common *armv7a = target_to_armv7a(target);
2229 struct arm *arm = &armv7a->arm;
2230 uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2231
2232 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
2233 address, size, count);
2234 if (target->state != TARGET_HALTED) {
2235 LOG_WARNING("target not halted");
2236 return ERROR_TARGET_NOT_HALTED;
2237 }
2238
2239 if (!count)
2240 return ERROR_OK;
2241
2242 /* Clear any abort. */
2243 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2244 armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2245 if (retval != ERROR_OK)
2246 return retval;
2247
2248 /* Read DSCR. */
2249 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2250 armv7a->debug_base + CPUDBG_DSCR, &dscr);
2251 if (retval != ERROR_OK)
2252 return retval;
2253
2254 /* Switch to non-blocking mode if not already in that mode. */
2255 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2256 if (retval != ERROR_OK)
2257 goto out;
2258
2259 /* Mark R0 as dirty. */
2260 arm_reg_current(arm, 0)->dirty = true;
2261
2262 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2263 retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
2264 if (retval != ERROR_OK)
2265 goto out;
2266
2267 /* Get the memory address into R0. */
2268 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2269 armv7a->debug_base + CPUDBG_DTRRX, address);
2270 if (retval != ERROR_OK)
2271 goto out;
2272 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
2273 if (retval != ERROR_OK)
2274 goto out;
2275
2276 if (size == 4 && (address % 4) == 0) {
2277 /* We are doing a word-aligned transfer, so use fast mode. */
2278 retval = cortex_a_write_cpu_memory_fast(target, count, buffer, &dscr);
2279 } else {
2280 /* Use slow path. */
2281 retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
2282 }
2283
2284 out:
2285 final_retval = retval;
2286
2287 /* Switch to non-blocking mode if not already in that mode. */
2288 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2289 if (final_retval == ERROR_OK)
2290 final_retval = retval;
2291
2292 /* Wait for last issued instruction to complete. */
2293 retval = cortex_a_wait_instrcmpl(target, &dscr, true);
2294 if (final_retval == ERROR_OK)
2295 final_retval = retval;
2296
2297 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2298 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2299 * check RXfull_l). Most of the time this will be free because RXfull_l
2300 * will be cleared immediately and cached in dscr. However, don't do this
2301 * if there is fault, because then the instruction might not have completed
2302 * successfully. */
2303 if (!(dscr & DSCR_STICKY_ABORT_PRECISE)) {
2304 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRRX_FULL_LATCHED, 0, &dscr);
2305 if (retval != ERROR_OK)
2306 return retval;
2307 }
2308
2309 /* If there were any sticky abort flags, clear them. */
2310 if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
2311 fault_dscr = dscr;
2312 mem_ap_write_atomic_u32(armv7a->debug_ap,
2313 armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2314 dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
2315 } else {
2316 fault_dscr = 0;
2317 }
2318
2319 /* Handle synchronous data faults. */
2320 if (fault_dscr & DSCR_STICKY_ABORT_PRECISE) {
2321 if (final_retval == ERROR_OK) {
2322 /* Final return value will reflect cause of fault. */
2323 retval = cortex_a_read_dfar_dfsr(target, &fault_dfar, &fault_dfsr, &dscr);
2324 if (retval == ERROR_OK) {
2325 LOG_ERROR("data abort at 0x%08" PRIx32 ", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2326 final_retval = cortex_a_dfsr_to_error_code(fault_dfsr);
2327 } else
2328 final_retval = retval;
2329 }
2330 /* Fault destroyed DFAR/DFSR; restore them. */
2331 retval = cortex_a_write_dfar_dfsr(target, orig_dfar, orig_dfsr, &dscr);
2332 if (retval != ERROR_OK)
2333 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2334 }
2335
2336 /* Handle asynchronous data faults. */
2337 if (fault_dscr & DSCR_STICKY_ABORT_IMPRECISE) {
2338 if (final_retval == ERROR_OK)
2339 /* No other error has been recorded so far, so keep this one. */
2340 final_retval = ERROR_TARGET_DATA_ABORT;
2341 }
2342
2343 /* If the DCC is nonempty, clear it. */
2344 if (dscr & DSCR_DTRTX_FULL_LATCHED) {
2345 uint32_t dummy;
2346 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2347 armv7a->debug_base + CPUDBG_DTRTX, &dummy);
2348 if (final_retval == ERROR_OK)
2349 final_retval = retval;
2350 }
2351 if (dscr & DSCR_DTRRX_FULL_LATCHED) {
2352 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
2353 if (final_retval == ERROR_OK)
2354 final_retval = retval;
2355 }
2356
2357 /* Done. */
2358 return final_retval;
2359 }
2360
2361 static int cortex_a_read_cpu_memory_slow(struct target *target,
2362 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
2363 {
2364 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2365 * in *dscr; updated to new value. This is slow because it works for
2366 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2367 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2368 * preferred.
2369 * Preconditions:
2370 * - Address is in R0.
2371 * - R0 is marked dirty.
2372 */
2373 struct armv7a_common *armv7a = target_to_armv7a(target);
2374 struct arm *arm = &armv7a->arm;
2375 int retval;
2376
2377 /* Mark register R1 as dirty, to use for transferring data. */
2378 arm_reg_current(arm, 1)->dirty = true;
2379
2380 /* Switch to non-blocking mode if not already in that mode. */
2381 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2382 if (retval != ERROR_OK)
2383 return retval;
2384
2385 /* Go through the objects. */
2386 while (count) {
2387 /* Issue a load of the appropriate size to R1. */
2388 uint32_t opcode, data;
2389 if (size == 1)
2390 opcode = ARMV4_5_LDRB_IP(1, 0);
2391 else if (size == 2)
2392 opcode = ARMV4_5_LDRH_IP(1, 0);
2393 else
2394 opcode = ARMV4_5_LDRW_IP(1, 0);
2395 retval = cortex_a_exec_opcode(target, opcode, dscr);
2396 if (retval != ERROR_OK)
2397 return retval;
2398
2399 /* Issue a write of R1 to DTRTX. */
2400 retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr);
2401 if (retval != ERROR_OK)
2402 return retval;
2403
2404 /* Check for faults and return early. */
2405 if (*dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE))
2406 return ERROR_OK; /* A data fault is not considered a system failure. */
2407
2408 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2409 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2410 * must also check TXfull_l). Most of the time this will be free
2411 * because TXfull_l will be set immediately and cached in dscr. */
2412 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRTX_FULL_LATCHED,
2413 DSCR_DTRTX_FULL_LATCHED, dscr);
2414 if (retval != ERROR_OK)
2415 return retval;
2416
2417 /* Read the value transferred to DTRTX into the buffer. */
2418 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2419 armv7a->debug_base + CPUDBG_DTRTX, &data);
2420 if (retval != ERROR_OK)
2421 return retval;
2422 if (size == 1)
2423 *buffer = (uint8_t) data;
2424 else if (size == 2)
2425 target_buffer_set_u16(target, buffer, (uint16_t) data);
2426 else
2427 target_buffer_set_u32(target, buffer, data);
2428
2429 /* Advance. */
2430 buffer += size;
2431 --count;
2432 }
2433
2434 return ERROR_OK;
2435 }
2436
2437 static int cortex_a_read_cpu_memory_fast(struct target *target,
2438 uint32_t count, uint8_t *buffer, uint32_t *dscr)
2439 {
2440 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2441 * *dscr; updated to new value. This is fast but only works for word-sized
2442 * objects at aligned addresses.
2443 * Preconditions:
2444 * - Address is in R0 and must be a multiple of 4.
2445 * - R0 is marked dirty.
2446 */
2447 struct armv7a_common *armv7a = target_to_armv7a(target);
2448 uint32_t u32;
2449 int retval;
2450
2451 /* Switch to non-blocking mode if not already in that mode. */
2452 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2453 if (retval != ERROR_OK)
2454 return retval;
2455
2456 /* Issue the LDC instruction via a write to ITR. */
2457 retval = cortex_a_exec_opcode(target, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr);
2458 if (retval != ERROR_OK)
2459 return retval;
2460
2461 count--;
2462
2463 if (count > 0) {
2464 /* Switch to fast mode if not already in that mode. */
2465 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_FAST_MODE, dscr);
2466 if (retval != ERROR_OK)
2467 return retval;
2468
2469 /* Latch LDC instruction. */
2470 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2471 armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2472 if (retval != ERROR_OK)
2473 return retval;
2474
2475 /* Read the value transferred to DTRTX into the buffer. Due to fast
2476 * mode rules, this blocks until the instruction finishes executing and
2477 * then reissues the read instruction to read the next word from
2478 * memory. The last read of DTRTX in this call reads the second-to-last
2479 * word from memory and issues the read instruction for the last word.
2480 */
2481 retval = mem_ap_read_buf_noincr(armv7a->debug_ap, buffer,
2482 4, count, armv7a->debug_base + CPUDBG_DTRTX);
2483 if (retval != ERROR_OK)
2484 return retval;
2485
2486 /* Advance. */
2487 buffer += count * 4;
2488 }
2489
2490 /* Wait for last issued instruction to complete. */
2491 retval = cortex_a_wait_instrcmpl(target, dscr, false);
2492 if (retval != ERROR_OK)
2493 return retval;
2494
2495 /* Switch to non-blocking mode if not already in that mode. */
2496 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2497 if (retval != ERROR_OK)
2498 return retval;
2499
2500 /* Check for faults and return early. */
2501 if (*dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE))
2502 return ERROR_OK; /* A data fault is not considered a system failure. */
2503
2504 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2505 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2506 * check TXfull_l). Most of the time this will be free because TXfull_l
2507 * will be set immediately and cached in dscr. */
2508 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRTX_FULL_LATCHED,
2509 DSCR_DTRTX_FULL_LATCHED, dscr);
2510 if (retval != ERROR_OK)
2511 return retval;
2512
2513 /* Read the value transferred to DTRTX into the buffer. This is the last
2514 * word. */
2515 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2516 armv7a->debug_base + CPUDBG_DTRTX, &u32);
2517 if (retval != ERROR_OK)
2518 return retval;
2519 target_buffer_set_u32(target, buffer, u32);
2520
2521 return ERROR_OK;
2522 }
2523
2524 static int cortex_a_read_cpu_memory(struct target *target,
2525 uint32_t address, uint32_t size,
2526 uint32_t count, uint8_t *buffer)
2527 {
2528 /* Read memory through the CPU. */
2529 int retval, final_retval;
2530 struct armv7a_common *armv7a = target_to_armv7a(target);
2531 struct arm *arm = &armv7a->arm;
2532 uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2533
2534 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
2535 address, size, count);
2536 if (target->state != TARGET_HALTED) {
2537 LOG_WARNING("target not halted");
2538 return ERROR_TARGET_NOT_HALTED;
2539 }
2540
2541 if (!count)
2542 return ERROR_OK;
2543
2544 /* Clear any abort. */
2545 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2546 armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2547 if (retval != ERROR_OK)
2548 return retval;
2549
2550 /* Read DSCR */
2551 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2552 armv7a->debug_base + CPUDBG_DSCR, &dscr);
2553 if (retval != ERROR_OK)
2554 return retval;
2555
2556 /* Switch to non-blocking mode if not already in that mode. */
2557 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2558 if (retval != ERROR_OK)
2559 goto out;
2560
2561 /* Mark R0 as dirty. */
2562 arm_reg_current(arm, 0)->dirty = true;
2563
2564 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2565 retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
2566 if (retval != ERROR_OK)
2567 goto out;
2568
2569 /* Get the memory address into R0. */
2570 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2571 armv7a->debug_base + CPUDBG_DTRRX, address);
2572 if (retval != ERROR_OK)
2573 goto out;
2574 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
2575 if (retval != ERROR_OK)
2576 goto out;
2577
2578 if (size == 4 && (address % 4) == 0) {
2579 /* We are doing a word-aligned transfer, so use fast mode. */
2580 retval = cortex_a_read_cpu_memory_fast(target, count, buffer, &dscr);
2581 } else {
2582 /* Use slow path. */
2583 retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
2584 }
2585
2586 out:
2587 final_retval = retval;
2588
2589 /* Switch to non-blocking mode if not already in that mode. */
2590 retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2591 if (final_retval == ERROR_OK)
2592 final_retval = retval;
2593
2594 /* Wait for last issued instruction to complete. */
2595 retval = cortex_a_wait_instrcmpl(target, &dscr, true);
2596 if (final_retval == ERROR_OK)
2597 final_retval = retval;
2598
2599 /* If there were any sticky abort flags, clear them. */
2600 if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
2601 fault_dscr = dscr;
2602 mem_ap_write_atomic_u32(armv7a->debug_ap,
2603 armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2604 dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
2605 } else {
2606 fault_dscr = 0;
2607 }
2608
2609 /* Handle synchronous data faults. */
2610 if (fault_dscr & DSCR_STICKY_ABORT_PRECISE) {
2611 if (final_retval == ERROR_OK) {
2612 /* Final return value will reflect cause of fault. */
2613 retval = cortex_a_read_dfar_dfsr(target, &fault_dfar, &fault_dfsr, &dscr);
2614 if (retval == ERROR_OK) {
2615 LOG_ERROR("data abort at 0x%08" PRIx32 ", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2616 final_retval = cortex_a_dfsr_to_error_code(fault_dfsr);
2617 } else
2618 final_retval = retval;
2619 }
2620 /* Fault destroyed DFAR/DFSR; restore them. */
2621 retval = cortex_a_write_dfar_dfsr(target, orig_dfar, orig_dfsr, &dscr);
2622 if (retval != ERROR_OK)
2623 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2624 }
2625
2626 /* Handle asynchronous data faults. */
2627 if (fault_dscr & DSCR_STICKY_ABORT_IMPRECISE) {
2628 if (final_retval == ERROR_OK)
2629 /* No other error has been recorded so far, so keep this one. */
2630 final_retval = ERROR_TARGET_DATA_ABORT;
2631 }
2632
2633 /* If the DCC is nonempty, clear it. */
2634 if (dscr & DSCR_DTRTX_FULL_LATCHED) {
2635 uint32_t dummy;
2636 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2637 armv7a->debug_base + CPUDBG_DTRTX, &dummy);
2638 if (final_retval == ERROR_OK)
2639 final_retval = retval;
2640 }
2641 if (dscr & DSCR_DTRRX_FULL_LATCHED) {
2642 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
2643 if (final_retval == ERROR_OK)
2644 final_retval = retval;
2645 }
2646
2647 /* Done. */
2648 return final_retval;
2649 }
2650
2651
2652 /*
2653 * Cortex-A Memory access
2654 *
2655 * This is same Cortex-M3 but we must also use the correct
2656 * ap number for every access.
2657 */
2658
2659 static int cortex_a_read_phys_memory(struct target *target,
2660 target_addr_t address, uint32_t size,
2661 uint32_t count, uint8_t *buffer)
2662 {
2663 struct armv7a_common *armv7a = target_to_armv7a(target);
2664 struct adiv5_dap *swjdp = armv7a->arm.dap;
2665 uint8_t apsel = swjdp->apsel;
2666 int retval;
2667
2668 if (!count || !buffer)
2669 return ERROR_COMMAND_SYNTAX_ERROR;
2670
2671 LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
2672 address, size, count);
2673
2674 if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num))
2675 return mem_ap_read_buf(armv7a->memory_ap, buffer, size, count, address);
2676
2677 /* read memory through the CPU */
2678 cortex_a_prep_memaccess(target, 1);
2679 retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
2680 cortex_a_post_memaccess(target, 1);
2681
2682 return retval;
2683 }
2684
2685 static int cortex_a_read_memory(struct target *target, target_addr_t address,
2686 uint32_t size, uint32_t count, uint8_t *buffer)
2687 {
2688 int retval;
2689
2690 /* cortex_a handles unaligned memory access */
2691 LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
2692 address, size, count);
2693
2694 cortex_a_prep_memaccess(target, 0);
2695 retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
2696 cortex_a_post_memaccess(target, 0);
2697
2698 return retval;
2699 }
2700
2701 static int cortex_a_read_memory_ahb(struct target *target, target_addr_t address,
2702 uint32_t size, uint32_t count, uint8_t *buffer)
2703 {
2704 int mmu_enabled = 0;
2705 target_addr_t virt, phys;
2706 int retval;
2707 struct armv7a_common *armv7a = target_to_armv7a(target);
2708 struct adiv5_dap *swjdp = armv7a->arm.dap;
2709 uint8_t apsel = swjdp->apsel;
2710
2711 if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap->ap_num))
2712 return target_read_memory(target, address, size, count, buffer);
2713
2714 /* cortex_a handles unaligned memory access */
2715 LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
2716 address, size, count);
2717
2718 /* determine if MMU was enabled on target stop */
2719 if (!armv7a->is_armv7r) {
2720 retval = cortex_a_mmu(target, &mmu_enabled);
2721 if (retval != ERROR_OK)
2722 return retval;
2723 }
2724
2725 if (mmu_enabled) {
2726 virt = address;
2727 retval = cortex_a_virt2phys(target, virt, &phys);
2728 if (retval != ERROR_OK)
2729 return retval;
2730
2731 LOG_DEBUG("Reading at virtual address. "
2732 "Translating v:" TARGET_ADDR_FMT " to r:" TARGET_ADDR_FMT,
2733 virt, phys);
2734 address = phys;
2735 }
2736
2737 if (!count || !buffer)
2738 return ERROR_COMMAND_SYNTAX_ERROR;
2739
2740 retval = mem_ap_read_buf(armv7a->memory_ap, buffer, size, count, address);
2741
2742 return retval;
2743 }
2744
2745 static int cortex_a_write_phys_memory(struct target *target,
2746 target_addr_t address, uint32_t size,
2747 uint32_t count, const uint8_t *buffer)
2748 {
2749 struct armv7a_common *armv7a = target_to_armv7a(target);
2750 struct adiv5_dap *swjdp = armv7a->arm.dap;
2751 uint8_t apsel = swjdp->apsel;
2752 int retval;
2753
2754 if (!count || !buffer)
2755 return ERROR_COMMAND_SYNTAX_ERROR;
2756
2757 LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
2758 address, size, count);
2759
2760 if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num))
2761 return mem_ap_write_buf(armv7a->memory_ap, buffer, size, count, address);
2762
2763 /* write memory through the CPU */
2764 cortex_a_prep_memaccess(target, 1);
2765 retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
2766 cortex_a_post_memaccess(target, 1);
2767
2768 return retval;
2769 }
2770
2771 static int cortex_a_write_memory(struct target *target, target_addr_t address,
2772 uint32_t size, uint32_t count, const uint8_t *buffer)
2773 {
2774 int retval;
2775
2776 /* cortex_a handles unaligned memory access */
2777 LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
2778 address, size, count);
2779
2780 /* memory writes bypass the caches, must flush before writing */
2781 armv7a_cache_auto_flush_on_write(target, address, size * count);
2782
2783 cortex_a_prep_memaccess(target, 0);
2784 retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
2785 cortex_a_post_memaccess(target, 0);
2786 return retval;
2787 }
2788
2789 static int cortex_a_write_memory_ahb(struct target *target, target_addr_t address,
2790 uint32_t size, uint32_t count, const uint8_t *buffer)
2791 {
2792 int mmu_enabled = 0;
2793 target_addr_t virt, phys;
2794 int retval;
2795 struct armv7a_common *armv7a = target_to_armv7a(target);
2796 struct adiv5_dap *swjdp = armv7a->arm.dap;
2797 uint8_t apsel = swjdp->apsel;
2798
2799 if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap->ap_num))
2800 return target_write_memory(target, address, size, count, buffer);
2801
2802 /* cortex_a handles unaligned memory access */
2803 LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
2804 address, size, count);
2805
2806 /* determine if MMU was enabled on target stop */
2807 if (!armv7a->is_armv7r) {
2808 retval = cortex_a_mmu(target, &mmu_enabled);
2809 if (retval != ERROR_OK)
2810 return retval;
2811 }
2812
2813 if (mmu_enabled) {
2814 virt = address;
2815 retval = cortex_a_virt2phys(target, virt, &phys);
2816 if (retval != ERROR_OK)
2817 return retval;
2818
2819 LOG_DEBUG("Writing to virtual address. "
2820 "Translating v:" TARGET_ADDR_FMT " to r:" TARGET_ADDR_FMT,
2821 virt,
2822 phys);
2823 address = phys;
2824 }
2825
2826 if (!count || !buffer)
2827 return ERROR_COMMAND_SYNTAX_ERROR;
2828
2829 retval = mem_ap_write_buf(armv7a->memory_ap, buffer, size, count, address);
2830
2831 return retval;
2832 }
2833
2834 static int cortex_a_read_buffer(struct target *target, target_addr_t address,
2835 uint32_t count, uint8_t *buffer)
2836 {
2837 uint32_t size;
2838
2839 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2840 * will have something to do with the size we leave to it. */
2841 for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
2842 if (address & size) {
2843 int retval = cortex_a_read_memory_ahb(target, address, size, 1, buffer);
2844 if (retval != ERROR_OK)
2845 return retval;
2846 address += size;
2847 count -= size;
2848 buffer += size;
2849 }
2850 }
2851
2852 /* Read the data with as large access size as possible. */
2853 for (; size > 0; size /= 2) {
2854 uint32_t aligned = count - count % size;
2855 if (aligned > 0) {
2856 int retval = cortex_a_read_memory_ahb(target, address, size, aligned / size, buffer);
2857 if (retval != ERROR_OK)
2858 return retval;
2859 address += aligned;
2860 count -= aligned;
2861 buffer += aligned;
2862 }
2863 }
2864
2865 return ERROR_OK;
2866 }
2867
2868 static int cortex_a_write_buffer(struct target *target, target_addr_t address,
2869 uint32_t count, const uint8_t *buffer)
2870 {
2871 uint32_t size;
2872
2873 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2874 * will have something to do with the size we leave to it. */
2875 for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
2876 if (address & size) {
2877 int retval = cortex_a_write_memory_ahb(target, address, size, 1, buffer);
2878 if (retval != ERROR_OK)
2879 return retval;
2880 address += size;
2881 count -= size;
2882 buffer += size;
2883 }
2884 }
2885
2886 /* Write the data with as large access size as possible. */
2887 for (; size > 0; size /= 2) {
2888 uint32_t aligned = count - count % size;
2889 if (aligned > 0) {
2890 int retval = cortex_a_write_memory_ahb(target, address, size, aligned / size, buffer);
2891 if (retval != ERROR_OK)
2892 return retval;
2893 address += aligned;
2894 count -= aligned;
2895 buffer += aligned;
2896 }
2897 }
2898
2899 return ERROR_OK;
2900 }
2901
2902 static int cortex_a_handle_target_request(void *priv)
2903 {
2904 struct target *target = priv;
2905 struct armv7a_common *armv7a = target_to_armv7a(target);
2906 int retval;
2907
2908 if (!target_was_examined(target))
2909 return ERROR_OK;
2910 if (!target->dbg_msg_enabled)
2911 return ERROR_OK;
2912
2913 if (target->state == TARGET_RUNNING) {
2914 uint32_t request;
2915 uint32_t dscr;
2916 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2917 armv7a->debug_base + CPUDBG_DSCR, &dscr);
2918
2919 /* check if we have data */
2920 int64_t then = timeval_ms();
2921 while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2922 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2923 armv7a->debug_base + CPUDBG_DTRTX, &request);
2924 if (retval == ERROR_OK) {
2925 target_request(target, request);
2926 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2927 armv7a->debug_base + CPUDBG_DSCR, &dscr);
2928 }
2929 if (timeval_ms() > then + 1000) {
2930 LOG_ERROR("Timeout waiting for dtr tx full");
2931 return ERROR_FAIL;
2932 }
2933 }
2934 }
2935
2936 return ERROR_OK;
2937 }
2938
2939 /*
2940 * Cortex-A target information and configuration
2941 */
2942
2943 static int cortex_a_examine_first(struct target *target)
2944 {
2945 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
2946 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
2947 struct adiv5_dap *swjdp = armv7a->arm.dap;
2948
2949 int i;
2950 int retval = ERROR_OK;
2951 uint32_t didr, cpuid, dbg_osreg;
2952
2953 /* Search for the APB-AP - it is needed for access to debug registers */
2954 retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
2955 if (retval != ERROR_OK) {
2956 LOG_ERROR("Could not find APB-AP for debug access");
2957 return retval;
2958 }
2959
2960 retval = mem_ap_init(armv7a->debug_ap);
2961 if (retval != ERROR_OK) {
2962 LOG_ERROR("Could not initialize the APB-AP");
2963 return retval;
2964 }
2965
2966 armv7a->debug_ap->memaccess_tck = 80;
2967
2968 /* Search for the AHB-AB.
2969 * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
2970 * can access system memory. */
2971 armv7a->memory_ap_available = false;
2972 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7a->memory_ap);
2973 if (retval == ERROR_OK) {
2974 retval = mem_ap_init(armv7a->memory_ap);
2975 if (retval == ERROR_OK)
2976 armv7a->memory_ap_available = true;
2977 }
2978 if (retval != ERROR_OK) {
2979 /* AHB-AP not found or unavailable - use the CPU */
2980 LOG_DEBUG("No AHB-AP available for memory access");
2981 }
2982
2983 if (!target->dbgbase_set) {
2984 uint32_t dbgbase;
2985 /* Get ROM Table base */
2986 uint32_t apid;
2987 int32_t coreidx = target->coreid;
2988 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2989 target->cmd_name);
2990 retval = dap_get_debugbase(armv7a->debug_ap, &dbgbase, &apid);
2991 if (retval != ERROR_OK)
2992 return retval;
2993 /* Lookup 0x15 -- Processor DAP */
2994 retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, 0x15,
2995 &armv7a->debug_base, &coreidx);
2996 if (retval != ERROR_OK) {
2997 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2998 target->cmd_name);
2999 return retval;
3000 }
3001 LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
3002 target->coreid, armv7a->debug_base);
3003 } else
3004 armv7a->debug_base = target->dbgbase;
3005
3006 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3007 armv7a->debug_base + CPUDBG_DIDR, &didr);
3008 if (retval != ERROR_OK) {
3009 LOG_DEBUG("Examine %s failed", "DIDR");
3010 return retval;
3011 }
3012
3013 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3014 armv7a->debug_base + CPUDBG_CPUID, &cpuid);
3015 if (retval != ERROR_OK) {
3016 LOG_DEBUG("Examine %s failed", "CPUID");
3017 return retval;
3018 }
3019
3020 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
3021 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
3022
3023 cortex_a->didr = didr;
3024 cortex_a->cpuid = cpuid;
3025
3026 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3027 armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
3028 if (retval != ERROR_OK)
3029 return retval;
3030 LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
3031
3032 if ((dbg_osreg & PRSR_POWERUP_STATUS) == 0) {
3033 LOG_ERROR("target->coreid %" PRId32 " powered down!", target->coreid);
3034 target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */
3035 return ERROR_TARGET_INIT_FAILED;
3036 }
3037
3038 if (dbg_osreg & PRSR_STICKY_RESET_STATUS)
3039 LOG_DEBUG("target->coreid %" PRId32 " was reset!", target->coreid);
3040
3041 /* Read DBGOSLSR and check if OSLK is implemented */
3042 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3043 armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg);
3044 if (retval != ERROR_OK)
3045 return retval;
3046 LOG_DEBUG("target->coreid %" PRId32 " DBGOSLSR 0x%" PRIx32, target->coreid, dbg_osreg);
3047
3048 /* check if OS Lock is implemented */
3049 if ((dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM0 || (dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM1) {
3050 /* check if OS Lock is set */
3051 if (dbg_osreg & OSLSR_OSLK) {
3052 LOG_DEBUG("target->coreid %" PRId32 " OSLock set! Trying to unlock", target->coreid);
3053
3054 retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
3055 armv7a->debug_base + CPUDBG_OSLAR,
3056 0);
3057 if (retval == ERROR_OK)
3058 retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3059 armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg);
3060
3061 /* if we fail to access the register or cannot reset the OSLK bit, bail out */
3062 if (retval != ERROR_OK || (dbg_osreg & OSLSR_OSLK) != 0) {
3063 LOG_ERROR("target->coreid %" PRId32 " OSLock sticky, core not powered?",
3064 target->coreid);
3065 target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */
3066 return ERROR_TARGET_INIT_FAILED;
3067 }
3068 }
3069 }
3070
3071 armv7a->arm.core_type = ARM_MODE_MON;
3072
3073 /* Avoid recreating the registers cache */
3074 if (!target_was_examined(target)) {
3075 retval = cortex_a_dpm_setup(cortex_a, didr);
3076 if (retval != ERROR_OK)
3077 return retval;
3078 }
3079
3080 /* Setup Breakpoint Register Pairs */
3081 cortex_a->brp_num = ((didr >> 24) & 0x0F) + 1;
3082 cortex_a->brp_num_context = ((didr >> 20) & 0x0F) + 1;
3083 cortex_a->brp_num_available = cortex_a->brp_num;
3084 free(cortex_a->brp_list);
3085 cortex_a->brp_list = calloc(cortex_a->brp_num, sizeof(struct cortex_a_brp));
3086 /* cortex_a->brb_enabled = ????; */
3087 for (i = 0; i < cortex_a->brp_num; i++) {
3088 cortex_a->brp_list[i].used = 0;
3089 if (i < (cortex_a->brp_num-cortex_a->brp_num_context))
3090 cortex_a->brp_list[i].type = BRP_NORMAL;
3091 else
3092 cortex_a->brp_list[i].type = BRP_CONTEXT;
3093 cortex_a->brp_list[i].value = 0;
3094 cortex_a->brp_list[i].control = 0;
3095 cortex_a->brp_list[i].BRPn = i;
3096 }
3097
3098 LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
3099
3100 /* select debug_ap as default */
3101 swjdp->apsel = armv7a->debug_ap->ap_num;
3102
3103 target_set_examined(target);
3104 return ERROR_OK;
3105 }
3106
3107 static int cortex_a_examine(struct target *target)
3108 {
3109 int retval = ERROR_OK;
3110
3111 /* Reestablish communication after target reset */
3112 retval = cortex_a_examine_first(target);
3113
3114 /* Configure core debug access */
3115 if (retval == ERROR_OK)
3116 retval = cortex_a_init_debug_access(target);
3117
3118 return retval;
3119 }
3120
3121 /*
3122 * Cortex-A target creation and initialization
3123 */
3124
3125 static int cortex_a_init_target(struct command_context *cmd_ctx,
3126 struct target *target)
3127 {
3128 /* examine_first() does a bunch of this */
3129 arm_semihosting_init(target);
3130 return ERROR_OK;
3131 }
3132
3133 static int cortex_a_init_arch_info(struct target *target,
3134 struct cortex_a_common *cortex_a, struct adiv5_dap *dap)
3135 {
3136 struct armv7a_common *armv7a = &cortex_a->armv7a_common;
3137
3138 /* Setup struct cortex_a_common */
3139 cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3140 armv7a->arm.dap = dap;
3141
3142 cortex_a->fast_reg_read = 0;
3143
3144 /* register arch-specific functions */
3145 armv7a->examine_debug_reason = NULL;
3146
3147 armv7a->post_debug_entry = cortex_a_post_debug_entry;
3148
3149 armv7a->pre_restore_context = NULL;
3150
3151 armv7a->armv7a_mmu.read_physical_memory = cortex_a_read_phys_memory;
3152
3153
3154 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3155
3156 /* REVISIT v7a setup should be in a v7a-specific routine */
3157 armv7a_init_arch_info(target, armv7a);
3158 target_register_timer_callback(cortex_a_handle_target_request, 1, 1, target);
3159
3160 return ERROR_OK;
3161 }
3162
3163 static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
3164 {
3165 struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
3166 cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3167 struct adiv5_private_config *pc;
3168
3169 if (target->private_config == NULL)
3170 return ERROR_FAIL;
3171
3172 pc = (struct adiv5_private_config *)target->private_config;
3173
3174 cortex_a->armv7a_common.is_armv7r = false;
3175
3176 cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3;
3177
3178 return cortex_a_init_arch_info(target, cortex_a, pc->dap);
3179 }
3180
3181 static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
3182 {
3183 struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
3184 cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3185 struct adiv5_private_config *pc;
3186
3187 pc = (struct adiv5_private_config *)target->private_config;
3188 if (adiv5_verify_config(pc) != ERROR_OK)
3189 return ERROR_FAIL;
3190
3191 cortex_a->armv7a_common.is_armv7r = true;
3192
3193 return cortex_a_init_arch_info(target, cortex_a, pc->dap);
3194 }
3195
3196 static void cortex_a_deinit_target(struct target *target)
3197 {
3198 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3199 struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
3200
3201 free(cortex_a->brp_list);
3202 free(dpm->dbp);
3203 free(dpm->dwp);
3204 free(target->private_config);
3205 free(cortex_a);
3206 }
3207
3208 static int cortex_a_mmu(struct target *target, int *enabled)
3209 {
3210 struct armv7a_common *armv7a = target_to_armv7a(target);
3211
3212 if (target->state != TARGET_HALTED) {
3213 LOG_ERROR("%s: target not halted", __func__);
3214 return ERROR_TARGET_INVALID;
3215 }
3216
3217 if (armv7a->is_armv7r)
3218 *enabled = 0;
3219 else
3220 *enabled = target_to_cortex_a(target)->armv7a_common.armv7a_mmu.mmu_enabled;
3221
3222 return ERROR_OK;
3223 }
3224
3225 static int cortex_a_virt2phys(struct target *target,
3226 target_addr_t virt, target_addr_t *phys)
3227 {
3228 int retval = ERROR_FAIL;
3229 struct armv7a_common *armv7a = target_to_armv7a(target);
3230 struct adiv5_dap *swjdp = armv7a->arm.dap;
3231 uint8_t apsel = swjdp->apsel;
3232 if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num)) {
3233 uint32_t ret;
3234 retval = armv7a_mmu_translate_va(target,
3235 virt, &ret);
3236 if (retval != ERROR_OK)
3237 goto done;
3238 *phys = ret;
3239 } else {/* use this method if armv7a->memory_ap not selected
3240 * mmu must be enable in order to get a correct translation */
3241 retval = cortex_a_mmu_modify(target, 1);
3242 if (retval != ERROR_OK)
3243 goto done;
3244 retval = armv7a_mmu_translate_va_pa(target, (uint32_t)virt,
3245 (uint32_t *)phys, 1);
3246 }
3247 done:
3248 return retval;
3249 }
3250
3251 COMMAND_HANDLER(cortex_a_handle_cache_info_command)
3252 {
3253 struct target *target = get_current_target(CMD_CTX);
3254 struct armv7a_common *armv7a = target_to_armv7a(target);
3255
3256 return armv7a_handle_cache_info_command(CMD_CTX,
3257 &armv7a->armv7a_mmu.armv7a_cache);
3258 }
3259
3260
3261 COMMAND_HANDLER(cortex_a_handle_dbginit_command)
3262 {
3263 struct target *target = get_current_target(CMD_CTX);
3264 if (!target_was_examined(target)) {
3265 LOG_ERROR("target not examined yet");
3266 return ERROR_FAIL;
3267 }
3268
3269 return cortex_a_init_debug_access(target);
3270 }
3271 COMMAND_HANDLER(cortex_a_handle_smp_off_command)
3272 {
3273 struct target *target = get_current_target(CMD_CTX);
3274 /* check target is an smp target */
3275 struct target_list *head;
3276 struct target *curr;
3277 head = target->head;
3278 target->smp = 0;
3279 if (head != (struct target_list *)NULL) {
3280 while (head != (struct target_list *)NULL) {
3281 curr = head->target;
3282 curr->smp = 0;
3283 head = head->next;
3284 }
3285 /* fixes the target display to the debugger */
3286 target->gdb_service->target = target;
3287 }
3288 return ERROR_OK;
3289 }
3290
3291 COMMAND_HANDLER(cortex_a_handle_smp_on_command)
3292 {
3293 struct target *target = get_current_target(CMD_CTX);
3294 struct target_list *head;
3295 struct target *curr;
3296 head = target->head;
3297 if (head != (struct target_list *)NULL) {
3298 target->smp = 1;
3299 while (head != (struct target_list *)NULL) {
3300 curr = head->target;
3301 curr->smp = 1;
3302 head = head->next;
3303 }
3304 }
3305 return ERROR_OK;
3306 }
3307
3308 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command)
3309 {
3310 struct target *target = get_current_target(CMD_CTX);
3311 int retval = ERROR_OK;
3312 struct target_list *head;
3313 head = target->head;
3314 if (head != (struct target_list *)NULL) {
3315 if (CMD_ARGC == 1) {
3316 int coreid = 0;
3317 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
3318 if (ERROR_OK != retval)
3319 return retval;
3320 target->gdb_service->core[1] = coreid;
3321
3322 }
3323 command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
3324 , target->gdb_service->core[1]);
3325 }
3326 return ERROR_OK;
3327 }
3328
3329 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
3330 {
3331 struct target *target = get_current_target(CMD_CTX);
3332 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3333
3334 static const Jim_Nvp nvp_maskisr_modes[] = {
3335 { .name = "off", .value = CORTEX_A_ISRMASK_OFF },
3336 { .name = "on", .value = CORTEX_A_ISRMASK_ON },
3337 { .name = NULL, .value = -1 },
3338 };
3339 const Jim_Nvp *n;
3340
3341 if (CMD_ARGC > 0) {
3342 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
3343 if (n->name == NULL) {
3344 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
3345 return ERROR_COMMAND_SYNTAX_ERROR;
3346 }
3347
3348 cortex_a->isrmasking_mode = n->value;
3349 }
3350
3351 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode);
3352 command_print(CMD_CTX, "cortex_a interrupt mask %s", n->name);
3353
3354 return ERROR_OK;
3355 }
3356
3357 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command)
3358 {
3359 struct target *target = get_current_target(CMD_CTX);
3360 struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3361
3362 static const Jim_Nvp nvp_dacrfixup_modes[] = {
3363 { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF },
3364 { .name = "on", .value = CORTEX_A_DACRFIXUP_ON },
3365 { .name = NULL, .value = -1 },
3366 };
3367 const Jim_Nvp *n;
3368
3369 if (CMD_ARGC > 0) {
3370 n = Jim_Nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]);
3371 if (n->name == NULL)
3372 return ERROR_COMMAND_SYNTAX_ERROR;
3373 cortex_a->dacrfixup_mode = n->value;
3374
3375 }
3376
3377 n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
3378 command_print(CMD_CTX, "cortex_a domain access control fixup %s", n->name);
3379
3380 return ERROR_OK;
3381 }
3382
3383 static const struct command_registration cortex_a_exec_command_handlers[] = {
3384 {
3385 .name = "cache_info",
3386 .handler = cortex_a_handle_cache_info_command,
3387 .mode = COMMAND_EXEC,
3388 .help = "display information about target caches",
3389 .usage = "",
3390 },
3391 {
3392 .name = "dbginit",
3393 .handler = cortex_a_handle_dbginit_command,
3394 .mode = COMMAND_EXEC,
3395 .help = "Initialize core debug",
3396 .usage = "",
3397 },
3398 { .name = "smp_off",
3399 .handler = cortex_a_handle_smp_off_command,
3400 .mode = COMMAND_EXEC,
3401 .help = "Stop smp handling",
3402 .usage = "",},
3403 {
3404 .name = "smp_on",
3405 .handler = cortex_a_handle_smp_on_command,
3406 .mode = COMMAND_EXEC,
3407 .help = "Restart smp handling",
3408 .usage = "",
3409 },
3410 {
3411 .name = "smp_gdb",
3412 .handler = cortex_a_handle_smp_gdb_command,
3413 .mode = COMMAND_EXEC,
3414 .help = "display/fix current core played to gdb",
3415 .usage = "",
3416 },
3417 {
3418 .name = "maskisr",
3419 .handler = handle_cortex_a_mask_interrupts_command,
3420 .mode = COMMAND_ANY,
3421 .help = "mask cortex_a interrupts",
3422 .usage = "['on'|'off']",
3423 },
3424 {
3425 .name = "dacrfixup",
3426 .handler = handle_cortex_a_dacrfixup_command,
3427 .mode = COMMAND_EXEC,
3428 .help = "set domain access control (DACR) to all-manager "
3429 "on memory access",
3430 .usage = "['on'|'off']",
3431 },
3432
3433 COMMAND_REGISTRATION_DONE
3434 };
3435 static const struct command_registration cortex_a_command_handlers[] = {
3436 {
3437 .chain = arm_command_handlers,
3438 },
3439 {
3440 .chain = armv7a_command_handlers,
3441 },
3442 {
3443 .name = "cortex_a",
3444 .mode = COMMAND_ANY,
3445 .help = "Cortex-A command group",
3446 .usage = "",
3447 .chain = cortex_a_exec_command_handlers,
3448 },
3449 COMMAND_REGISTRATION_DONE
3450 };
3451
3452 struct target_type cortexa_target = {
3453 .name = "cortex_a",
3454 .deprecated_name = "cortex_a8",
3455
3456 .poll = cortex_a_poll,
3457 .arch_state = armv7a_arch_state,
3458
3459 .halt = cortex_a_halt,
3460 .resume = cortex_a_resume,
3461 .step = cortex_a_step,
3462
3463 .assert_reset = cortex_a_assert_reset,
3464 .deassert_reset = cortex_a_deassert_reset,
3465
3466 /* REVISIT allow exporting VFP3 registers ... */
3467 .get_gdb_reg_list = arm_get_gdb_reg_list,
3468
3469 .read_memory = cortex_a_read_memory,
3470 .write_memory = cortex_a_write_memory,
3471
3472 .read_buffer = cortex_a_read_buffer,
3473 .write_buffer = cortex_a_write_buffer,
3474
3475 .checksum_memory = arm_checksum_memory,
3476 .blank_check_memory = arm_blank_check_memory,
3477
3478 .run_algorithm = armv4_5_run_algorithm,
3479
3480 .add_breakpoint = cortex_a_add_breakpoint,
3481 .add_context_breakpoint = cortex_a_add_context_breakpoint,
3482 .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
3483 .remove_breakpoint = cortex_a_remove_breakpoint,
3484 .add_watchpoint = NULL,
3485 .remove_watchpoint = NULL,
3486
3487 .commands = cortex_a_command_handlers,
3488 .target_create = cortex_a_target_create,
3489 .target_jim_configure = adiv5_jim_configure,
3490 .init_target = cortex_a_init_target,
3491 .examine = cortex_a_examine,
3492 .deinit_target = cortex_a_deinit_target,
3493
3494 .read_phys_memory = cortex_a_read_phys_memory,
3495 .write_phys_memory = cortex_a_write_phys_memory,
3496 .mmu = cortex_a_mmu,
3497 .virt2phys = cortex_a_virt2phys,
3498 };
3499
3500 static const struct command_registration cortex_r4_exec_command_handlers[] = {
3501 {
3502 .name = "dbginit",
3503 .handler = cortex_a_handle_dbginit_command,
3504 .mode = COMMAND_EXEC,
3505 .help = "Initialize core debug",
3506 .usage = "",
3507 },
3508 {
3509 .name = "maskisr",
3510 .handler = handle_cortex_a_mask_interrupts_command,
3511 .mode = COMMAND_EXEC,
3512 .help = "mask cortex_r4 interrupts",
3513 .usage = "['on'|'off']",
3514 },
3515
3516 COMMAND_REGISTRATION_DONE
3517 };
3518 static const struct command_registration cortex_r4_command_handlers[] = {
3519 {
3520 .chain = arm_command_handlers,
3521 },
3522 {
3523 .name = "cortex_r4",
3524 .mode = COMMAND_ANY,
3525 .help = "Cortex-R4 command group",
3526 .usage = "",
3527 .chain = cortex_r4_exec_command_handlers,
3528 },
3529 COMMAND_REGISTRATION_DONE
3530 };
3531
3532 struct target_type cortexr4_target = {
3533 .name = "cortex_r4",
3534
3535 .poll = cortex_a_poll,
3536 .arch_state = armv7a_arch_state,
3537
3538 .halt = cortex_a_halt,
3539 .resume = cortex_a_resume,
3540 .step = cortex_a_step,
3541
3542 .assert_reset = cortex_a_assert_reset,
3543 .deassert_reset = cortex_a_deassert_reset,
3544
3545 /* REVISIT allow exporting VFP3 registers ... */
3546 .get_gdb_reg_list = arm_get_gdb_reg_list,
3547
3548 .read_memory = cortex_a_read_phys_memory,
3549 .write_memory = cortex_a_write_phys_memory,
3550
3551 .checksum_memory = arm_checksum_memory,
3552 .blank_check_memory = arm_blank_check_memory,
3553
3554 .run_algorithm = armv4_5_run_algorithm,
3555
3556 .add_breakpoint = cortex_a_add_breakpoint,
3557 .add_context_breakpoint = cortex_a_add_context_breakpoint,
3558 .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
3559 .remove_breakpoint = cortex_a_remove_breakpoint,
3560 .add_watchpoint = NULL,
3561 .remove_watchpoint = NULL,
3562
3563 .commands = cortex_r4_command_handlers,
3564 .target_create = cortex_r4_target_create,
3565 .target_jim_configure = adiv5_jim_configure,
3566 .init_target = cortex_a_init_target,
3567 .examine = cortex_a_examine,
3568 .deinit_target = cortex_a_deinit_target,
3569 };
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