Add RISC-V support.
[openocd.git] / src / target / armv4_5.h
blob3ce4ed0e56ca7089542aa5f76c878125c4ac8537
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_ARMV4_5_H
26 #define OPENOCD_TARGET_ARMV4_5_H
28 /* This stuff "knows" that its callers aren't talking
29 * to microcontroller profile (current Cortex-M) parts.
30 * We want to phase it out so core code can be shared.
33 /* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
34 * index into the armv4_5_core_reg_map array. Its remaining users are
35 * remnants which could as easily walk * the register cache directly as
36 * use the expensive ARMV4_5_CORE_REG_MODE() macro.
38 int arm_mode_to_number(enum arm_mode mode);
39 enum arm_mode armv4_5_number_to_mode(int number);
41 extern const int armv4_5_core_reg_map[8][17];
43 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
44 (cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
46 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
47 enum { ARMV4_5_CPSR = 31, };
49 #endif /* OPENOCD_TARGET_ARMV4_5_H */