1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/log.h>
26 #include <target/target.h>
27 #include "nds32_disassembler.h"
29 static const int enable4_bits
[] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4};
31 int nds32_read_opcode(struct nds32
*nds32
, uint32_t address
, uint32_t *value
)
33 struct target
*target
= nds32
->target
;
36 if (!target_was_examined(target
)) {
37 LOG_ERROR("Target not examined yet");
41 int retval
= target_read_buffer(target
, address
, 4, value_buf
);
43 if (retval
== ERROR_OK
) {
44 /* instructions are always big-endian */
45 *value
= be_to_h_u32(value_buf
);
47 LOG_DEBUG("address: 0x%8.8" PRIx32
", value: 0x%8.8" PRIx32
"",
52 LOG_DEBUG("address: 0x%8.8" PRIx32
" failed",
59 static int nds32_parse_type_0(uint32_t opcode
, int32_t *imm
)
61 *imm
= opcode
& 0x1FFFFFF;
66 static int nds32_parse_type_1(uint32_t opcode
, uint8_t *rt
, int32_t *imm
)
68 *rt
= (opcode
>> 20) & 0x1F;
69 *imm
= opcode
& 0xFFFFF;
74 static int nds32_parse_type_2(uint32_t opcode
, uint8_t *rt
, uint8_t *ra
, int32_t *imm
)
76 *rt
= (opcode
>> 20) & 0x1F;
77 *ra
= (opcode
>> 15) & 0x1F;
78 *imm
= opcode
& 0x7FFF;
83 static int nds32_parse_type_3(uint32_t opcode
, uint8_t *rt
, uint8_t *ra
,
84 uint8_t *rb
, int32_t *imm
)
86 *rt
= (opcode
>> 20) & 0x1F;
87 *ra
= (opcode
>> 15) & 0x1F;
88 *rb
= (opcode
>> 10) & 0x1F;
89 *imm
= opcode
& 0x3FF;
94 static int nds32_parse_type_4(uint32_t opcode
, uint8_t *rt
, uint8_t *ra
,
95 uint8_t *rb
, uint8_t *rd
, uint8_t *sub_opc
)
97 *rt
= (opcode
>> 20) & 0x1F;
98 *ra
= (opcode
>> 15) & 0x1F;
99 *rb
= (opcode
>> 10) & 0x1F;
100 *rd
= (opcode
>> 5) & 0x1F;
101 *sub_opc
= opcode
& 0x1F;
106 /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
107 static int nds32_parse_group_0_insn(struct nds32
*nds32
, uint32_t opcode
,
109 struct nds32_instruction
*instruction
)
113 opc_6
= instruction
->info
.opc_6
;
115 switch (opc_6
& 0x7) {
117 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
118 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
119 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
120 instruction
->type
= NDS32_INSN_LOAD_STORE
;
121 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
122 &(instruction
->access_start
));
123 instruction
->access_start
+= instruction
->info
.imm
;
124 instruction
->access_end
= instruction
->access_start
+ 1;
125 snprintf(instruction
->text
,
127 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBI\t$r%d,[$r%d+#%d]",
129 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
130 instruction
->info
.imm
);
133 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
134 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
135 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 16; /* sign-extend */
136 instruction
->type
= NDS32_INSN_LOAD_STORE
;
137 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
138 &(instruction
->access_start
));
139 instruction
->access_start
+= instruction
->info
.imm
;
140 instruction
->access_end
= instruction
->access_start
+ 2;
141 snprintf(instruction
->text
,
143 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHI\t$r%d,[$r%d+#%d]",
145 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
146 instruction
->info
.imm
);
149 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
150 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
151 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 15; /* sign-extend */
152 instruction
->type
= NDS32_INSN_LOAD_STORE
;
153 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
154 &(instruction
->access_start
));
155 instruction
->access_start
+= instruction
->info
.imm
;
156 instruction
->access_end
= instruction
->access_start
+ 4;
157 snprintf(instruction
->text
,
159 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLWI\t$r%d,[$r%d+#%d]",
161 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
162 instruction
->info
.imm
);
165 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
166 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
167 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
168 instruction
->type
= NDS32_INSN_LOAD_STORE
;
169 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
170 &(instruction
->access_start
));
171 instruction
->access_end
= instruction
->access_start
+ 1;
172 snprintf(instruction
->text
,
174 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBI.bi\t$r%d,[$r%d],#%d",
176 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
177 instruction
->info
.imm
);
180 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
181 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
182 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 16; /* sign-extend */
183 instruction
->type
= NDS32_INSN_LOAD_STORE
;
184 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
185 &(instruction
->access_start
));
186 instruction
->access_end
= instruction
->access_start
+ 2;
187 snprintf(instruction
->text
,
189 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHI.bi\t$r%d,[$r%d],#%d",
191 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
192 instruction
->info
.imm
);
195 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
196 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
197 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 15; /* sign-extend */
198 instruction
->type
= NDS32_INSN_LOAD_STORE
;
199 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
200 &(instruction
->access_start
));
201 instruction
->access_end
= instruction
->access_start
+ 4;
202 snprintf(instruction
->text
,
204 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLWI.bi\t$r%d,[$r%d],#%d",
206 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
207 instruction
->info
.imm
);
210 snprintf(instruction
->text
,
212 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
221 static int nds32_parse_group_1_insn(struct nds32
*nds32
, uint32_t opcode
,
222 uint32_t address
, struct nds32_instruction
*instruction
)
226 opc_6
= instruction
->info
.opc_6
;
228 switch (opc_6
& 0x7) {
230 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
231 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
232 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
233 instruction
->type
= NDS32_INSN_LOAD_STORE
;
234 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
235 &(instruction
->access_start
));
236 instruction
->access_start
+= instruction
->info
.imm
;
237 instruction
->access_end
= instruction
->access_start
+ 1;
238 snprintf(instruction
->text
,
240 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSBI\t$r%d,[$r%d+#%d]",
242 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
243 instruction
->info
.imm
);
246 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
247 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
248 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 16; /* sign-extend */
249 instruction
->type
= NDS32_INSN_LOAD_STORE
;
250 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
251 &(instruction
->access_start
));
252 instruction
->access_start
+= instruction
->info
.imm
;
253 instruction
->access_end
= instruction
->access_start
+ 2;
254 snprintf(instruction
->text
,
256 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSHI\t$r%d,[$r%d+#%d]",
258 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
259 instruction
->info
.imm
);
262 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
263 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
264 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 15; /* sign-extend */
265 instruction
->type
= NDS32_INSN_LOAD_STORE
;
266 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
267 &(instruction
->access_start
));
268 instruction
->access_start
+= instruction
->info
.imm
;
269 instruction
->access_end
= instruction
->access_start
+ 4;
270 snprintf(instruction
->text
,
272 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSWI\t$r%d,[$r%d+#%d]",
274 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
275 instruction
->info
.imm
);
278 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
279 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
280 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
281 instruction
->type
= NDS32_INSN_LOAD_STORE
;
282 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
283 &(instruction
->access_start
));
284 instruction
->access_end
= instruction
->access_start
+ 1;
285 snprintf(instruction
->text
,
287 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSBI.bi\t$r%d,[$r%d],#%d",
289 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
290 instruction
->info
.imm
);
293 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
294 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
295 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 16; /* sign-extend */
296 instruction
->type
= NDS32_INSN_LOAD_STORE
;
297 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
298 &(instruction
->access_start
));
299 instruction
->access_end
= instruction
->access_start
+ 2;
300 snprintf(instruction
->text
,
302 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSHI.bi\t$r%d,[$r%d],#%d",
304 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
305 instruction
->info
.imm
);
308 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
309 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
310 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 15; /* sign-extend */
311 instruction
->type
= NDS32_INSN_LOAD_STORE
;
312 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
313 &(instruction
->access_start
));
314 instruction
->access_end
= instruction
->access_start
+ 4;
315 snprintf(instruction
->text
,
317 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSWI.bi\t$r%d,[$r%d],#%d",
319 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
320 instruction
->info
.imm
);
323 snprintf(instruction
->text
,
325 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
334 static int nds32_parse_group_2_insn(struct nds32
*nds32
, uint32_t opcode
,
335 uint32_t address
, struct nds32_instruction
*instruction
)
339 opc_6
= instruction
->info
.opc_6
;
341 switch (opc_6
& 0x7) {
343 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
344 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
345 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
346 instruction
->type
= NDS32_INSN_LOAD_STORE
;
347 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
348 &(instruction
->access_start
));
349 instruction
->access_start
+= instruction
->info
.imm
;
350 instruction
->access_end
= instruction
->access_start
+ 1;
351 snprintf(instruction
->text
,
353 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBSI\t$r%d,[$r%d+#%d]",
355 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
356 instruction
->info
.imm
);
359 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
360 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
361 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 16; /* sign-extend */
362 instruction
->type
= NDS32_INSN_LOAD_STORE
;
363 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
364 &(instruction
->access_start
));
365 instruction
->access_start
+= instruction
->info
.imm
;
366 instruction
->access_end
= instruction
->access_start
+ 2;
367 snprintf(instruction
->text
,
369 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHSI\t$r%d,[$r%d+#%d]",
371 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
372 instruction
->info
.imm
);
374 case 3: { /* DPREFI */
376 nds32_parse_type_2(opcode
, &sub_type
, &(instruction
->info
.ra
),
377 &(instruction
->info
.imm
));
378 instruction
->info
.sub_opc
= sub_type
& 0xF;
379 instruction
->type
= NDS32_INSN_MISC
;
380 if (sub_type
& 0x10) { /* DPREFI.d */
382 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 14;
383 snprintf(instruction
->text
,
385 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDPREFI.d\t%d,[$r%d+#%d]",
387 opcode
, instruction
->info
.sub_opc
,
388 instruction
->info
.ra
, instruction
->info
.imm
);
389 } else { /* DPREFI.w */
391 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 15;
392 snprintf(instruction
->text
,
394 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDPREFI.w\t%d,[$r%d+#%d]",
396 opcode
, instruction
->info
.sub_opc
,
397 instruction
->info
.ra
, instruction
->info
.imm
);
401 case 4: /* LBSI.bi */
402 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
403 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
404 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
405 instruction
->type
= NDS32_INSN_LOAD_STORE
;
406 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
407 &(instruction
->access_start
));
408 instruction
->access_end
= instruction
->access_start
+ 1;
409 snprintf(instruction
->text
,
411 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBSI.bi\t$r%d,[$r%d],#%d",
413 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
414 instruction
->info
.imm
);
416 case 5: /* LHSI.bi */
417 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
418 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
419 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 16; /* sign-extend */
420 instruction
->type
= NDS32_INSN_LOAD_STORE
;
421 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
422 &(instruction
->access_start
));
423 instruction
->access_end
= instruction
->access_start
+ 2;
424 snprintf(instruction
->text
,
426 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHSI.bi\t$r%d,[$r%d],#%d",
428 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
429 instruction
->info
.imm
);
432 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.imm
));
433 instruction
->type
= NDS32_INSN_LOAD_STORE
;
434 if ((instruction
->info
.imm
>> 19) & 0x1) { /* LBSI.gp */
435 instruction
->info
.imm
= (instruction
->info
.imm
<< 13) >> 13;
436 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
437 instruction
->access_start
+= instruction
->info
.imm
;
438 instruction
->access_end
= instruction
->access_start
+ 1;
439 snprintf(instruction
->text
,
441 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBSI.gp\t$r%d,[#%d]",
443 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
444 } else { /* LBI.gp */
445 instruction
->info
.imm
= (instruction
->info
.imm
<< 13) >> 13;
446 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
447 instruction
->access_start
+= instruction
->info
.imm
;
448 instruction
->access_end
= instruction
->access_start
+ 1;
449 snprintf(instruction
->text
,
451 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBI.gp\t$r%d,[#%d]",
453 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
457 snprintf(instruction
->text
,
459 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
468 static int nds32_parse_mem(struct nds32
*nds32
, uint32_t opcode
, uint32_t address
,
469 struct nds32_instruction
*instruction
)
471 uint32_t sub_opcode
= opcode
& 0x3F;
472 uint32_t val_ra
, val_rb
;
473 switch (sub_opcode
>> 3) {
475 switch (sub_opcode
& 0x7) {
477 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
478 &(instruction
->info
.ra
), \
479 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
480 instruction
->type
= NDS32_INSN_LOAD_STORE
;
481 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
482 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
483 instruction
->access_start
= val_ra
+
484 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
485 instruction
->access_end
= instruction
->access_start
+ 1;
486 snprintf(instruction
->text
,
488 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLB\t$r%d,[$r%d+($r%d<<%d)]",
490 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
491 instruction
->info
.rb
,
492 (instruction
->info
.imm
>> 8) & 0x3);
495 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
496 &(instruction
->info
.ra
),
497 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
498 instruction
->type
= NDS32_INSN_LOAD_STORE
;
499 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
500 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
501 instruction
->access_start
= val_ra
+
502 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
503 instruction
->access_end
= instruction
->access_start
+ 2;
504 snprintf(instruction
->text
,
506 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLH\t$r%d,[$r%d+($r%d<<%d)]",
508 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
509 instruction
->info
.rb
,
510 (instruction
->info
.imm
>> 8) & 0x3);
513 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
514 &(instruction
->info
.ra
),
515 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
516 instruction
->type
= NDS32_INSN_LOAD_STORE
;
517 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
518 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
519 instruction
->access_start
= val_ra
+
520 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
521 instruction
->access_end
= instruction
->access_start
+ 4;
522 snprintf(instruction
->text
,
524 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLW\t$r%d,[$r%d+($r%d<<%d)]",
526 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
527 instruction
->info
.rb
,
528 (instruction
->info
.imm
>> 8) & 0x3);
531 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
532 &(instruction
->info
.ra
),
533 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
534 instruction
->type
= NDS32_INSN_LOAD_STORE
;
535 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
536 &(instruction
->access_start
));
537 instruction
->access_end
= instruction
->access_start
+ 1;
538 snprintf(instruction
->text
,
540 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLB.bi\t$r%d,[$r%d],($r%d<<%d)",
542 opcode
, instruction
->info
.rt
,
543 instruction
->info
.ra
, instruction
->info
.rb
,
544 (instruction
->info
.imm
>> 8) & 0x3);
547 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
548 &(instruction
->info
.ra
),
549 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
550 instruction
->type
= NDS32_INSN_LOAD_STORE
;
551 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
552 &(instruction
->access_start
));
553 instruction
->access_end
= instruction
->access_start
+ 2;
554 snprintf(instruction
->text
,
556 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLH.bi\t$r%d,[$r%d],($r%d<<%d)",
558 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
559 instruction
->info
.rb
,
560 (instruction
->info
.imm
>> 8) & 0x3);
563 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
564 &(instruction
->info
.ra
),
565 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
566 instruction
->type
= NDS32_INSN_LOAD_STORE
;
567 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
568 &(instruction
->access_start
));
569 instruction
->access_end
= instruction
->access_start
+ 4;
570 snprintf(instruction
->text
,
572 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLW.bi\t$r%d,[$r%d],($r%d<<%d)",
574 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
575 instruction
->info
.rb
,
576 (instruction
->info
.imm
>> 8) & 0x3);
581 switch (sub_opcode
& 0x7) {
583 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
584 &(instruction
->info
.ra
),
585 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
586 instruction
->type
= NDS32_INSN_LOAD_STORE
;
587 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
588 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
589 instruction
->access_start
= val_ra
+
590 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
591 instruction
->access_end
= instruction
->access_start
+ 1;
592 snprintf(instruction
->text
,
594 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSB\t$r%d,[$r%d+($r%d<<%d)]",
596 opcode
, instruction
->info
.rt
,
597 instruction
->info
.ra
, instruction
->info
.rb
,
598 (instruction
->info
.imm
>> 8) & 0x3);
601 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
602 &(instruction
->info
.ra
),
603 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
604 instruction
->type
= NDS32_INSN_LOAD_STORE
;
605 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
606 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
607 instruction
->access_start
= val_ra
+
608 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
609 instruction
->access_end
= instruction
->access_start
+ 2;
610 snprintf(instruction
->text
,
612 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSH\t$r%d,[$r%d+($r%d<<%d)]",
614 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
615 instruction
->info
.rb
,
616 (instruction
->info
.imm
>> 8) & 0x3);
619 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
620 &(instruction
->info
.ra
),
621 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
622 instruction
->type
= NDS32_INSN_LOAD_STORE
;
623 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
624 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
625 instruction
->access_start
= val_ra
+
626 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
627 instruction
->access_end
= instruction
->access_start
+ 4;
628 snprintf(instruction
->text
,
630 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSW\t$r%d,[$r%d+($r%d<<%d)]",
632 opcode
, instruction
->info
.rt
,
633 instruction
->info
.ra
, instruction
->info
.rb
,
634 (instruction
->info
.imm
>> 8) & 0x3);
637 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
638 &(instruction
->info
.ra
),
639 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
640 instruction
->type
= NDS32_INSN_LOAD_STORE
;
641 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
642 &(instruction
->access_start
));
643 instruction
->access_end
= instruction
->access_start
+ 1;
644 snprintf(instruction
->text
,
646 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSB.bi\t$r%d,[$r%d],($r%d<<%d)",
648 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
649 instruction
->info
.rb
,
650 (instruction
->info
.imm
>> 8) & 0x3);
653 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
654 &(instruction
->info
.ra
),
655 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
656 instruction
->type
= NDS32_INSN_LOAD_STORE
;
657 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
658 &(instruction
->access_start
));
659 instruction
->access_end
= instruction
->access_start
+ 2;
660 snprintf(instruction
->text
,
662 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSH.bi\t$r%d,[$r%d],($r%d<<%d)",
664 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
665 instruction
->info
.rb
,
666 (instruction
->info
.imm
>> 8) & 0x3);
669 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
670 &(instruction
->info
.ra
),
671 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
672 instruction
->type
= NDS32_INSN_LOAD_STORE
;
673 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
674 &(instruction
->access_start
));
675 instruction
->access_end
= instruction
->access_start
+ 4;
676 snprintf(instruction
->text
,
678 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSW.bi\t$r%d,[$r%d],($r%d<<%d)",
680 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
681 instruction
->info
.rb
,
682 (instruction
->info
.imm
>> 8) & 0x3);
687 switch (sub_opcode
& 0x7) {
689 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
690 &(instruction
->info
.ra
),
691 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
692 instruction
->type
= NDS32_INSN_LOAD_STORE
;
693 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
694 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
695 instruction
->access_start
= val_ra
+
696 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
697 instruction
->access_end
= instruction
->access_start
+ 1;
698 snprintf(instruction
->text
,
700 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBS\t$r%d,[$r%d+($r%d<<%d)]",
702 opcode
, instruction
->info
.rt
,
703 instruction
->info
.ra
, instruction
->info
.rb
,
704 (instruction
->info
.imm
>> 8) & 0x3);
707 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
708 &(instruction
->info
.ra
),
709 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
710 instruction
->type
= NDS32_INSN_LOAD_STORE
;
711 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
712 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
713 instruction
->access_start
= val_ra
+
714 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
715 instruction
->access_end
= instruction
->access_start
+ 2;
716 snprintf(instruction
->text
,
718 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHS\t$r%d,[$r%d+($r%d<<%d)]",
720 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
721 instruction
->info
.rb
,
722 (instruction
->info
.imm
>> 8) & 0x3);
725 nds32_parse_type_3(opcode
, &(instruction
->info
.sub_opc
),
726 &(instruction
->info
.ra
),
727 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
728 instruction
->type
= NDS32_INSN_MISC
;
729 snprintf(instruction
->text
,
731 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDPREF\t#%d,[$r%d+($r%d<<#%d)]",
733 opcode
, instruction
->info
.sub_opc
,
734 instruction
->info
.ra
, instruction
->info
.rb
,
735 (instruction
->info
.imm
>> 8) & 0x3);
738 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
739 &(instruction
->info
.ra
),
740 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
741 instruction
->type
= NDS32_INSN_LOAD_STORE
;
742 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
743 &(instruction
->access_start
));
744 instruction
->access_end
= instruction
->access_start
+ 1;
745 snprintf(instruction
->text
,
747 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBS.bi\t$r%d,[$r%d],($r%d<<%d)",
749 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
750 instruction
->info
.rb
,
751 (instruction
->info
.imm
>> 8) & 0x3);
754 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
755 &(instruction
->info
.ra
),
756 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
757 instruction
->type
= NDS32_INSN_LOAD_STORE
;
758 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
759 &(instruction
->access_start
));
760 instruction
->access_end
= instruction
->access_start
+ 2;
761 snprintf(instruction
->text
,
763 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHS.bi\t$r%d,[$r%d],($r%d<<%d)",
765 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
766 instruction
->info
.rb
,
767 (instruction
->info
.imm
>> 8) & 0x3);
772 switch (sub_opcode
& 0x7) {
774 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
775 &(instruction
->info
.ra
),
776 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
777 instruction
->type
= NDS32_INSN_LOAD_STORE
;
778 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
779 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
780 instruction
->access_start
= val_ra
+
781 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
782 instruction
->access_end
= instruction
->access_start
+ 4;
783 snprintf(instruction
->text
,
785 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLLW\t$r%d,[$r%d+($r%d<<%d)]",
787 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
788 instruction
->info
.rb
,
789 (instruction
->info
.imm
>> 8) & 0x3);
792 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
793 &(instruction
->info
.ra
),
794 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
795 instruction
->type
= NDS32_INSN_LOAD_STORE
;
796 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
797 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
798 instruction
->access_start
= val_ra
+
799 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
800 instruction
->access_end
= instruction
->access_start
+ 4;
801 snprintf(instruction
->text
,
803 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSCW\t$r%d,[$r%d+($r%d<<%d)]",
805 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
806 instruction
->info
.rb
,
807 (instruction
->info
.imm
>> 8) & 0x3);
812 switch (sub_opcode
& 0x7) {
814 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
815 &(instruction
->info
.ra
),
816 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
817 instruction
->type
= NDS32_INSN_LOAD_STORE
;
818 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
819 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
820 instruction
->access_start
= val_ra
+
821 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
822 instruction
->access_end
= instruction
->access_start
+ 1;
823 snprintf(instruction
->text
,
825 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLBUP\t$r%d,[$r%d+($r%d<<%d)]",
827 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
828 instruction
->info
.rb
,
829 (instruction
->info
.imm
>> 8) & 0x3);
832 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
833 &(instruction
->info
.ra
),
834 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
835 instruction
->type
= NDS32_INSN_LOAD_STORE
;
836 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
837 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
838 instruction
->access_start
= val_ra
+
839 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
840 instruction
->access_end
= instruction
->access_start
+ 4;
841 snprintf(instruction
->text
,
843 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLWUP\t$r%d,[$r%d+($r%d<<%d)]",
845 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
846 instruction
->info
.rb
,
847 (instruction
->info
.imm
>> 8) & 0x3);
852 switch (sub_opcode
& 0x7) {
854 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
855 &(instruction
->info
.ra
),
856 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
857 instruction
->type
= NDS32_INSN_LOAD_STORE
;
858 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
859 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
860 instruction
->access_start
= val_ra
+
861 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
862 instruction
->access_end
= instruction
->access_start
+ 1;
863 snprintf(instruction
->text
,
865 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSBUP\t$r%d,[$r%d+($r%d<<%d)]",
867 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
868 instruction
->info
.rb
,
869 (instruction
->info
.imm
>> 8) & 0x3);
872 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
873 &(instruction
->info
.ra
),
874 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
875 instruction
->type
= NDS32_INSN_LOAD_STORE
;
876 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &val_ra
);
877 nds32_get_mapped_reg(nds32
, instruction
->info
.rb
, &val_rb
);
878 instruction
->access_start
= val_ra
+
879 (val_rb
<< ((instruction
->info
.imm
>> 8) & 0x3));
880 instruction
->access_end
= instruction
->access_start
+ 4;
881 snprintf(instruction
->text
,
883 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSWUP\t$r%d,[$r%d+($r%d<<%d)]",
885 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
886 instruction
->info
.rb
,
887 (instruction
->info
.imm
>> 8) & 0x3);
892 snprintf(instruction
->text
,
894 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
903 static int nds32_calculate_lsmw_access_range(struct nds32
*nds32
,
904 struct nds32_instruction
*instruction
)
910 enable4
= (instruction
->info
.imm
>> 6) & 0xF;
911 ba
= (instruction
->info
.imm
>> 4) & 0x1;
912 id
= (instruction
->info
.imm
>> 3) & 0x1;
915 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &(instruction
->access_start
));
916 if (id
) { /* decrease */
917 /* access_end is the (last_element+1), so no need to minus 4 */
918 /* instruction->access_end -= 4; */
919 instruction
->access_end
= instruction
->access_start
;
920 } else { /* increase */
921 instruction
->access_start
+= 4;
924 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
, &(instruction
->access_start
));
925 instruction
->access_end
= instruction
->access_start
- 4;
928 if (id
) { /* decrease */
929 instruction
->access_start
= instruction
->access_end
-
930 4 * (instruction
->info
.rd
- instruction
->info
.rb
+ 1);
931 instruction
->access_start
-= (4 * enable4_bits
[enable4
]);
932 } else { /* increase */
933 instruction
->access_end
= instruction
->access_start
+
934 4 * (instruction
->info
.rd
- instruction
->info
.rb
+ 1);
935 instruction
->access_end
+= (4 * enable4_bits
[enable4
]);
941 static int nds32_parse_lsmw(struct nds32
*nds32
, uint32_t opcode
, uint32_t address
,
942 struct nds32_instruction
*instruction
)
944 if (opcode
& 0x20) { /* SMW, SMWA, SMWZB */
945 switch (opcode
& 0x3) {
949 nds32_parse_type_3(opcode
, &(instruction
->info
.rb
),
950 &(instruction
->info
.ra
),
951 &(instruction
->info
.rd
), &(instruction
->info
.imm
));
952 instruction
->type
= NDS32_INSN_LOAD_STORE
;
953 nds32_calculate_lsmw_access_range(nds32
, instruction
);
954 snprintf(instruction
->text
,
956 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSMW\t$r%d,[$r%d],$r%d,%d",
958 opcode
, instruction
->info
.rb
, instruction
->info
.ra
,
959 instruction
->info
.rd
,
960 (instruction
->info
.imm
>> 6) & 0xF);
963 nds32_parse_type_3(opcode
, &(instruction
->info
.rb
),
964 &(instruction
->info
.ra
),
965 &(instruction
->info
.rd
), &(instruction
->info
.imm
));
966 instruction
->type
= NDS32_INSN_LOAD_STORE
;
967 nds32_calculate_lsmw_access_range(nds32
, instruction
);
968 snprintf(instruction
->text
,
970 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSMWA\t$r%d,[$r%d],$r%d,%d",
972 opcode
, instruction
->info
.rb
, instruction
->info
.ra
,
973 instruction
->info
.rd
,
974 (instruction
->info
.imm
>> 6) & 0xF);
977 nds32_parse_type_3(opcode
, &(instruction
->info
.rb
),
978 &(instruction
->info
.ra
),
979 &(instruction
->info
.rd
), &(instruction
->info
.imm
));
980 instruction
->type
= NDS32_INSN_LOAD_STORE
;
981 /* TODO: calculate access_start/access_end */
982 snprintf(instruction
->text
,
984 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSMWZB\t$r%d,[$r%d],$r%d,%d",
986 opcode
, instruction
->info
.rb
, instruction
->info
.ra
,
987 instruction
->info
.rd
,
988 (instruction
->info
.imm
>> 6) & 0xF);
991 snprintf(instruction
->text
,
993 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
998 } else { /* LMW, LMWA, LMWZB */
999 switch (opcode
& 0x3) {
1001 nds32_parse_type_3(opcode
, &(instruction
->info
.rb
),
1002 &(instruction
->info
.ra
),
1003 &(instruction
->info
.rd
), &(instruction
->info
.imm
));
1004 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1005 nds32_calculate_lsmw_access_range(nds32
, instruction
);
1006 snprintf(instruction
->text
,
1008 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLMW\t$r%d,[$r%d],$r%d,%d",
1010 opcode
, instruction
->info
.rb
, instruction
->info
.ra
,
1011 instruction
->info
.rd
,
1012 (instruction
->info
.imm
>> 6) & 0xF);
1015 nds32_parse_type_3(opcode
, &(instruction
->info
.rb
),
1016 &(instruction
->info
.ra
),
1017 &(instruction
->info
.rd
), &(instruction
->info
.imm
));
1018 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1019 nds32_calculate_lsmw_access_range(nds32
, instruction
);
1020 snprintf(instruction
->text
,
1022 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLMWA\t$r%d,[$r%d],$r%d,%d",
1024 opcode
, instruction
->info
.rb
, instruction
->info
.ra
,
1025 instruction
->info
.rd
,
1026 (instruction
->info
.imm
>> 6) & 0xF);
1029 nds32_parse_type_3(opcode
, &(instruction
->info
.rb
),
1030 &(instruction
->info
.ra
),
1031 &(instruction
->info
.rd
), &(instruction
->info
.imm
));
1032 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1033 /* TODO: calculate access_start/access_end */
1034 snprintf(instruction
->text
,
1036 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLMWZB\t$r%d,[$r%d],$r%d,%d",
1038 opcode
, instruction
->info
.rb
, instruction
->info
.ra
,
1039 instruction
->info
.rd
,
1040 (instruction
->info
.imm
>> 6) & 0xF);
1043 snprintf(instruction
->text
,
1045 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
1055 static int nds32_parse_hwgp(struct nds32
*nds32
, uint32_t opcode
, uint32_t address
,
1056 struct nds32_instruction
*instruction
)
1058 switch ((opcode
>> 18) & 0x3) {
1059 case 0: /* LHI.gp */
1060 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.imm
));
1061 instruction
->info
.imm
= (instruction
->info
.imm
<< 14) >> 13; /* sign-extend */
1062 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1063 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
1064 instruction
->access_start
+= instruction
->info
.imm
;
1065 instruction
->access_end
= instruction
->access_start
+ 2;
1066 snprintf(instruction
->text
,
1068 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHI.gp\t$r%d,[#%d]",
1070 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1072 case 1: /* LHSI.gp */
1073 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.imm
));
1074 instruction
->info
.imm
= (instruction
->info
.imm
<< 14) >> 13; /* sign-extend */
1075 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1076 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
1077 instruction
->access_start
+= instruction
->info
.imm
;
1078 instruction
->access_end
= instruction
->access_start
+ 2;
1079 snprintf(instruction
->text
,
1081 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLHSI.gp\t$r%d,[#%d]",
1083 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1085 case 2: /* SHI.gp */
1086 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.imm
));
1087 instruction
->info
.imm
= (instruction
->info
.imm
<< 14) >> 13; /* sign-extend */
1088 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1089 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
1090 instruction
->access_start
+= instruction
->info
.imm
;
1091 instruction
->access_end
= instruction
->access_start
+ 2;
1092 snprintf(instruction
->text
,
1094 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSHI.gp\t$r%d,[#%d]",
1096 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1099 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1100 if ((opcode
>> 17) & 0x1) { /* SWI.gp */
1101 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
1102 &(instruction
->info
.imm
));
1104 instruction
->info
.imm
= (instruction
->info
.imm
<< 15) >> 13;
1105 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
1106 instruction
->access_start
+= instruction
->info
.imm
;
1107 instruction
->access_end
= instruction
->access_start
+ 4;
1108 snprintf(instruction
->text
,
1110 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSWI.gp\t$r%d,[#%d]",
1112 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1113 } else { /* LWI.gp */
1114 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
1115 &(instruction
->info
.imm
));
1117 instruction
->info
.imm
= (instruction
->info
.imm
<< 15) >> 13;
1118 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
1119 instruction
->access_start
+= instruction
->info
.imm
;
1120 instruction
->access_end
= instruction
->access_start
+ 4;
1121 snprintf(instruction
->text
,
1123 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tLWI.gp\t$r%d,[#%d]",
1125 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1130 snprintf(instruction
->text
,
1132 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
1141 static int nds32_parse_sbgp(struct nds32
*nds32
, uint32_t opcode
, uint32_t address
,
1142 struct nds32_instruction
*instruction
)
1144 switch ((opcode
>> 19) & 0x1) {
1145 case 0: /* SBI.gp */
1146 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.imm
));
1147 instruction
->info
.imm
= (instruction
->info
.imm
<< 13) >> 13; /* sign-extend */
1148 instruction
->type
= NDS32_INSN_LOAD_STORE
;
1149 nds32_get_mapped_reg(nds32
, R29
, &(instruction
->access_start
));
1150 instruction
->access_start
+= instruction
->info
.imm
;
1151 instruction
->access_end
= instruction
->access_start
+ 1;
1152 snprintf(instruction
->text
,
1154 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSBI.gp\t$r%d,[#%d]",
1156 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1158 case 1: /* ADDI.gp */
1159 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.imm
));
1160 instruction
->info
.imm
= (instruction
->info
.imm
<< 13) >> 13; /* sign-extend */
1161 instruction
->type
= NDS32_INSN_DATA_PROC
;
1162 snprintf(instruction
->text
,
1164 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tADDI.gp\t$r%d,#%d",
1166 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
1169 snprintf(instruction
->text
,
1171 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
1180 static int nds32_parse_group_3_insn(struct nds32
*nds32
, uint32_t opcode
, uint32_t address
,
1181 struct nds32_instruction
*instruction
)
1185 opc_6
= instruction
->info
.opc_6
;
1187 switch (opc_6
& 0x7) {
1189 nds32_parse_mem(nds32
, opcode
, address
, instruction
);
1192 nds32_parse_lsmw(nds32
, opcode
, address
, instruction
);
1195 nds32_parse_hwgp(nds32
, opcode
, address
, instruction
);
1198 nds32_parse_sbgp(nds32
, opcode
, address
, instruction
);
1201 snprintf(instruction
->text
,
1203 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
1212 static int nds32_parse_alu_1(uint32_t opcode
, uint32_t address
,
1213 struct nds32_instruction
*instruction
)
1215 switch (opcode
& 0x1F) {
1217 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
), &(instruction
->info
.ra
),
1218 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1219 instruction
->type
= NDS32_INSN_DATA_PROC
;
1220 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1221 if (instruction
->info
.imm
)
1222 snprintf(instruction
->text
,
1224 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tADD_SLLI\t$r%d,$r%d,$r%d,%d",
1226 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1227 instruction
->info
.rb
,
1228 instruction
->info
.imm
);
1230 snprintf(instruction
->text
,
1232 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tADD\t$r%d,$r%d,$r%d",
1234 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1235 instruction
->info
.rb
);
1238 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1239 &(instruction
->info
.ra
),
1240 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1241 instruction
->type
= NDS32_INSN_DATA_PROC
;
1242 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1243 if (instruction
->info
.imm
)
1244 snprintf(instruction
->text
,
1246 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSUB_SLLI\t$r%d,$r%d,$r%d,%d",
1248 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1249 instruction
->info
.rb
,
1250 instruction
->info
.imm
);
1252 snprintf(instruction
->text
,
1254 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSUB\t$r%d,$r%d,$r%d",
1256 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1257 instruction
->info
.rb
);
1260 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1261 &(instruction
->info
.ra
),
1262 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1263 instruction
->type
= NDS32_INSN_DATA_PROC
;
1264 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1265 if (instruction
->info
.imm
)
1266 snprintf(instruction
->text
,
1268 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tAND_SLLI\t$r%d,$r%d,$r%d,%d",
1270 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1271 instruction
->info
.rb
,
1272 instruction
->info
.imm
);
1274 snprintf(instruction
->text
,
1276 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tAND\t$r%d,$r%d,$r%d",
1278 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1279 instruction
->info
.rb
);
1282 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1283 &(instruction
->info
.ra
),
1284 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1285 instruction
->type
= NDS32_INSN_DATA_PROC
;
1286 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1287 if (instruction
->info
.imm
)
1288 snprintf(instruction
->text
,
1290 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tXOR_SLLI\t$r%d,$r%d,$r%d,%d",
1292 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1293 instruction
->info
.rb
,
1294 instruction
->info
.imm
);
1296 snprintf(instruction
->text
,
1298 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tXOR\t$r%d,$r%d,$r%d",
1300 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1301 instruction
->info
.rb
);
1304 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1305 &(instruction
->info
.ra
),
1306 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1307 instruction
->type
= NDS32_INSN_DATA_PROC
;
1308 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1309 if (instruction
->info
.imm
)
1310 snprintf(instruction
->text
,
1312 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tOR_SLLI\t$r%d,$r%d,$r%d,%d",
1314 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1315 instruction
->info
.rb
,
1316 instruction
->info
.imm
);
1318 snprintf(instruction
->text
,
1320 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tOR\t$r%d,$r%d,$r%d",
1322 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1323 instruction
->info
.rb
);
1326 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1327 &(instruction
->info
.ra
),
1328 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1329 instruction
->type
= NDS32_INSN_DATA_PROC
;
1330 snprintf(instruction
->text
,
1332 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tNOR\t$r%d,$r%d,$r%d",
1334 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1335 instruction
->info
.rb
);
1338 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1339 &(instruction
->info
.ra
),
1340 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1341 instruction
->type
= NDS32_INSN_DATA_PROC
;
1342 snprintf(instruction
->text
,
1344 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSLT\t$r%d,$r%d,$r%d",
1346 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1347 instruction
->info
.rb
);
1350 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1351 &(instruction
->info
.ra
),
1352 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1353 instruction
->type
= NDS32_INSN_DATA_PROC
;
1354 snprintf(instruction
->text
,
1356 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSLTS\t$r%d,$r%d,$r%d",
1358 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1359 instruction
->info
.rb
);
1361 case 8: { /* SLLI */
1364 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1365 &(instruction
->info
.ra
),
1367 instruction
->info
.imm
= imm
;
1368 instruction
->type
= NDS32_INSN_DATA_PROC
;
1369 snprintf(instruction
->text
,
1371 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSLLI\t$r%d,$r%d,#%d",
1373 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1374 instruction
->info
.imm
);
1377 case 9: { /* SRLI */
1380 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1381 &(instruction
->info
.ra
),
1383 instruction
->info
.imm
= imm
;
1384 instruction
->type
= NDS32_INSN_DATA_PROC
;
1385 snprintf(instruction
->text
,
1387 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSRLI\t$r%d,$r%d,#%d",
1389 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1390 instruction
->info
.imm
);
1393 case 10: { /* SRAI */
1396 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1397 &(instruction
->info
.ra
),
1399 instruction
->info
.imm
= imm
;
1400 instruction
->type
= NDS32_INSN_DATA_PROC
;
1401 snprintf(instruction
->text
,
1403 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSRAI\t$r%d,$r%d,#%d",
1405 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1406 instruction
->info
.imm
);
1409 case 11: { /* ROTRI */
1412 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1413 &(instruction
->info
.ra
),
1415 instruction
->info
.imm
= imm
;
1416 instruction
->type
= NDS32_INSN_DATA_PROC
;
1417 snprintf(instruction
->text
,
1419 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tROTRI\t$r%d,$r%d,#%d",
1421 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1422 instruction
->info
.imm
);
1425 case 12: { /* SLL */
1426 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1427 &(instruction
->info
.ra
),
1428 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1429 instruction
->type
= NDS32_INSN_DATA_PROC
;
1430 snprintf(instruction
->text
,
1432 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSLL\t$r%d,$r%d,$r%d",
1434 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1435 instruction
->info
.rb
);
1438 case 13: { /* SRL */
1439 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1440 &(instruction
->info
.ra
),
1441 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1442 instruction
->type
= NDS32_INSN_DATA_PROC
;
1443 snprintf(instruction
->text
,
1445 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSRL\t$r%d,$r%d,$r%d",
1447 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1448 instruction
->info
.rb
);
1451 case 14: { /* SRA */
1452 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1453 &(instruction
->info
.ra
),
1454 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1455 instruction
->type
= NDS32_INSN_DATA_PROC
;
1456 snprintf(instruction
->text
,
1458 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSRA\t$r%d,$r%d,$r%d",
1460 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1461 instruction
->info
.rb
);
1464 case 15: { /* ROTR */
1465 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1466 &(instruction
->info
.ra
),
1467 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1468 instruction
->type
= NDS32_INSN_DATA_PROC
;
1469 snprintf(instruction
->text
,
1471 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tROTR\t$r%d,$r%d,$r%d",
1473 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1474 instruction
->info
.rb
);
1477 case 16: { /* SEB */
1478 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1479 &(instruction
->info
.ra
),
1480 &(instruction
->info
.imm
));
1481 instruction
->type
= NDS32_INSN_DATA_PROC
;
1482 snprintf(instruction
->text
,
1484 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSEB\t$r%d,$r%d",
1486 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1489 case 17: { /* SEH */
1490 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1491 &(instruction
->info
.ra
),
1492 &(instruction
->info
.imm
));
1493 instruction
->type
= NDS32_INSN_DATA_PROC
;
1494 snprintf(instruction
->text
,
1496 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSEH\t$r%d,$r%d",
1498 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1502 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1503 &(instruction
->info
.ra
),
1504 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1505 instruction
->type
= NDS32_INSN_DATA_PROC
;
1506 snprintf(instruction
->text
,
1508 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBITC\t$r%d,$r%d,$r%d",
1510 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1511 instruction
->info
.rb
);
1513 case 19: { /* ZEH */
1514 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1515 &(instruction
->info
.ra
),
1516 &(instruction
->info
.imm
));
1517 instruction
->type
= NDS32_INSN_DATA_PROC
;
1518 snprintf(instruction
->text
,
1520 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tZEH\t$r%d,$r%d",
1522 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1525 case 20: { /* WSBH */
1526 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1527 &(instruction
->info
.ra
),
1528 &(instruction
->info
.imm
));
1529 instruction
->type
= NDS32_INSN_DATA_PROC
;
1530 snprintf(instruction
->text
,
1532 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tWSBH\t$r%d,$r%d",
1534 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1537 case 21: /* OR_SRLI */
1538 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1539 &(instruction
->info
.ra
),
1540 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1541 instruction
->type
= NDS32_INSN_DATA_PROC
;
1542 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1543 if (instruction
->info
.imm
)
1544 snprintf(instruction
->text
,
1546 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tOR_SRLI\t$r%d,$r%d,$r%d,%d",
1548 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1549 instruction
->info
.rb
,
1550 instruction
->info
.imm
);
1552 snprintf(instruction
->text
,
1554 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tOR\t$r%d,$r%d,$r%d",
1556 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1557 instruction
->info
.rb
);
1559 case 22: { /* DIVSR */
1560 nds32_parse_type_4(opcode
, &(instruction
->info
.rt
),
1561 &(instruction
->info
.ra
),
1562 &(instruction
->info
.rb
), &(instruction
->info
.rd
),
1563 &(instruction
->info
.sub_opc
));
1564 instruction
->type
= NDS32_INSN_DATA_PROC
;
1565 snprintf(instruction
->text
,
1567 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDIVSR\t$r%d,$r%d,$r%d,$r%d",
1569 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1570 instruction
->info
.rb
,
1571 instruction
->info
.rd
);
1574 case 23: { /* DIVR */
1575 nds32_parse_type_4(opcode
, &(instruction
->info
.rt
),
1576 &(instruction
->info
.ra
),
1577 &(instruction
->info
.rb
), &(instruction
->info
.rd
),
1578 &(instruction
->info
.sub_opc
));
1579 instruction
->type
= NDS32_INSN_DATA_PROC
;
1580 snprintf(instruction
->text
,
1582 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDIVR\t$r%d,$r%d,$r%d,$r%d",
1584 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1585 instruction
->info
.rb
,
1586 instruction
->info
.rd
);
1589 case 24: { /* SVA */
1590 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1591 &(instruction
->info
.ra
),
1592 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1593 instruction
->type
= NDS32_INSN_DATA_PROC
;
1594 snprintf(instruction
->text
,
1596 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSVA\t$r%d,$r%d,$r%d",
1598 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1599 instruction
->info
.rb
);
1602 case 25: { /* SVS */
1603 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1604 &(instruction
->info
.ra
),
1605 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1606 instruction
->type
= NDS32_INSN_DATA_PROC
;
1607 snprintf(instruction
->text
,
1609 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSVS\t$r%d,$r%d,$r%d",
1611 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1612 instruction
->info
.rb
);
1615 case 26: { /* CMOVZ */
1616 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1617 &(instruction
->info
.ra
),
1618 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1619 instruction
->type
= NDS32_INSN_MISC
;
1620 snprintf(instruction
->text
,
1622 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCMOVZ\t$r%d,$r%d,$r%d",
1624 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1625 instruction
->info
.rb
);
1628 case 27: { /* CMOVN */
1629 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1630 &(instruction
->info
.ra
),
1631 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1632 instruction
->type
= NDS32_INSN_MISC
;
1633 snprintf(instruction
->text
,
1635 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCMOVN\t$r%d,$r%d,$r%d",
1637 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1638 instruction
->info
.rb
);
1641 case 28: /* ADD_SRLI */
1642 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1643 &(instruction
->info
.ra
),
1644 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1645 instruction
->type
= NDS32_INSN_DATA_PROC
;
1646 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1647 if (instruction
->info
.imm
)
1648 snprintf(instruction
->text
,
1650 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tADD_SRLI\t$r%d,$r%d,$r%d,%d",
1652 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1653 instruction
->info
.rb
,
1654 instruction
->info
.imm
);
1656 snprintf(instruction
->text
,
1658 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tADD\t$r%d,$r%d,$r%d",
1660 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1661 instruction
->info
.rb
);
1663 case 29: /* SUB_SRLI */
1664 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1665 &(instruction
->info
.ra
),
1666 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1667 instruction
->type
= NDS32_INSN_DATA_PROC
;
1668 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1669 if (instruction
->info
.imm
)
1670 snprintf(instruction
->text
,
1672 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSUB_SRLI\t$r%d,$r%d,$r%d,%d",
1674 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1675 instruction
->info
.rb
,
1676 instruction
->info
.imm
);
1678 snprintf(instruction
->text
,
1680 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSUB\t$r%d,$r%d,$r%d",
1682 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1683 instruction
->info
.rb
);
1685 case 30: /* AND_SRLI */
1686 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1687 &(instruction
->info
.ra
),
1688 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1689 instruction
->type
= NDS32_INSN_DATA_PROC
;
1690 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1691 if (instruction
->info
.imm
)
1692 snprintf(instruction
->text
,
1694 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tAND_SRLI\t$r%d,$r%d,$r%d,%d",
1696 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1697 instruction
->info
.rb
,
1698 instruction
->info
.imm
);
1700 snprintf(instruction
->text
,
1702 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tAND\t$r%d,$r%d,$r%d",
1704 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1705 instruction
->info
.rb
);
1707 case 31: /* XOR_SRLI */
1708 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1709 &(instruction
->info
.ra
),
1710 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1711 instruction
->type
= NDS32_INSN_DATA_PROC
;
1712 instruction
->info
.imm
= (instruction
->info
.imm
>> 5) & 0x1F;
1713 if (instruction
->info
.imm
)
1714 snprintf(instruction
->text
,
1716 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tXOR_SRLI\t$r%d,$r%d,$r%d,%d",
1718 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1719 instruction
->info
.rb
,
1720 instruction
->info
.imm
);
1722 snprintf(instruction
->text
,
1724 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tXOR\t$r%d,$r%d,$r%d",
1726 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1727 instruction
->info
.rb
);
1730 snprintf(instruction
->text
,
1732 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
1741 static int nds32_parse_alu_2(uint32_t opcode
, uint32_t address
,
1742 struct nds32_instruction
*instruction
)
1744 switch (opcode
& 0x3F) {
1746 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1747 &(instruction
->info
.ra
),
1748 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1749 instruction
->type
= NDS32_INSN_DATA_PROC
;
1750 snprintf(instruction
->text
,
1752 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMAX\t$r%d,$r%d,$r%d",
1754 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1755 instruction
->info
.rb
);
1758 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1759 &(instruction
->info
.ra
),
1760 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1761 instruction
->type
= NDS32_INSN_DATA_PROC
;
1762 snprintf(instruction
->text
,
1764 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMIN\t$r%d,$r%d,$r%d",
1766 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1767 instruction
->info
.rb
);
1770 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1771 &(instruction
->info
.ra
),
1772 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1773 instruction
->type
= NDS32_INSN_DATA_PROC
;
1774 snprintf(instruction
->text
,
1776 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tAVE\t$r%d,$r%d,$r%d",
1778 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1779 instruction
->info
.rb
);
1782 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1783 &(instruction
->info
.ra
),
1784 &(instruction
->info
.imm
));
1785 instruction
->type
= NDS32_INSN_DATA_PROC
;
1786 snprintf(instruction
->text
,
1788 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tAVE\t$r%d,$r%d",
1790 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1792 case 4: { /* CLIPS */
1794 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1795 &(instruction
->info
.ra
),
1796 &imm
, &(instruction
->info
.imm
));
1797 instruction
->info
.imm
= imm
;
1798 instruction
->type
= NDS32_INSN_DATA_PROC
;
1799 snprintf(instruction
->text
,
1801 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCLIPS\t$r%d,$r%d,#%d",
1803 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1804 instruction
->info
.imm
);
1807 case 5: { /* CLIP */
1809 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1810 &(instruction
->info
.ra
),
1811 &imm
, &(instruction
->info
.imm
));
1812 instruction
->info
.imm
= imm
;
1813 instruction
->type
= NDS32_INSN_DATA_PROC
;
1814 snprintf(instruction
->text
,
1816 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCLIP\t$r%d,$r%d,#%d",
1818 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1819 instruction
->info
.imm
);
1823 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1824 &(instruction
->info
.ra
),
1825 &(instruction
->info
.imm
));
1826 instruction
->type
= NDS32_INSN_DATA_PROC
;
1827 snprintf(instruction
->text
,
1829 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCLO\t$r%d,$r%d",
1831 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1834 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
1835 &(instruction
->info
.ra
),
1836 &(instruction
->info
.imm
));
1837 instruction
->type
= NDS32_INSN_DATA_PROC
;
1838 snprintf(instruction
->text
,
1840 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCLZ\t$r%d,$r%d",
1842 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
1844 case 8: { /* BSET */
1846 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1847 &(instruction
->info
.ra
),
1848 &imm
, &(instruction
->info
.imm
));
1849 instruction
->info
.imm
= imm
;
1850 instruction
->type
= NDS32_INSN_DATA_PROC
;
1851 snprintf(instruction
->text
,
1853 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBSET\t$r%d,$r%d,#%d",
1855 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1856 instruction
->info
.imm
);
1859 case 9: { /* BCLR */
1861 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1862 &(instruction
->info
.ra
),
1863 &imm
, &(instruction
->info
.imm
));
1864 instruction
->info
.imm
= imm
;
1865 instruction
->type
= NDS32_INSN_DATA_PROC
;
1866 snprintf(instruction
->text
,
1868 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBCLR\t$r%d,$r%d,#%d",
1870 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1871 instruction
->info
.imm
);
1874 case 10: { /* BTGL */
1876 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1877 &(instruction
->info
.ra
),
1878 &imm
, &(instruction
->info
.imm
));
1879 instruction
->info
.imm
= imm
;
1880 instruction
->type
= NDS32_INSN_DATA_PROC
;
1881 snprintf(instruction
->text
,
1883 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBTGL\t$r%d,$r%d,#%d",
1885 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1886 instruction
->info
.imm
);
1889 case 11: { /* BTST */
1891 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1892 &(instruction
->info
.ra
),
1893 &imm
, &(instruction
->info
.imm
));
1894 instruction
->info
.imm
= imm
;
1895 instruction
->type
= NDS32_INSN_DATA_PROC
;
1896 snprintf(instruction
->text
,
1898 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBTST\t$r%d,$r%d,#%d",
1900 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1901 instruction
->info
.imm
);
1905 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1906 &(instruction
->info
.ra
),
1907 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1908 instruction
->type
= NDS32_INSN_DATA_PROC
;
1909 snprintf(instruction
->text
,
1911 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBSE\t$r%d,$r%d,$r%d",
1913 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1914 instruction
->info
.rb
);
1917 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1918 &(instruction
->info
.ra
),
1919 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1920 instruction
->type
= NDS32_INSN_DATA_PROC
;
1921 snprintf(instruction
->text
,
1923 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBSP\t$r%d,$r%d,$r%d",
1925 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1926 instruction
->info
.rb
);
1929 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1930 &(instruction
->info
.ra
),
1931 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1932 instruction
->type
= NDS32_INSN_DATA_PROC
;
1933 snprintf(instruction
->text
,
1935 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tFFB\t$r%d,$r%d,$r%d",
1937 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1938 instruction
->info
.rb
);
1940 case 15: /* FFMISM */
1941 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1942 &(instruction
->info
.ra
),
1943 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1944 instruction
->type
= NDS32_INSN_DATA_PROC
;
1945 snprintf(instruction
->text
,
1947 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tFFMISM\t$r%d,$r%d,$r%d",
1949 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1950 instruction
->info
.rb
);
1952 case 23: /* FFZMISM */
1953 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1954 &(instruction
->info
.ra
),
1955 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1956 instruction
->type
= NDS32_INSN_DATA_PROC
;
1957 snprintf(instruction
->text
,
1959 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tFFZMISM\t$r%d,$r%d,$r%d",
1961 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1962 instruction
->info
.rb
);
1964 case 32: /* MFUSR */
1965 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
1966 &(instruction
->info
.imm
));
1967 instruction
->type
= NDS32_INSN_RESOURCE_ACCESS
;
1968 snprintf(instruction
->text
,
1970 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMFUSR\t$r%d,#%d",
1972 opcode
, instruction
->info
.rt
,
1973 (instruction
->info
.imm
>> 10) & 0x3FF);
1975 case 33: /* MTUSR */
1976 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
1977 &(instruction
->info
.imm
));
1978 instruction
->type
= NDS32_INSN_RESOURCE_ACCESS
;
1979 snprintf(instruction
->text
,
1981 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMTUSR\t$r%d,#%d",
1983 opcode
, instruction
->info
.rt
,
1984 (instruction
->info
.imm
>> 10) & 0x3FF);
1987 nds32_parse_type_3(opcode
, &(instruction
->info
.rt
),
1988 &(instruction
->info
.ra
),
1989 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
1990 instruction
->type
= NDS32_INSN_DATA_PROC
;
1991 snprintf(instruction
->text
,
1993 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMUL\t$r%d,$r%d,$r%d",
1995 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
1996 instruction
->info
.rb
);
1998 case 40: { /* MULTS64 */
2000 nds32_parse_type_3(opcode
, &dt_val
,
2001 &(instruction
->info
.ra
),
2002 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2003 instruction
->type
= NDS32_INSN_DATA_PROC
;
2004 snprintf(instruction
->text
,
2006 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMULTS64\t$D%d,$r%d,$r%d",
2008 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2009 instruction
->info
.rb
);
2012 case 41: { /* MULT64 */
2014 nds32_parse_type_3(opcode
, &dt_val
,
2015 &(instruction
->info
.ra
),
2016 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2017 instruction
->type
= NDS32_INSN_DATA_PROC
;
2018 snprintf(instruction
->text
,
2020 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMULT64\t$D%d,$r%d,$r%d",
2022 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2023 instruction
->info
.rb
);
2026 case 42: { /* MADDS64 */
2028 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2029 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2030 instruction
->type
= NDS32_INSN_DATA_PROC
;
2031 snprintf(instruction
->text
,
2033 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMADDS64\t$D%d,$r%d,$r%d",
2035 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2036 instruction
->info
.rb
);
2039 case 43: { /* MADD64 */
2041 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2042 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2043 instruction
->type
= NDS32_INSN_DATA_PROC
;
2044 snprintf(instruction
->text
,
2046 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMADD64\t$D%d,$r%d,$r%d",
2048 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2049 instruction
->info
.rb
);
2052 case 44: { /* MSUBS64 */
2054 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2055 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2056 instruction
->type
= NDS32_INSN_DATA_PROC
;
2057 snprintf(instruction
->text
,
2059 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMSUBS64\t$D%d,$r%d,$r%d",
2061 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2062 instruction
->info
.rb
);
2065 case 45: { /* MSUB64 */
2067 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2068 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2069 instruction
->type
= NDS32_INSN_DATA_PROC
;
2070 snprintf(instruction
->text
,
2072 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMSUB64\t$D%d,$r%d,$r%d",
2074 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2075 instruction
->info
.rb
);
2078 case 46: { /* DIVS */
2080 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2081 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2082 instruction
->type
= NDS32_INSN_DATA_PROC
;
2083 snprintf(instruction
->text
,
2085 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDIVS\t$D%d,$r%d,$r%d",
2087 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2088 instruction
->info
.rb
);
2091 case 47: { /* DIV */
2093 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2094 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2095 instruction
->type
= NDS32_INSN_DATA_PROC
;
2096 snprintf(instruction
->text
,
2098 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDIV\t$D%d,$r%d,$r%d",
2100 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2101 instruction
->info
.rb
);
2104 case 49: { /* MULT32 */
2106 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2107 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2108 instruction
->type
= NDS32_INSN_DATA_PROC
;
2109 snprintf(instruction
->text
,
2111 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMULT32\t$D%d,$r%d,$r%d",
2113 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2114 instruction
->info
.rb
);
2117 case 51: { /* MADD32 */
2119 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2120 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2121 instruction
->type
= NDS32_INSN_DATA_PROC
;
2122 snprintf(instruction
->text
,
2124 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMADD32\t$D%d,$r%d,$r%d",
2126 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2127 instruction
->info
.rb
);
2130 case 53: { /* MSUB32 */
2132 nds32_parse_type_3(opcode
, &dt_val
, &(instruction
->info
.ra
),
2133 &(instruction
->info
.rb
), &(instruction
->info
.imm
));
2134 instruction
->type
= NDS32_INSN_DATA_PROC
;
2135 snprintf(instruction
->text
,
2137 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMSUB32\t$D%d,$r%d,$r%d",
2139 opcode
, (dt_val
>> 1) & 0x1, instruction
->info
.ra
,
2140 instruction
->info
.rb
);
2144 snprintf(instruction
->text
,
2146 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
2155 static int nds32_parse_group_4_insn(struct nds32
*nds32
, uint32_t opcode
,
2156 uint32_t address
, struct nds32_instruction
*instruction
)
2160 opc_6
= instruction
->info
.opc_6
;
2162 switch (opc_6
& 0x7) {
2164 nds32_parse_alu_1(opcode
, address
, instruction
);
2167 nds32_parse_alu_2(opcode
, address
, instruction
);
2170 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2171 &(instruction
->info
.imm
));
2173 instruction
->info
.imm
= (instruction
->info
.imm
<< 12) >> 12;
2174 instruction
->type
= NDS32_INSN_DATA_PROC
;
2175 snprintf(instruction
->text
,
2177 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMOVI\t$r%d,#%d",
2179 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2182 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2183 &(instruction
->info
.imm
));
2184 instruction
->type
= NDS32_INSN_DATA_PROC
;
2185 snprintf(instruction
->text
,
2187 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSETHI\t$r%d,0x%8.8" PRIx32
,
2189 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2192 nds32_parse_type_0(opcode
, &(instruction
->info
.imm
));
2194 instruction
->info
.imm
= (instruction
->info
.imm
<< 8) >> 8;
2195 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
2196 if ((instruction
->info
.imm
>> 24) & 0x1) { /* JAL */
2197 snprintf(instruction
->text
,
2199 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tJAL\t#%d",
2201 opcode
, instruction
->info
.imm
);
2203 snprintf(instruction
->text
,
2205 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tJ\t#%d",
2207 opcode
, instruction
->info
.imm
);
2210 case 5: { /* JREG */
2212 nds32_parse_type_0(opcode
, &imm
);
2213 instruction
->info
.rb
= (imm
>> 10) & 0x1F;
2214 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
2215 switch (imm
& 0x1F) {
2218 if (imm
& 0x20) { /* RET */
2219 snprintf(instruction
->text
,
2221 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tRET\t$r%d",
2223 opcode
, instruction
->info
.rb
);
2225 snprintf(instruction
->text
,
2227 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tJR\t$r%d",
2229 opcode
, instruction
->info
.rb
);
2233 instruction
->info
.rt
= (imm
>> 20) & 0x1F;
2234 snprintf(instruction
->text
,
2236 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tJRAL\t$r%d,$r%d",
2238 opcode
, instruction
->info
.rt
, instruction
->info
.rb
);
2241 snprintf(instruction
->text
,
2243 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tJRNEZ\t$r%d",
2245 opcode
, instruction
->info
.rb
);
2247 case 3: /* JRALNEZ */
2248 instruction
->info
.rt
= (imm
>> 20) & 0x1F;
2249 if (instruction
->info
.rt
== R30
)
2250 snprintf(instruction
->text
,
2252 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tJRALNEZ\t$r%d",
2254 opcode
, instruction
->info
.rb
);
2256 snprintf(instruction
->text
,
2258 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
2259 "\tJRALNEZ\t$r%d,$r%d",
2262 instruction
->info
.rt
,
2263 instruction
->info
.rb
);
2271 nds32_parse_type_0(opcode
, &imm
);
2272 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
2273 if ((imm
>> 14) & 0x1) { /* BNE */
2274 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2275 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2277 instruction
->info
.imm
= (instruction
->info
.imm
<< 18) >> 18;
2278 snprintf(instruction
->text
,
2280 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBNE\t$r%d,$r%d,#%d",
2282 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2283 instruction
->info
.imm
);
2285 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2286 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2288 instruction
->info
.imm
= (instruction
->info
.imm
<< 18) >> 18;
2289 snprintf(instruction
->text
,
2291 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBEQ\t$r%d,$r%d,#%d",
2293 opcode
, instruction
->info
.rt
,
2294 instruction
->info
.ra
,
2295 instruction
->info
.imm
);
2302 nds32_parse_type_0(opcode
, &imm
);
2303 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
2304 switch ((imm
>> 16) & 0xF) {
2306 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2307 &(instruction
->info
.imm
));
2308 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2309 snprintf(instruction
->text
,
2311 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBEQZ\t$r%d,#%d",
2313 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2316 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2317 &(instruction
->info
.imm
));
2318 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2319 snprintf(instruction
->text
,
2321 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBNEZ\t$r%d,#%d",
2323 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2326 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2327 &(instruction
->info
.imm
));
2328 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2329 snprintf(instruction
->text
,
2331 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBGEZ\t$r%d,#%d",
2333 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2336 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2337 &(instruction
->info
.imm
));
2338 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2339 snprintf(instruction
->text
,
2341 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBLTZ\t$r%d,#%d",
2343 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2346 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2347 &(instruction
->info
.imm
));
2348 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2349 snprintf(instruction
->text
,
2351 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBGTZ\t$r%d,#%d",
2353 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2356 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2357 &(instruction
->info
.imm
));
2358 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2359 snprintf(instruction
->text
,
2361 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBLEZ\t$r%d,#%d",
2363 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2365 case 12: /* BGEZAL */
2366 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2367 &(instruction
->info
.imm
));
2368 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2369 snprintf(instruction
->text
,
2371 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBGEZAL\t$r%d,#%d",
2373 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2375 case 13: /* BLTZAL */
2376 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2377 &(instruction
->info
.imm
));
2378 instruction
->info
.imm
= (instruction
->info
.imm
<< 16) >> 16;
2379 snprintf(instruction
->text
,
2381 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBLTZAL\t$r%d,#%d",
2383 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2389 snprintf(instruction
->text
,
2391 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
2400 static int nds32_parse_group_5_insn(struct nds32
*nds32
, uint32_t opcode
,
2401 uint32_t address
, struct nds32_instruction
*instruction
)
2405 opc_6
= instruction
->info
.opc_6
;
2407 switch (opc_6
& 0x7) {
2409 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2410 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2411 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
2412 instruction
->type
= NDS32_INSN_DATA_PROC
;
2413 snprintf(instruction
->text
,
2415 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tADDI\t$r%d,$r%d,#%d",
2417 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2418 instruction
->info
.imm
);
2421 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2422 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2423 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
2424 instruction
->type
= NDS32_INSN_DATA_PROC
;
2425 snprintf(instruction
->text
,
2427 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSUBRI\t$r%d,$r%d,#%d",
2429 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2430 instruction
->info
.imm
);
2433 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2434 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2435 instruction
->type
= NDS32_INSN_DATA_PROC
;
2436 snprintf(instruction
->text
,
2438 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tANDI\t$r%d,$r%d,#%d",
2440 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2441 instruction
->info
.imm
);
2444 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2445 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2446 instruction
->type
= NDS32_INSN_DATA_PROC
;
2447 snprintf(instruction
->text
,
2449 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tXORI\t$r%d,$r%d,#%d",
2451 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2452 instruction
->info
.imm
);
2455 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2456 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2457 instruction
->type
= NDS32_INSN_DATA_PROC
;
2458 snprintf(instruction
->text
,
2460 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tORI\t$r%d,$r%d,0x%8.8" PRIx32
,
2462 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2463 instruction
->info
.imm
);
2466 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2467 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2468 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
2469 instruction
->type
= NDS32_INSN_DATA_PROC
;
2470 snprintf(instruction
->text
,
2472 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSLTI\t$r%d,$r%d,#%d",
2474 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2475 instruction
->info
.imm
);
2478 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2479 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2480 instruction
->info
.imm
= (instruction
->info
.imm
<< 17) >> 17; /* sign-extend */
2481 instruction
->type
= NDS32_INSN_DATA_PROC
;
2482 snprintf(instruction
->text
,
2484 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSLTSI\t$r%d,$r%d,#%d",
2486 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2487 instruction
->info
.imm
);
2490 snprintf(instruction
->text
,
2492 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
2501 static int nds32_parse_group_6_insn(struct nds32
*nds32
, uint32_t opcode
,
2502 uint32_t address
, struct nds32_instruction
*instruction
)
2506 opc_6
= instruction
->info
.opc_6
;
2508 switch (opc_6
& 0x7) {
2509 case 2: { /* MISC */
2513 nds32_parse_type_0(opcode
, &imm
);
2515 sub_opc
= imm
& 0x1F;
2517 case 0: /* STANDBY */
2518 instruction
->type
= NDS32_INSN_MISC
;
2519 snprintf(instruction
->text
,
2521 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSTANDBY\t#%d",
2523 opcode
, (opcode
>> 5) & 0x3);
2527 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2528 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2529 instruction
->type
= NDS32_INSN_MISC
;
2530 snprintf(instruction
->text
,
2532 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tCCTL",
2537 nds32_parse_type_1(opcode
, &(instruction
->info
.rt
),
2538 &(instruction
->info
.imm
));
2539 instruction
->type
= NDS32_INSN_RESOURCE_ACCESS
;
2540 snprintf(instruction
->text
,
2542 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMFSR\t$r%d,#%d",
2544 opcode
, instruction
->info
.rt
,
2545 (instruction
->info
.imm
>> 10) & 0x3FF);
2548 nds32_parse_type_1(opcode
, &(instruction
->info
.ra
),
2549 &(instruction
->info
.imm
));
2550 instruction
->type
= NDS32_INSN_RESOURCE_ACCESS
;
2551 snprintf(instruction
->text
,
2553 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMTSR\t$r%d,#%d",
2555 opcode
, instruction
->info
.ra
,
2556 (instruction
->info
.imm
>> 10) & 0x3FF);
2559 instruction
->type
= NDS32_INSN_MISC
;
2560 snprintf(instruction
->text
,
2562 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tIRET",
2567 instruction
->type
= NDS32_INSN_MISC
;
2568 snprintf(instruction
->text
,
2570 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tTRAP\t#%d",
2572 opcode
, (imm
>> 5) & 0x7FFF);
2575 nds32_parse_type_1(opcode
, &(instruction
->info
.ra
),
2576 &(instruction
->info
.imm
));
2577 instruction
->type
= NDS32_INSN_MISC
;
2578 snprintf(instruction
->text
,
2580 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tTEQZ\t$r%d,#%d",
2582 opcode
, instruction
->info
.ra
,
2583 (instruction
->info
.imm
>> 5) & 0x7FFF);
2586 nds32_parse_type_1(opcode
, &(instruction
->info
.ra
),
2587 &(instruction
->info
.imm
));
2588 instruction
->type
= NDS32_INSN_MISC
;
2589 snprintf(instruction
->text
,
2591 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tTNEZ\t$r%d,#%d",
2593 opcode
, instruction
->info
.ra
,
2594 (instruction
->info
.imm
>> 5) & 0x7FFF);
2597 instruction
->type
= NDS32_INSN_MISC
;
2598 snprintf(instruction
->text
,
2600 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tDSB",
2605 instruction
->type
= NDS32_INSN_MISC
;
2606 snprintf(instruction
->text
,
2608 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tISB",
2612 case 10: /* BREAK */
2613 instruction
->type
= NDS32_INSN_MISC
;
2614 instruction
->info
.sub_opc
= imm
& 0x1F;
2615 instruction
->info
.imm
= (imm
>> 5) & 0x7FFF;
2616 snprintf(instruction
->text
,
2618 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tBREAK\t#%d",
2620 opcode
, instruction
->info
.imm
);
2622 case 11: /* SYSCALL */
2623 instruction
->type
= NDS32_INSN_MISC
;
2624 snprintf(instruction
->text
,
2626 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSYSCALL\t#%d",
2628 opcode
, (imm
>> 5) & 0x7FFF);
2630 case 12: /* MSYNC */
2631 instruction
->type
= NDS32_INSN_MISC
;
2632 snprintf(instruction
->text
,
2634 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tMSYNC\t#%d",
2636 opcode
, (imm
>> 5) & 0x7);
2638 case 13: /* ISYNC */
2639 nds32_parse_type_1(opcode
, &(instruction
->info
.ra
),
2640 &(instruction
->info
.imm
));
2641 instruction
->type
= NDS32_INSN_MISC
;
2642 snprintf(instruction
->text
,
2644 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tISYNC\t$r%d",
2646 opcode
, instruction
->info
.ra
);
2648 case 14: /* TLBOP */
2650 nds32_parse_type_2(opcode
, &(instruction
->info
.rt
),
2651 &(instruction
->info
.ra
), &(instruction
->info
.imm
));
2652 instruction
->type
= NDS32_INSN_RESOURCE_ACCESS
;
2653 snprintf(instruction
->text
,
2655 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tTLBOP",
2664 snprintf(instruction
->text
,
2666 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
2675 static uint32_t field_mask
[9] = {
2687 static uint8_t nds32_extract_field_8u(uint16_t opcode
, uint32_t start
, uint32_t length
)
2689 if (0 < length
&& length
< 9)
2690 return (opcode
>> start
) & field_mask
[length
];
2695 static int nds32_parse_group_0_insn_16(struct nds32
*nds32
, uint16_t opcode
,
2696 uint32_t address
, struct nds32_instruction
*instruction
)
2698 switch ((opcode
>> 10) & 0x7) {
2700 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 5);
2701 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 0, 5);
2702 instruction
->type
= NDS32_INSN_MISC
;
2703 snprintf(instruction
->text
,
2705 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tMOV55\t$r%d,$r%d",
2707 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2709 case 1: /* MOVI55 */
2710 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 5);
2711 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
2712 instruction
->info
.imm
= (instruction
->info
.imm
<< 27) >> 27;
2713 instruction
->type
= NDS32_INSN_MISC
;
2714 snprintf(instruction
->text
,
2716 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tMOVI55\t$r%d,#%d",
2718 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2720 case 2: /* ADD45, SUB45 */
2721 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
2722 instruction
->info
.rb
= nds32_extract_field_8u(opcode
, 0, 5);
2723 instruction
->type
= NDS32_INSN_DATA_PROC
;
2724 if (nds32_extract_field_8u(opcode
, 9, 1) == 0) { /* ADD45 */
2725 snprintf(instruction
->text
,
2727 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADD45\t$r%d,$r%d",
2729 opcode
, instruction
->info
.rt
, instruction
->info
.rb
);
2730 } else { /* SUB45 */
2731 snprintf(instruction
->text
,
2733 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSUB45\t$r%d,$r%d",
2735 opcode
, instruction
->info
.rt
, instruction
->info
.rb
);
2739 case 3: /* ADDI45, SUBI45 */
2740 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
2741 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
2742 instruction
->type
= NDS32_INSN_DATA_PROC
;
2743 if (nds32_extract_field_8u(opcode
, 9, 1) == 0) { /* ADDI45 */
2744 snprintf(instruction
->text
,
2746 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADDI45\t$r%d,#%d",
2748 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2749 } else { /* SUBI45 */
2750 snprintf(instruction
->text
,
2752 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSUBI45\t$r%d,#%d",
2754 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2757 case 4: /* SRAI45, SRLI45 */
2758 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
2759 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
2760 instruction
->type
= NDS32_INSN_DATA_PROC
;
2761 if (nds32_extract_field_8u(opcode
, 9, 1) == 0) { /* SRAI45 */
2762 snprintf(instruction
->text
,
2764 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSRAI45\t$r%d,#%d",
2766 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2767 } else { /* SRLI45 */
2768 if ((instruction
->info
.rt
== 0) && (instruction
->info
.imm
== 0)) {
2769 snprintf(instruction
->text
,
2771 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tNOP",
2775 snprintf(instruction
->text
,
2777 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSRLI45\t$r%d,#%d",
2779 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2784 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2785 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2786 instruction
->type
= NDS32_INSN_DATA_PROC
;
2787 if (nds32_extract_field_8u(opcode
, 9, 1) == 0) { /* SLLI333 */
2788 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3);
2789 snprintf(instruction
->text
,
2791 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSLLI333\t$r%d,$r%d,#%d",
2793 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2794 instruction
->info
.imm
);
2796 instruction
->info
.sub_opc
= nds32_extract_field_8u(opcode
, 0, 3);
2797 switch (instruction
->info
.sub_opc
) {
2799 snprintf(instruction
->text
,
2801 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tZEB33\t$r%d,$r%d",
2803 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2806 snprintf(instruction
->text
,
2808 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tZEH33\t$r%d,$r%d",
2810 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2813 snprintf(instruction
->text
,
2815 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSEB33\t$r%d,$r%d",
2817 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2820 snprintf(instruction
->text
,
2822 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSEH33\t$r%d,$r%d",
2824 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2826 case 4: /* XLSB33 */
2827 snprintf(instruction
->text
,
2829 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tXLSB33\t$r%d,$r%d",
2831 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2833 case 5: /* XLLB33 */
2834 snprintf(instruction
->text
,
2836 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tXLLB33\t$r%d,$r%d",
2838 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
2840 case 6: /* BMSKI33 */
2841 instruction
->info
.ra
= 0;
2842 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 3, 3);
2843 snprintf(instruction
->text
,
2845 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBMSKI33\t$r%d,$r%d",
2847 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2849 case 7: /* FEXTI33 */
2850 instruction
->info
.ra
= 0;
2851 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 3, 3);
2852 snprintf(instruction
->text
,
2854 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tFEXTI33\t$r%d,$r%d",
2856 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
2859 snprintf(instruction
->text
,
2861 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
2862 "\tUNDEFINED INSTRUCTION",
2869 case 6: /* ADD333, SUB333 */
2870 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2871 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2872 instruction
->info
.rb
= nds32_extract_field_8u(opcode
, 0, 3);
2873 instruction
->type
= NDS32_INSN_DATA_PROC
;
2874 if (nds32_extract_field_8u(opcode
, 9, 1) == 0) { /* ADD333 */
2875 snprintf(instruction
->text
,
2877 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADD333\t$r%d,$r%d,$r%d",
2879 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2880 instruction
->info
.rb
);
2881 } else { /* SUB333 */
2882 snprintf(instruction
->text
,
2884 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSUB333\t$r%d,$r%d,$r%d",
2886 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2887 instruction
->info
.rb
);
2890 case 7: /* ADDI333, SUBI333 */
2891 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2892 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2893 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3);
2894 instruction
->type
= NDS32_INSN_DATA_PROC
;
2895 if (nds32_extract_field_8u(opcode
, 9, 1) == 0) { /* ADDI333 */
2896 snprintf(instruction
->text
,
2898 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADDI333\t$r%d,$r%d,#%d",
2900 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2901 instruction
->info
.imm
);
2902 } else { /* SUBI333 */
2903 snprintf(instruction
->text
,
2905 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSUBI333\t$r%d,$r%d,#%d",
2907 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2908 instruction
->info
.imm
);
2912 snprintf(instruction
->text
,
2914 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
2923 static int nds32_parse_group_1_insn_16(struct nds32
*nds32
, uint16_t opcode
,
2924 uint32_t address
, struct nds32_instruction
*instruction
)
2926 switch ((opcode
>> 9) & 0xF) {
2927 case 0: /* LWI333 */
2928 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2929 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2930 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3) << 2;
2931 instruction
->type
= NDS32_INSN_LOAD_STORE
;
2932 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
2933 &(instruction
->access_start
));
2934 instruction
->access_start
+= instruction
->info
.imm
;
2935 instruction
->access_end
= instruction
->access_start
+ 4;
2936 snprintf(instruction
->text
,
2938 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLWI333\t$r%d,[$r%d+(#%d)]",
2940 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2941 instruction
->info
.imm
);
2943 case 1: /* LWI333.BI */
2944 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2945 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2946 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3);
2947 instruction
->type
= NDS32_INSN_LOAD_STORE
;
2948 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
2949 &(instruction
->access_start
));
2950 instruction
->access_end
= instruction
->access_start
+ 4;
2951 snprintf(instruction
->text
,
2953 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLWI333.BI\t$r%d,[$r%d],#%d",
2955 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2956 instruction
->info
.imm
<< 2);
2958 case 2: /* LHI333 */
2959 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2960 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2961 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3) << 1;
2962 instruction
->type
= NDS32_INSN_LOAD_STORE
;
2963 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
2964 &(instruction
->access_start
));
2965 instruction
->access_start
+= instruction
->info
.imm
;
2966 instruction
->access_end
= instruction
->access_start
+ 2;
2967 snprintf(instruction
->text
,
2969 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLHI333\t$r%d,[$r%d+(#%d)]",
2971 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2972 instruction
->info
.imm
);
2974 case 3: /* LBI333 */
2975 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2976 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2977 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3);
2978 instruction
->type
= NDS32_INSN_LOAD_STORE
;
2979 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
2980 &(instruction
->access_start
));
2981 instruction
->access_start
+= instruction
->info
.imm
;
2982 instruction
->access_end
= instruction
->access_start
+ 1;
2983 snprintf(instruction
->text
,
2985 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLBI333\t$r%d,[$r%d+(#%d)]",
2987 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
2988 instruction
->info
.imm
);
2990 case 4: /* SWI333 */
2991 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
2992 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
2993 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3) << 2;
2994 instruction
->type
= NDS32_INSN_LOAD_STORE
;
2995 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
2996 &(instruction
->access_start
));
2997 instruction
->access_start
+= instruction
->info
.imm
;
2998 instruction
->access_end
= instruction
->access_start
+ 4;
2999 snprintf(instruction
->text
,
3001 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSWI333\t$r%d,[$r%d+(#%d)]",
3003 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
3004 instruction
->info
.imm
);
3006 case 5: /* SWI333.BI */
3007 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
3008 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
3009 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3) << 2;
3010 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3011 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
3012 &(instruction
->access_start
));
3013 instruction
->access_end
= instruction
->access_start
+ 4;
3014 snprintf(instruction
->text
,
3016 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSWI333.BI\t$r%d,[$r%d],#%d",
3018 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
3019 instruction
->info
.imm
);
3021 case 6: /* SHI333 */
3022 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
3023 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
3024 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3) << 1;
3025 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3026 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
3027 &(instruction
->access_start
));
3028 instruction
->access_start
+= instruction
->info
.imm
;
3029 instruction
->access_end
= instruction
->access_start
+ 2;
3030 snprintf(instruction
->text
,
3032 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSHI333\t$r%d,[$r%d+(#%d)]",
3034 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
3035 instruction
->info
.imm
);
3037 case 7: /* SBI333 */
3038 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
3039 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
3040 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 3);
3041 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3042 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
3043 &(instruction
->access_start
));
3044 instruction
->access_start
+= instruction
->info
.imm
;
3045 instruction
->access_end
= instruction
->access_start
+ 1;
3046 snprintf(instruction
->text
,
3048 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSHI333\t$r%d,[$r%d+(#%d)]",
3050 opcode
, instruction
->info
.rt
, instruction
->info
.ra
,
3051 instruction
->info
.imm
);
3053 case 8: /* ADDRI36.SP */
3054 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
3055 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 6) << 2;
3056 instruction
->type
= NDS32_INSN_DATA_PROC
;
3057 snprintf(instruction
->text
,
3059 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADDRI36.SP\t$r%d,#%d",
3061 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3063 case 9: /* LWI45.FE */
3064 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
3065 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
3066 instruction
->info
.imm
-= 32;
3067 instruction
->info
.imm
<<= 2;
3068 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3069 nds32_get_mapped_reg(nds32
, R8
, &(instruction
->access_start
));
3070 instruction
->access_start
+= instruction
->info
.imm
;
3071 instruction
->access_end
= instruction
->access_start
+ 4;
3072 snprintf(instruction
->text
,
3074 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLWI45.FE\t$r%d,[#%d]",
3076 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3078 case 10: /* LWI450 */
3079 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
3080 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 0, 5);
3081 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3082 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
3083 &(instruction
->access_start
));
3084 instruction
->access_end
= instruction
->access_start
+ 4;
3085 snprintf(instruction
->text
,
3087 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLWI450\t$r%d,$r%d",
3089 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3091 case 11: /* SWI450 */
3092 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
3093 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 0, 5);
3094 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3095 nds32_get_mapped_reg(nds32
, instruction
->info
.ra
,
3096 &(instruction
->access_start
));
3097 instruction
->access_end
= instruction
->access_start
+ 4;
3098 snprintf(instruction
->text
,
3100 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSWI450\t$r%d,$r%d",
3102 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3107 case 15: /* LWI37, SWI37 */
3108 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 8, 3);
3109 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 7) << 2;
3110 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3111 nds32_get_mapped_reg(nds32
, R28
, &(instruction
->access_start
));
3112 instruction
->access_start
+= instruction
->info
.imm
;
3113 instruction
->access_end
= instruction
->access_start
+ 4;
3114 if (nds32_extract_field_8u(opcode
, 7, 1) == 0) { /* LWI37 */
3115 snprintf(instruction
->text
,
3117 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLWI37\t$r%d,[fp+#%d]",
3119 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3120 } else { /* SWI37 */
3121 snprintf(instruction
->text
,
3123 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSWI37\t$r%d,[fp+#%d]",
3125 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3128 default: /* ERROR */
3129 snprintf(instruction
->text
,
3131 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
3140 static int nds32_parse_group_2_insn_16(struct nds32
*nds32
, uint16_t opcode
,
3141 uint32_t address
, struct nds32_instruction
*instruction
)
3143 switch ((opcode
>> 11) & 0x3) {
3144 case 0: /* BEQZ38 */
3145 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 8, 3);
3146 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 8);
3147 instruction
->info
.imm
= (instruction
->info
.imm
<< 24) >> 24;
3148 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
3149 snprintf(instruction
->text
,
3151 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBEQZ38\t$r%d,#%d",
3153 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3155 case 1: /* BNEZ38 */
3156 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 8, 3);
3157 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 8);
3158 instruction
->info
.imm
= (instruction
->info
.imm
<< 24) >> 24;
3159 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
3160 snprintf(instruction
->text
,
3162 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBNEZ38\t$r%d,#%d",
3164 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3166 case 2: /* BEQS38,J8 */
3167 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 8, 3);
3168 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 8);
3169 instruction
->info
.imm
= (instruction
->info
.imm
<< 24) >> 24;
3170 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
3171 if (instruction
->info
.rt
== 5) { /* J8 */
3172 snprintf(instruction
->text
,
3174 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tJ8\t#%d",
3176 opcode
, instruction
->info
.imm
);
3177 } else { /* BEQS38 */
3178 snprintf(instruction
->text
,
3180 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBEQS38\t$r%d,#%d",
3182 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3185 case 3: /* BNES38, JR5, RET5, JRAL5 */
3186 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 8, 3);
3187 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 8);
3188 instruction
->info
.imm
= (instruction
->info
.imm
<< 24) >> 24;
3189 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
3190 if (instruction
->info
.rt
== 5) {
3191 instruction
->info
.imm
= 0;
3192 instruction
->info
.rb
= nds32_extract_field_8u(opcode
, 0, 5);
3193 switch (nds32_extract_field_8u(opcode
, 5, 3)) {
3195 snprintf(instruction
->text
,
3197 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tJR5\t$r%d",
3199 opcode
, instruction
->info
.rb
);
3202 snprintf(instruction
->text
,
3204 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tJRAL5\t$r%d",
3206 opcode
, instruction
->info
.rb
);
3208 case 2: /* EX9.IT */
3209 instruction
->info
.rb
= 0;
3210 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
3211 /* TODO: implement real instruction semantics */
3212 snprintf(instruction
->text
,
3214 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tEX9.IT\t#%d",
3216 opcode
, instruction
->info
.imm
);
3219 snprintf(instruction
->text
,
3221 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tRET5\t$r%d",
3223 opcode
, instruction
->info
.rb
);
3225 case 5: /* ADD5.PC */
3226 instruction
->info
.rt
= 0;
3227 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 0, 5);
3228 instruction
->type
= NDS32_INSN_DATA_PROC
;
3229 snprintf(instruction
->text
,
3231 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADD5.PC\t$r%d",
3233 opcode
, instruction
->info
.rt
);
3236 snprintf(instruction
->text
,
3238 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
3239 "\tUNDEFINED INSTRUCTION",
3244 } else { /* BNES38 */
3245 snprintf(instruction
->text
,
3247 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBNES38\t$r%d,#%d",
3249 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3257 static int nds32_parse_group_3_insn_16(struct nds32
*nds32
, uint16_t opcode
,
3258 uint32_t address
, struct nds32_instruction
*instruction
)
3260 switch ((opcode
>> 11) & 0x3) {
3262 switch ((opcode
>> 9) & 0x3) {
3263 case 0: /* SLTS45 */
3264 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 5, 4);
3265 instruction
->info
.rb
= nds32_extract_field_8u(opcode
, 0, 5);
3266 instruction
->type
= NDS32_INSN_DATA_PROC
;
3267 snprintf(instruction
->text
,
3269 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSLTS45\t$r%d,$r%d",
3271 opcode
, instruction
->info
.ra
, instruction
->info
.rb
);
3274 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 5, 4);
3275 instruction
->info
.rb
= nds32_extract_field_8u(opcode
, 0, 5);
3276 instruction
->type
= NDS32_INSN_DATA_PROC
;
3277 snprintf(instruction
->text
,
3279 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSLT45\t$r%d,$r%d",
3281 opcode
, instruction
->info
.ra
, instruction
->info
.rb
);
3283 case 2: /* SLTSI45 */
3284 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 5, 4);
3285 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
3286 instruction
->type
= NDS32_INSN_DATA_PROC
;
3287 snprintf(instruction
->text
,
3289 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSLTSI45\t$r%d,#%d",
3291 opcode
, instruction
->info
.ra
, instruction
->info
.imm
);
3293 case 3: /* SLTI45 */
3294 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 5, 4);
3295 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5);
3296 instruction
->type
= NDS32_INSN_DATA_PROC
;
3297 snprintf(instruction
->text
,
3299 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSLTI45\t$r%d,#%d",
3301 opcode
, instruction
->info
.ra
, instruction
->info
.imm
);
3306 switch ((opcode
>> 9) & 0x3) {
3308 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 8);
3309 instruction
->info
.imm
= (instruction
->info
.imm
<< 24) >> 24;
3310 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
3311 if (nds32_extract_field_8u(opcode
, 8, 1) == 0) { /* BEQZS8 */
3312 snprintf(instruction
->text
,
3314 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBEQZS8\t#%d",
3316 opcode
, instruction
->info
.imm
);
3317 } else { /* BNEZS8 */
3318 snprintf(instruction
->text
,
3320 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBNEZS8\t#%d",
3322 opcode
, instruction
->info
.imm
);
3325 case 1: /* BREAK16 */
3326 if (((opcode
>> 5) & 0xF) == 0) {
3327 instruction
->type
= NDS32_INSN_MISC
;
3328 snprintf(instruction
->text
,
3330 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tBREAK16\t#%d",
3332 opcode
, opcode
& 0x1F);
3333 } else { /* EX9.IT */
3334 instruction
->type
= NDS32_INSN_MISC
;
3335 /* TODO: implement real instruction semantics */
3336 snprintf(instruction
->text
,
3338 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tEX9.IT\t#%d",
3340 opcode
, opcode
& 0x1FF);
3343 case 2: /* ADDI10S */
3345 instruction
->info
.imm
= opcode
& 0x3FF;
3346 instruction
->info
.imm
= (instruction
->info
.imm
<< 22) >> 22;
3347 instruction
->type
= NDS32_INSN_DATA_PROC
;
3348 snprintf(instruction
->text
,
3350 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tADDI10.SP\t#%d",
3352 opcode
, instruction
->info
.imm
);
3357 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 8, 3);
3358 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 7) << 2;
3359 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3360 nds32_get_mapped_reg(nds32
, R31
, &(instruction
->access_start
));
3361 instruction
->access_start
+= instruction
->info
.imm
;
3362 instruction
->access_end
= instruction
->access_start
+ 4;
3363 if (nds32_extract_field_8u(opcode
, 7, 1) == 0) { /* LWI37.SP */
3364 snprintf(instruction
->text
,
3366 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tLWI37.SP\t$r%d,[+#%d]",
3368 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3369 } else { /* SWI37.SP */
3370 snprintf(instruction
->text
,
3372 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tSWI37.SP\t$r%d,[+#%d]",
3374 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3378 switch ((opcode
>> 9) & 0x3) {
3379 case 0: /* IFCALL9 */
3380 instruction
->info
.imm
= opcode
& 0x1FF;
3381 instruction
->type
= NDS32_INSN_JUMP_BRANCH
;
3382 snprintf(instruction
->text
,
3384 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tIFCALL9\t#%d",
3386 opcode
, instruction
->info
.imm
);
3388 case 1: /* MOVPI45 */
3389 instruction
->info
.imm
= nds32_extract_field_8u(opcode
, 0, 5) + 16;
3390 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 5, 4);
3391 instruction
->type
= NDS32_INSN_MISC
;
3392 snprintf(instruction
->text
,
3394 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
"\t\tMOVPI45\t$r%d,#%d",
3396 opcode
, instruction
->info
.rt
, instruction
->info
.imm
);
3398 case 2: /* PUSH25, POP25, MOVD44 */
3399 switch ((opcode
>> 7) & 0x3) {
3400 case 0: /* PUSH25 */
3405 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3406 instruction
->info
.imm
=
3407 nds32_extract_field_8u(opcode
, 0, 5) << 3;
3408 re
= nds32_extract_field_8u(opcode
, 5, 2);
3419 instruction
->info
.rd
= re
;
3420 /* GPRs list: R6 ~ Re and fp, gp, lp */
3421 gpr_count
= 3 + (re
- 5);
3423 nds32_get_mapped_reg(nds32
, R31
,
3424 &(instruction
->access_end
));
3425 instruction
->access_start
=
3426 instruction
->access_end
- (gpr_count
* 4);
3428 snprintf(instruction
->text
,
3430 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3431 "\t\tPUSH25\t$r%d,#%d",
3433 opcode
, instruction
->info
.rd
,
3434 instruction
->info
.imm
);
3442 instruction
->type
= NDS32_INSN_LOAD_STORE
;
3443 instruction
->info
.imm
=
3444 nds32_extract_field_8u(opcode
, 0, 5) << 3;
3445 re
= nds32_extract_field_8u(opcode
, 5, 2);
3456 instruction
->info
.rd
= re
;
3457 /* GPRs list: R6 ~ Re and fp, gp, lp */
3458 gpr_count
= 3 + (re
- 5);
3460 nds32_get_mapped_reg(nds32
, R31
,
3461 &(instruction
->access_start
));
3462 instruction
->access_start
+= instruction
->info
.imm
;
3463 instruction
->access_end
=
3464 instruction
->access_start
+ (gpr_count
* 4);
3466 snprintf(instruction
->text
,
3468 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3469 "\t\tPOP25\t$r%d,#%d",
3471 opcode
, instruction
->info
.rd
,
3472 instruction
->info
.imm
);
3475 case 2: /* MOVD44 */
3477 instruction
->info
.ra
=
3478 nds32_extract_field_8u(opcode
, 0, 4) * 2;
3479 instruction
->info
.rt
=
3480 nds32_extract_field_8u(opcode
, 4, 4) * 2;
3481 instruction
->type
= NDS32_INSN_MISC
;
3482 snprintf(instruction
->text
,
3484 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3485 "\t\tMOVD44\t$r%d,$r%d",
3487 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3491 case 3: /* NEG33, NOT33, MUL33, XOR33, AND33, OR33 */
3492 instruction
->info
.ra
= nds32_extract_field_8u(opcode
, 3, 3);
3493 instruction
->info
.rt
= nds32_extract_field_8u(opcode
, 6, 3);
3494 instruction
->type
= NDS32_INSN_DATA_PROC
;
3495 switch (opcode
& 0x7) {
3497 snprintf(instruction
->text
,
3499 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3500 "\t\tNEG33\t$r%d,$r%d",
3502 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3505 snprintf(instruction
->text
,
3507 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3508 "\t\tNOT33\t$r%d,$r%d",
3510 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3513 snprintf(instruction
->text
,
3515 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3516 "\t\tMUL33\t$r%d,$r%d",
3518 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3521 snprintf(instruction
->text
,
3523 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3524 "\t\tXOR33\t$r%d,$r%d",
3526 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3529 snprintf(instruction
->text
,
3531 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3532 "\t\tAND33\t$r%d,$r%d",
3534 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3537 snprintf(instruction
->text
,
3539 "0x%8.8" PRIx32
"\t0x%4.4" PRIx32
3540 "\t\tOR33\t$r%d,$r%d",
3542 opcode
, instruction
->info
.rt
, instruction
->info
.ra
);
3549 snprintf(instruction
->text
,
3551 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
3560 int nds32_evaluate_opcode(struct nds32
*nds32
, uint32_t opcode
, uint32_t address
,
3561 struct nds32_instruction
*instruction
)
3563 int retval
= ERROR_OK
;
3565 /* clear fields, to avoid confusion */
3566 memset(instruction
, 0, sizeof(struct nds32_instruction
));
3569 /* 16 bits instruction */
3570 instruction
->instruction_size
= 2;
3571 opcode
= (opcode
>> 16) & 0xFFFF;
3572 instruction
->opcode
= opcode
;
3574 switch ((opcode
>> 13) & 0x3) {
3576 retval
= nds32_parse_group_0_insn_16(nds32
, opcode
, address
, instruction
);
3579 retval
= nds32_parse_group_1_insn_16(nds32
, opcode
, address
, instruction
);
3582 retval
= nds32_parse_group_2_insn_16(nds32
, opcode
, address
, instruction
);
3585 retval
= nds32_parse_group_3_insn_16(nds32
, opcode
, address
, instruction
);
3588 snprintf(instruction
->text
,
3590 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",
3596 /* 32 bits instruction */
3597 instruction
->instruction_size
= 4;
3598 instruction
->opcode
= opcode
;
3601 opc_6
= opcode
>> 25;
3602 instruction
->info
.opc_6
= opc_6
;
3604 switch ((opc_6
>> 3) & 0x7) {
3605 case 0: /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
3606 retval
= nds32_parse_group_0_insn(nds32
, opcode
, address
, instruction
);
3608 case 1: /* SBI, SHI, SWI, SBI.bi, SHI.bi, SWI.bi */
3609 retval
= nds32_parse_group_1_insn(nds32
, opcode
, address
, instruction
);
3611 case 2: /* LBSI, LHSI, DPREFI, LBSI.bi, LHSI.bi, LBGP */
3612 retval
= nds32_parse_group_2_insn(nds32
, opcode
, address
, instruction
);
3614 case 3: /* MEM, LSMW, HWGP, SBGP */
3615 retval
= nds32_parse_group_3_insn(nds32
, opcode
, address
, instruction
);
3617 case 4: /* ALU_1, ALU_2, MOVI, SETHI, JI, JREG, BR1, BR2 */
3618 retval
= nds32_parse_group_4_insn(nds32
, opcode
, address
, instruction
);
3620 case 5: /* ADDI, SUBRI, ANDI, XORI, ORI, SLTI, SLTSI */
3621 retval
= nds32_parse_group_5_insn(nds32
, opcode
, address
, instruction
);
3624 retval
= nds32_parse_group_6_insn(nds32
, opcode
, address
, instruction
);
3626 default: /* ERROR */
3627 snprintf(instruction
->text
,
3629 "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tUNDEFINED INSTRUCTION",