1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32c0x family
5 # stm32c0 devices support SWD transports only.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32c0x
19 # Work-area is a space in RAM used for flash programming
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x1800
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
31 # SWD IDCODE (single drop, arm)
32 set _CPUTAPID 0x0bc11477
35 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
36 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
38 set _TARGETNAME $_CHIPNAME.cpu
39 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
43 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
44 flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
49 adapter srst delay 100
54 reset_config srst_nogate
57 # if srst is not fitted use SYSRESETREQ to
58 # perform a soft reset
59 cortex_m reset_config sysresetreq
62 $_TARGETNAME configure -event examine-end {
64 # RCC_APB1ENR |= DBGMCUEN
65 mmw 0x4002103C 0x08000000 0
67 # Enable debug during low power modes (uses more power)
68 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
69 mmw 0x40015804 0x00000006 0
71 # Stop watchdog counters during halt
72 # DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
73 mmw 0x40015808 0x00001800 0