1 # SPDX-License-Identifier: GPL-2.0-or-later
6 reset_config trst_and_srst srst_gates_jtag
10 if { [info exists CHIPNAME] } {
11 set _CHIPNAME $CHIPNAME
16 if { [info exists ENDIAN] } {
22 if { [info exists CPUTAPID] } {
23 set _CPUTAPID $CPUTAPID
25 set _CPUTAPID 0x07b3601d
28 if { [info exists SDMATAPID] } {
29 set _SDMATAPID $SDMATAPID
31 set _SDMATAPID 0x2190101d
34 if { [info exists ETBTAPID] } {
35 set _ETBTAPID $ETBTAPID
37 set _ETBTAPID 0x2b900f0f
40 #========================================
42 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
44 # The "SDMA" - <S>mart <DMA> controller debug tap
45 # Based on some IO pins - this can be disabled & removed
48 # SJC_MOD - controls multiplexer - disables ARM1136
49 # SDMA_BYPASS - disables SDMA -
51 # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
52 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
54 # No IDCODE for this TAP
55 jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
57 # Per section 40.17.1, table 40-85 the IR register is 4 bits
58 # But this conflicts with Diagram 6-13, "3bits ir and drs"
59 jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
61 set _TARGETNAME $_CHIPNAME.cpu
62 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
65 proc power_restore {} { echo "Sensed power restore. No action." }
66 proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
68 # trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
69 etm config $_TARGETNAME 16 normal full etb
70 etb config $_TARGETNAME $_CHIPNAME.etb