1 # SPDX-License-Identifier: GPL-2.0-or-later
4 set CPU_MAX_ADDRESS 0xFFFFFFFF
5 source [find bitsbytes.tcl]
6 source [find memory.tcl]
7 source [find mmr_helpers.tcl]
9 # Common ESP chips definitions
11 # Espressif supports only NuttX in the upstream.
12 # FreeRTOS support is not upstreamed yet.
14 if { [info exists ESP_RTOS] } {
18 # by default current dir (when OOCD has been started)
19 set _SEMIHOST_BASEDIR "."
20 if { [info exists ESP_SEMIHOST_BASEDIR] } {
21 set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR
24 proc set_esp_common_variables { } {
25 global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
26 global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
27 global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
29 # For now we support dual core at most.
30 if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {
31 set _TARGETNAME_0 $_CHIPNAME
33 set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0
37 set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0
38 set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1
39 set _TAPNAME_0 $_TARGETNAME_0
40 set _TAPNAME_1 $_TARGETNAME_1
43 set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable"
44 set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset"
45 set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled"
48 proc create_esp_jtag { } {
49 global _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU
50 jtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID
51 if { $_ONLYCPU != 1 } {
52 jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID
53 } elseif [info exists _CPUNAME_1] {
54 jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID
58 proc create_openocd_targets { } {
59 global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU
61 target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
62 if { $_ONLYCPU != 1 } {
63 target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
64 target smp $_TARGETNAME_0 $_TARGETNAME_1
68 proc create_esp_target { ARCH } {
69 set_esp_common_variables
71 create_openocd_targets
72 configure_openocd_events
74 if { $ARCH == "xtensa"} {
75 configure_esp_xtensa_default_settings
77 # riscv targets are not upstreamed yet.
78 # they can be found at the official Espressif fork.
82 #################### Set event handlers and default settings ####################
84 proc configure_event_examine_end { } {
85 global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
87 $_TARGETNAME_0 configure -event examine-end {
88 # Need to enable to set 'semihosting_basedir'
89 arm semihosting enable
90 arm semihosting_resexit enable
91 if { [info exists _SEMIHOST_BASEDIR] } {
92 if { $_SEMIHOST_BASEDIR != "" } {
93 arm semihosting_basedir $_SEMIHOST_BASEDIR
98 if { $_ONLYCPU != 1 } {
99 $_TARGETNAME_1 configure -event examine-end {
100 # Need to enable to set 'semihosting_basedir'
101 arm semihosting enable
102 arm semihosting_resexit enable
103 if { [info exists _SEMIHOST_BASEDIR] } {
104 if { $_SEMIHOST_BASEDIR != "" } {
105 arm semihosting_basedir $_SEMIHOST_BASEDIR
112 proc configure_event_reset_assert_post { } {
113 global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
115 $_TARGETNAME_0 configure -event reset-assert-post {
116 global _ESP_SOC_RESET
120 if { $_ONLYCPU != 1 } {
121 $_TARGETNAME_1 configure -event reset-assert-post {
122 global _ESP_SOC_RESET
128 proc configure_event_halted { } {
131 $_TARGETNAME_0 configure -event halted {
132 global _ESP_WDT_DISABLE
134 esp halted_event_handler
138 proc configure_event_gdb_attach { } {
139 global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
141 $_TARGETNAME_0 configure -event gdb-attach {
142 if { $_ESP_SMP_BREAK != 0 } {
143 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
145 # necessary to auto-probe flash bank when GDB is connected and generate proper memory map
147 if { [$_ESP_MEMPROT_IS_ENABLED] } {
148 # 'reset halt' to disable memory protection and allow flasher to work correctly
149 echo "Memory protection is enabled. Reset target to disable it..."
154 if { $_ONLYCPU != 1 } {
155 $_TARGETNAME_1 configure -event gdb-attach {
156 if { $_ESP_SMP_BREAK != 0 } {
157 $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
159 # necessary to auto-probe flash bank when GDB is connected
161 if { [$_ESP_MEMPROT_IS_ENABLED] } {
162 # 'reset halt' to disable memory protection and allow flasher to work correctly
163 echo "Memory protection is enabled. Reset target to disable it..."
170 proc configure_openocd_events { } {
171 configure_event_examine_end
172 configure_event_reset_assert_post
173 configure_event_gdb_attach
176 proc configure_esp_xtensa_default_settings { } {
177 global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME
179 $_TARGETNAME_0 xtensa maskisr on
180 if { $_ESP_SMP_BREAK != 0 } {
181 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
184 gdb_breakpoint_override hard
186 if { [info exists _FLASH_VOLTAGE] } {
187 $_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE