tcl/target/c100helper.tcl

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 proc helpC100 {} {
   4     echo "List of useful functions for C100 processor:"
   5     echo "1)  reset init:        will set up your Telo board"
   6     echo "2)  setupNOR:          will setup NOR access"
   7     echo "3)  showNOR:           will show current NOR config registers for 16-bit, 16MB NOR"
   8     echo "4)  setupGPIO:         will setup GPIOs for Telo board"
   9     echo "5)  showGPIO:          will show current GPIO config registers"
  10     echo "6)  highGPIO5:         will set GPIO5=NOR_addr22=1 to access upper 8MB"
  11     echo "7)  lowGPIO5:          will set GPIO5=NOR_addr22=0 to access lower 8MB"
  12     echo "8)  showAmbaClk:       will show current config registers for Amba Bus Clock"
  13     echo "9)  setupAmbaClk:      will setup Amba Bus Clock=165MHz"
  14     echo "10) showArmClk:        will show current config registers for Arm Bus Clock"
  15     echo "11) setupArmClk:       will setup Amba Bus Clock=450MHz"
  16     echo "12) ooma_board_detect: will show which version of Telo you have"
  17     echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configured"
  18     echo "14) showDDR2:          will show DDR2 config registers"
  19     echo "15) showWatchdog:      will show current register config for watchdog"
  20     echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"
  21     echo "17) bootNOR:           will boot Telo from NOR"
  22     echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be configured"
  23     echo "19) putcUART0:         will print a character on UART0"
  24     echo "20) putsUART0:         will print a string on UART0"
  25     echo "21) trainDDR2:         will run DDR2 training program"
  26     echo "22) flashUBOOT:        will program NOR sectors 0-3 with u-boot.bin"
  27 }
  28
  29 source [find mem_helper.tcl]
  30
  31 # read a 64-bit register (memory mapped)
  32 proc mr64bit {reg} {
  33     return [read_memory $reg 32 2]
  34 }
  35
  36
  37 # write a 64-bit register (memory mapped)
  38 proc mw64bit {reg value} {
  39     set high [expr {$value >> 32}]
  40     set low  [expr {$value & 0xffffffff}]
  41     #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
  42     mww $reg $low
  43     mww [expr {$reg+4}] $high
  44 }
  45
  46
  47 proc showNOR {} {
  48     echo "This is the current NOR setup"
  49     set EX_CSEN_REG         [regs EX_CSEN_REG ]
  50     set EX_CS0_SEG_REG      [regs EX_CS0_SEG_REG ]
  51     set EX_CS0_CFG_REG      [regs EX_CS0_CFG_REG ]
  52     set EX_CS0_TMG1_REG     [regs EX_CS0_TMG1_REG ]
  53     set EX_CS0_TMG2_REG     [regs EX_CS0_TMG2_REG ]
  54     set EX_CS0_TMG3_REG     [regs EX_CS0_TMG3_REG ]
  55     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
  56     set EX_MFSM_REG         [regs EX_MFSM_REG ]
  57     set EX_CSFSM_REG        [regs EX_CSFSM_REG ]
  58     set EX_WRFSM_REG        [regs EX_WRFSM_REG ]
  59     set EX_RDFSM_REG        [regs EX_RDFSM_REG ]
  60
  61     echo [format "EX_CSEN_REG      (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
  62     echo [format "EX_CS0_SEG_REG   (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
  63     echo [format "EX_CS0_CFG_REG   (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
  64     echo [format "EX_CS0_TMG1_REG  (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
  65     echo [format "EX_CS0_TMG2_REG  (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
  66     echo [format "EX_CS0_TMG3_REG  (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
  67     echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
  68     echo [format "EX_MFSM_REG      (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
  69     echo [format "EX_CSFSM_REG     (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
  70     echo [format "EX_WRFSM_REG     (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
  71     echo [format "EX_RDFSM_REG     (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
  72 }
  73
  74
  75
  76 proc showGPIO {} {
  77     echo "This is the current GPIO register setup"
  78     # GPIO outputs register
  79     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
  80     # GPIO Output Enable register
  81     set GPIO_OE_REG                 [regs GPIO_OE_REG]
  82     set GPIO_HI_INT_ENABLE_REG      [regs GPIO_HI_INT_ENABLE_REG]
  83     set GPIO_LO_INT_ENABLE_REG      [regs GPIO_LO_INT_ENABLE_REG]
  84     # GPIO input register
  85     set GPIO_INPUT_REG              [regs GPIO_INPUT_REG]
  86     set APB_ACCESS_WS_REG           [regs APB_ACCESS_WS_REG]
  87     set MUX_CONF_REG                [regs MUX_CONF_REG]
  88     set SYSCONF_REG                 [regs SYSCONF_REG]
  89     set GPIO_ARM_ID_REG             [regs GPIO_ARM_ID_REG]
  90     set GPIO_BOOTSTRAP_REG          [regs GPIO_BOOTSTRAP_REG]
  91     set GPIO_LOCK_REG               [regs GPIO_LOCK_REG]
  92     set GPIO_IOCTRL_REG             [regs GPIO_IOCTRL_REG]
  93     set GPIO_DEVID_REG              [regs GPIO_DEVID_REG]
  94
  95     echo [format "GPIO_OUTPUT_REG       (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
  96     echo [format "GPIO_OE_REG           (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
  97     echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
  98     echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
  99     echo [format "GPIO_INPUT_REG        (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
 100     echo [format "APB_ACCESS_WS_REG     (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
 101     echo [format "MUX_CONF_REG          (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
 102     echo [format "SYSCONF_REG           (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
 103     echo [format "GPIO_ARM_ID_REG       (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
 104     echo [format "GPIO_BOOTSTRAP_REG    (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
 105     echo [format "GPIO_LOCK_REG         (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
 106     echo [format "GPIO_IOCTRL_REG       (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
 107     echo [format "GPIO_DEVID_REG        (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
 108 }
 109
 110
 111
 112 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
 113 proc showAmbaClk {} {
 114     set CFG_REFCLKFREQ               [config CFG_REFCLKFREQ]
 115     set CLKCORE_AHB_CLK_CNTRL        [regs CLKCORE_AHB_CLK_CNTRL]
 116     set PLL_CLK_BYPASS               [regs PLL_CLK_BYPASS]
 117
 118     echo [format "CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
 119     set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
 120     # see if the PLL is in bypass mode
 121     set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
 122     echo [format "PLL bypass bit: %d" $bypass]
 123     if {$bypass == 1} {
 124         echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
 125     } else {
 126         # nope, extract x,y,w and compute the PLL output freq.
 127         set x [expr {($value & 0x0001F0000) >> 16}]
 128         echo [format "x: %d" $x]
 129         set y [expr {($value & 0x00000007F)}]
 130         echo [format "y: %d" $y]
 131         set w [expr {($value & 0x000000300) >> 8}]
 132         echo [format "w: %d" $w]
 133         echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
 134     }
 135 }
 136
 137
 138 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
 139 # this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
 140 proc setupAmbaClk {} {
 141     set CLKCORE_PLL_STATUS           [regs CLKCORE_PLL_STATUS]
 142     set CLKCORE_AHB_CLK_CNTRL        [regs CLKCORE_AHB_CLK_CNTRL]
 143     set ARM_PLL_BY_CTRL     [regs ARM_PLL_BY_CTRL]
 144     set ARM_AHB_BYP         [regs ARM_AHB_BYP]
 145     set PLL_DISABLE         [regs PLL_DISABLE]
 146     set PLL_CLK_BYPASS      [regs PLL_CLK_BYPASS]
 147     set AHB_PLL_BY_CTRL     [regs AHB_PLL_BY_CTRL]
 148     set DIV_BYPASS          [regs DIV_BYPASS]
 149     set AHBCLK_PLL_LOCK     [regs AHBCLK_PLL_LOCK]
 150     set CFG_REFCLKFREQ           [config CFG_REFCLKFREQ]
 151     set CONFIG_SYS_HZ_CLOCK      [config CONFIG_SYS_HZ_CLOCK]
 152     set w    [config w_amba]
 153     set x    [config x_amba]
 154     set y    [config y_amba]
 155
 156     echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
 157     #echo [format "setupAmbaClk: w= %d" $w]
 158     #echo [format "setupAmbaClk: x= %d" $x]
 159     #echo [format "setupAmbaClk: y= %d" $y]
 160     # set PLL into BYPASS mode using MUX
 161     mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
 162     # do an internal PLL bypass
 163     mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
 164     # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
 165     # openocd smallest resolution is 1ms so, wait 1ms
 166     sleep 1
 167     # disable the PLL
 168     mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
 169     # wait 1ms
 170     sleep 1
 171     # enable the PLL
 172     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
 173     sleep 1
 174     # set X, W and X
 175     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
 176     mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
 177     # wait for PLL to lock
 178     echo "Waiting for Amba PLL to lock"
 179     while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
 180     # remove the internal PLL bypass
 181     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
 182     # remove PLL from BYPASS mode using MUX
 183     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
 184 }
 185
 186
 187 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
 188 proc showArmClk {} {
 189     set CFG_REFCLKFREQ          [config CFG_REFCLKFREQ]
 190     set CLKCORE_ARM_CLK_CNTRL   [regs CLKCORE_ARM_CLK_CNTRL]
 191     set PLL_CLK_BYPASS          [regs PLL_CLK_BYPASS]
 192
 193     echo [format "CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
 194     set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
 195     # see if the PLL is in bypass mode
 196     set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
 197     echo [format "PLL bypass bit: %d" $bypass]
 198     if {$bypass == 1} {
 199         echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
 200     } else {
 201         # nope, extract x,y,w and compute the PLL output freq.
 202         set x [expr {($value & 0x0001F0000) >> 16}]
 203         echo [format "x: %d" $x]
 204         set y [expr {($value & 0x00000007F)}]
 205         echo [format "y: %d" $y]
 206         set w [expr {($value & 0x000000300) >> 8}]
 207         echo [format "w: %d" $w]
 208         echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
 209     }
 210 }
 211
 212 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
 213 # Arm Clock is used by two ARM1136 cores
 214 proc setupArmClk {} {
 215     set CLKCORE_PLL_STATUS        [regs CLKCORE_PLL_STATUS]
 216     set CLKCORE_ARM_CLK_CNTRL     [regs CLKCORE_ARM_CLK_CNTRL]
 217     set ARM_PLL_BY_CTRL           [regs ARM_PLL_BY_CTRL]
 218     set ARM_AHB_BYP               [regs ARM_AHB_BYP]
 219     set PLL_DISABLE               [regs PLL_DISABLE]
 220     set PLL_CLK_BYPASS            [regs PLL_CLK_BYPASS]
 221     set AHB_PLL_BY_CTRL           [regs AHB_PLL_BY_CTRL]
 222     set DIV_BYPASS                [regs DIV_BYPASS]
 223     set FCLK_PLL_LOCK             [regs FCLK_PLL_LOCK]
 224     set CFG_REFCLKFREQ          [config CFG_REFCLKFREQ]
 225     set CFG_ARM_CLOCK           [config CFG_ARM_CLOCK]
 226     set w    [config w_arm]
 227     set x    [config x_arm]
 228     set y    [config y_arm]
 229
 230     echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
 231     #echo [format "setupArmClk: w= %d" $w]
 232     #echo [format "setupArmaClk: x= %d" $x]
 233     #echo [format "setupArmaClk: y= %d" $y]
 234     # set PLL into BYPASS mode using MUX
 235     mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
 236     # do an internal PLL bypass
 237     mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
 238     # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
 239     # openocd smallest resolution is 1ms so, wait 1ms
 240     sleep 1
 241     # disable the PLL
 242     mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
 243     # wait 1ms
 244     sleep 1
 245     # enable the PLL
 246     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
 247     sleep 1
 248     # set X, W and X
 249     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
 250     mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
 251     # wait for PLL to lock
 252     echo "Waiting for Amba PLL to lock"
 253     while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
 254     # remove the internal PLL bypass
 255     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
 256     # remove PLL from BYPASS mode using MUX
 257     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
 258 }
 259
 260
 261
 262 proc setupPLL {} {
 263     echo "PLLs setup"
 264     setupAmbaClk
 265     setupArmClk
 266 }
 267
 268 # converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
 269 proc setupDDR2 {} {
 270     echo "Configuring DDR2"
 271
 272     set MEMORY_BASE_ADDR            [regs  MEMORY_BASE_ADDR]
 273     set MEMORY_MAX_ADDR             [regs  MEMORY_MAX_ADDR]
 274     set MEMORY_CR                   [regs  MEMORY_CR]
 275     set BLOCK_RESET_REG             [regs  BLOCK_RESET_REG]
 276     set DDR_RST                     [regs  DDR_RST]
 277
 278     # put DDR controller in reset (so that it is reset and correctly configured)
 279     # this is only necessary if DDR was previously confiured
 280     # and not reset.
 281     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
 282
 283     set M [expr {1024 * 1024}]
 284     set DDR_SZ_1024M    [expr {1024 * $M}]
 285     set DDR_SZ_256M     [expr {256 * $M}]
 286     set DDR_SZ_128M     [expr {128 * $M}]
 287     set DDR_SZ_64M      [expr {64 * $M}]
 288     # ooma_board_detect returns DDR2 memory size
 289     set tmp [ooma_board_detect]
 290     if {$tmp == "128M"} {
 291         echo "DDR2 size 128MB"
 292         set ddr_size $DDR_SZ_128M
 293     } elseif {$tmp == "256M"} {
 294         echo "DDR2 size 256MB"
 295         set ddr_size $DDR_SZ_256M
 296     } else {
 297         echo "Don't know how to handle this DDR2 size?"
 298     }
 299
 300     # Memory setup register
 301     mww $MEMORY_MAX_ADDR  [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
 302     # disable ROM remap
 303     mww $MEMORY_CR 0x0
 304     # Take DDR controller out of reset
 305     mmw $BLOCK_RESET_REG $DDR_RST 0x0
 306     # min. 20 ops delay
 307     sleep 1
 308
 309     # This will setup Denali DDR2 controller
 310     if {$tmp == "128M"} {
 311         configureDDR2regs_128M
 312     } elseif {$tmp == "256M"} {
 313         configureDDR2regs_256M
 314     } else {
 315         echo "Don't know how to configure DDR2 setup?"
 316     }
 317 }
 318
 319
 320
 321 proc showDDR2 {} {
 322
 323     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
 324     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
 325     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
 326     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
 327     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
 328     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
 329     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
 330     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
 331     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
 332     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
 333     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
 334     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
 335     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
 336     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
 337     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
 338     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
 339     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
 340     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
 341     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
 342     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
 343     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 344
 345     set tmp [mr64bit $DENALI_CTL_00_DATA]
 346     echo [format "DENALI_CTL_00_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
 347     set tmp [mr64bit $DENALI_CTL_01_DATA]
 348     echo [format "DENALI_CTL_01_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
 349     set tmp [mr64bit $DENALI_CTL_02_DATA]
 350     echo [format "DENALI_CTL_02_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
 351     set tmp [mr64bit $DENALI_CTL_03_DATA]
 352     echo [format "DENALI_CTL_03_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
 353     set tmp [mr64bit $DENALI_CTL_04_DATA]
 354     echo [format "DENALI_CTL_04_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
 355     set tmp [mr64bit $DENALI_CTL_05_DATA]
 356     echo [format "DENALI_CTL_05_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
 357     set tmp [mr64bit $DENALI_CTL_06_DATA]
 358     echo [format "DENALI_CTL_06_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
 359     set tmp [mr64bit $DENALI_CTL_07_DATA]
 360     echo [format "DENALI_CTL_07_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
 361     set tmp [mr64bit $DENALI_CTL_08_DATA]
 362     echo [format "DENALI_CTL_08_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
 363     set tmp [mr64bit $DENALI_CTL_09_DATA]
 364     echo [format "DENALI_CTL_09_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
 365     set tmp [mr64bit $DENALI_CTL_10_DATA]
 366     echo [format "DENALI_CTL_10_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
 367     set tmp [mr64bit $DENALI_CTL_11_DATA]
 368     echo [format "DENALI_CTL_11_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
 369     set tmp [mr64bit $DENALI_CTL_12_DATA]
 370     echo [format "DENALI_CTL_12_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
 371     set tmp [mr64bit $DENALI_CTL_13_DATA]
 372     echo [format "DENALI_CTL_13_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
 373     set tmp [mr64bit $DENALI_CTL_14_DATA]
 374     echo [format "DENALI_CTL_14_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
 375     set tmp [mr64bit $DENALI_CTL_15_DATA]
 376     echo [format "DENALI_CTL_15_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
 377     set tmp [mr64bit $DENALI_CTL_16_DATA]
 378     echo [format "DENALI_CTL_16_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
 379     set tmp [mr64bit $DENALI_CTL_17_DATA]
 380     echo [format "DENALI_CTL_17_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
 381     set tmp [mr64bit $DENALI_CTL_18_DATA]
 382     echo [format "DENALI_CTL_18_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
 383     set tmp [mr64bit $DENALI_CTL_19_DATA]
 384     echo [format "DENALI_CTL_19_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
 385     set tmp [mr64bit $DENALI_CTL_20_DATA]
 386     echo [format "DENALI_CTL_20_DATA   (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
 387
 388 }
 389
 390 proc initC100 {} {
 391     # this follows u-boot/cpu/arm1136/start.S
 392     set GPIO_LOCK_REG               [regs GPIO_LOCK_REG]
 393     set GPIO_IOCTRL_REG             [regs GPIO_IOCTRL_REG]
 394     set GPIO_IOCTRL_VAL             [regs GPIO_IOCTRL_VAL]
 395     set APB_ACCESS_WS_REG           [regs APB_ACCESS_WS_REG]
 396     set ASA_ARAM_BASEADDR           [regs ASA_ARAM_BASEADDR]
 397     set ASA_ARAM_TC_CR_REG          [regs ASA_ARAM_TC_CR_REG]
 398     set ASA_EBUS_BASEADDR           [regs ASA_EBUS_BASEADDR]
 399     set ASA_EBUS_TC_CR_REG          [regs ASA_EBUS_TC_CR_REG]
 400     set ASA_TC_REQIDMAEN            [regs ASA_TC_REQIDMAEN]
 401     set ASA_TC_REQTDMEN             [regs ASA_TC_REQTDMEN]
 402     set ASA_TC_REQIPSECUSBEN        [regs ASA_TC_REQIPSECUSBEN]
 403     set ASA_TC_REQARM0EN            [regs ASA_TC_REQARM0EN]
 404     set ASA_TC_REQARM1EN            [regs ASA_TC_REQARM1EN]
 405     set ASA_TC_REQMDMAEN            [regs ASA_TC_REQMDMAEN]
 406     set INTC_ARM1_CONTROL_REG       [regs INTC_ARM1_CONTROL_REG]
 407
 408
 409     # unlock writing to IOCTRL register
 410     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
 411     # enable address lines A15-A21
 412     mmw $GPIO_IOCTRL_REG 0xf 0x0
 413     # set ARM into supervisor mode (SVC32)
 414     # disable IRQ, FIQ
 415     # Do I need this in JTAG mode?
 416     # it really should be done as 'and ~0x1f | 0xd3 but
 417     # openocd does not support this yet
 418     reg cpsr 0xd3
 419     #   /*
 420     #    * flush v4 I/D caches
 421     #    */
 422     #   mov     r0, #0
 423     #   mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 424     arm mcr 15 0 7 7 0 0x0
 425     #   mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 426     arm mcr 15 0 8 7 0 0x0
 427
 428     #   /*
 429     #    * disable MMU stuff and caches
 430     #    */
 431     #   mrc     p15, 0, r0, c1, c0, 0
 432     arm mrc 15 0 1 0 0
 433     #   bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 434     #   bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 435     #   orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 436     #   orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 437     #   orr     r0, r0, #0x00400000     @ set bit 22 (U)
 438     #   mcr     p15, 0, r0, c1, c0, 0
 439     arm mcr 15 0 1 0 0 0x401002
 440     # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
 441     # APB init
 442     #           // Setting APB Bus Wait states to 1, set post write
 443     #   (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
 444     mww $APB_ACCESS_WS_REG 0x40
 445     # AHB init
 446     #   // enable all 6 masters for ARAM
 447     mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
 448     #   // enable all 6 masters for EBUS
 449     mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
 450
 451     # ARAM init
 452     #   // disable pipeline mode in ARAM
 453     # I don't think this is documented anywhere?
 454     mww $INTC_ARM1_CONTROL_REG 0x1
 455     # configure clocks
 456     setupPLL
 457     # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
 458     setupUART0
 459     # enable cache
 460     # ? (u-boot does nothing here)
 461     # DDR2 memory init
 462     setupDDR2
 463     putsUART0 "C100 initialization complete.\n"
 464     echo "C100 initialization complete."
 465 }
 466
 467 # show current state of watchdog timer
 468 proc showWatchdog {} {
 469     set TIMER_WDT_HIGH_BOUND    [regs TIMER_WDT_HIGH_BOUND]
 470     set TIMER_WDT_CONTROL       [regs TIMER_WDT_CONTROL]
 471     set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
 472
 473     echo [format "TIMER_WDT_HIGH_BOUND    (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
 474     echo [format "TIMER_WDT_CONTROL       (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
 475     echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
 476 }
 477
 478 # converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
 479 # this will trigger watchdog reset
 480 # the sw. reset does not work on C100
 481 # watchdog reset effectively works as hw. reset
 482 proc reboot {} {
 483     set TIMER_WDT_HIGH_BOUND    [regs TIMER_WDT_HIGH_BOUND]
 484     set TIMER_WDT_CONTROL       [regs TIMER_WDT_CONTROL]
 485     set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
 486
 487     # allow the counter to count to high value  before triggering
 488     # this is because register writes are slow over JTAG and
 489     # I don't want to miss the high_bound==curr_count condition
 490     mww $TIMER_WDT_HIGH_BOUND  0xffffff
 491     mww $TIMER_WDT_CURRENT_COUNT 0x0
 492     echo "JTAG speed lowered to 100kHz"
 493     adapter speed 100
 494     mww $TIMER_WDT_CONTROL 0x1
 495     # wait until the reset
 496     echo -n "Waiting for watchdog to trigger..."
 497     #while {[mrw $TIMER_WDT_CONTROL] == 1} {
 498     #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
 499     #    sleep 1
 500     #
 501     #}
 502     while {[c100.cpu curstate] != "running"} { sleep 1}
 503     echo "done."
 504     echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
 505 }