1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ######################################
4 # Target: Atmel AT91SAM9260
5 ######################################
7 source [find target/at91sam9261.cfg]
9 reset_config trst_and_srst
13 adapter srst delay 200
17 $_TARGETNAME configure -event reset-start {
18 # at reset chip runs at 32khz
22 $_TARGETNAME configure -event reset-init {at91sam_init}
25 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
26 set _FLASHNAME $_CHIPNAME.flash
27 flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
29 # Faster memory downloads. This is disabled automatically during
30 # reset init since all reset init sequences are too short for
32 arm7_9 dcc_downloads enable
33 arm7_9 fast_memory_access enable
35 proc at91sam_init { } {
36 mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
37 mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
39 mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
40 sleep 20 ;# wait 20 ms
41 mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
42 sleep 10 ;# wait 10 ms
43 mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
44 sleep 20 ;# wait 20 ms
45 mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
46 sleep 10 ;# wait 10 ms
47 mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
48 sleep 10 ;# wait 10 ms
50 # Now run at anything fast... ie: 10mhz!
51 adapter speed 10000 ;# Increase JTAG Speed to 6 MHz
53 mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
54 mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
55 mww 0xffffec08 0x00160016 ;# SMC_CYCLE0
56 mww 0xffffec0c 0x00161003 ;# SMC_MODE0
58 mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
59 mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
61 mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
63 mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
64 #mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
66 mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
68 mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
70 mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
86 mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
88 mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
90 mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us