1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # -------------------------------------------------------------------------
4 # KaRo TX25 CPU Module on a StarterkitV base board
5 # http://www.karo-electronics.com/tx25.html
6 # -------------------------------------------------------------------------
9 source [find target/imx25.cfg]
11 #-------------------------------------------------------------------------
13 #-------------------------------------------------------------------------
15 nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
18 $_TARGETNAME configure -event gdb-attach { reset init }
19 $_TARGETNAME configure -event reset-init { tx25_init }
24 #-------------------------------------------------------------------------
25 # AIPS setup - Only setup MPROTx registers. The PACR default values are good.
26 # Set all MPROTx to be non-bufferable, trusted for R/W,
27 # not forced to user-mode.
28 #-------------------------------------------------------------------------
30 mww 0x43f00000 0x77777777
31 mww 0x43f00004 0x77777777
32 mww 0x53f00000 0x77777777
33 mww 0x53f00004 0x77777777
37 #-------------------------------------------------------------------------
38 # MAX (Multi-Layer AHB Crossbar Switch) setup
39 # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
40 #-------------------------------------------------------------------------
42 mww 0x43f04000 0x00043210
43 mww 0x43f04100 0x00043210
44 mww 0x43f04200 0x00043210
45 mww 0x43f04300 0x00043210
46 mww 0x43f04400 0x00043210
48 # SGPCR - always park on last master
55 # MGPCR - restore default values
62 # Configure M3IF registers
63 # M3IF Control Register (M3IFCTL) for MX25
64 # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
65 # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
66 # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
67 # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
68 # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
69 # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
70 # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
71 # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
74 mww 0xb8003000 0x00000001
76 #-------------------------------------------------------------------------
78 #-------------------------------------------------------------------------
80 # Set the Clock CTL (HRM p. 355)
81 mww 0x53F80008 0x20034000
83 # Setup Clock Gating CTL 0-2 (HRM p. 357)
84 mww 0x53F8000C 0x1fffffff
85 mww 0x53F80010 0xffffffff
86 mww 0x53F80014 0x000fdfff
88 #-------------------------------------------------------------------------
89 # SDRAM initialization
90 #-------------------------------------------------------------------------
93 mww 0x43FAC454 0x00000800
95 # reset (set up ESDMISC)
96 mww 0xB8001010 0x00000002
98 # Setup for SDRAM Bank 0
99 #-------------------------------------------------------------------------
102 mww 0xB8001004 0x00095728
104 # CTL SMode = Precharge command
105 mww 0xB8001000 0x92116480
106 mww 0x80000400 0x00000000
108 # CTL SMode = Auto Refresh command
109 mww 0xB8001000 0xA2116480
119 # CTL SMode = Load Mode Register command
120 mww 0xB8001000 0xB2116480
124 mww 0xB8001000 0x82116480
126 # Setup for SDRAM Bank 1
127 #-------------------------------------------------------------------------
130 mww 0xB800100C 0x00095728
132 # CTL SMode = Precharge command
133 mww 0xB8001008 0x92116480
134 mww 0x90000400 0x00000000
136 # CTL SMode = Auto Refresh command
137 mww 0xB8001008 0xA2116480
138 mww 0x90000000 0x00000000
139 mww 0x90000000 0x00000000
140 mww 0x90000000 0x00000000
141 mww 0x90000000 0x00000000
142 mww 0x90000000 0x00000000
143 mww 0x90000000 0x00000000
144 mww 0x90000000 0x00000000
145 mww 0x90000000 0x00000000
147 # CTL SMode = Load Mode Register command
148 mww 0xB8001008 0xB2116480
152 mww 0xB8001008 0x82116480
155 #-------------------------------------------------------------------------
157 mww 0x43FAC02C 0x00000015
158 mww 0x53FD0000 0x01000000
159 mww 0x53FD0004 0x00000080