1 # SPDX-License-Identifier: GPL-2.0-or-later
3 #################################################################################################
4 # Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
5 # based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
7 # Generated for In-Circuit i.MX53 SO-Dimm ;#
8 #################################################################################################
10 # The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
11 source [find target/imx53.cfg]
12 # Helper for common memory read/modify/write procedures
13 source [find mem_helper.tcl]
15 echo "i.MX53 SO-Dimm board lodaded."
18 #reset_config srst_only
22 # Slow speed to be sure it will work
24 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
26 $_TARGETNAME configure -event "reset-assert" {
31 $_TARGETNAME configure -event reset-init { sodimm_init }
33 global AIPS1_BASE_ADDR
34 set AIPS1_BASE_ADDR 0x53F00000
35 global AIPS2_BASE_ADDR
36 set AIPS2_BASE_ADDR 0x63F00000
38 proc sodimm_init { } {
43 echo "HW version [format %x [mrw 0x48]]"
48 ; # ARM errata ID #468414
49 set tR [arm mrc 15 0 1 0 1]
50 arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
59 ; #reg cpsr 0x000001D3
67 # L2CC Cache setup/invalidation/disable
69 ; #/* explicitly disable L2 cache */
70 ; #mrc 15, 0, r0, c1, c0, 1
71 set tR [arm mrc 15 0 1 0 1]
73 ; #mcr 15, 0, r0, c1, c0, 1
74 arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
76 ; #/* reconfigure L2 cache aux control reg */
77 ; #mov r0, #0xC0 /* tag RAM */
78 ; #add r0, r0, #0x4 /* data RAM */
79 ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
80 ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
81 ; #orr r0, r0, #(1 << 22) /* disable write allocate */
83 ; #mcr 15, 1, r0, c9, c0, 2
84 arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
88 # AIPS setup - Only setup MPROTx registers.
89 # The PACR default values are good.
91 ; # Set all MPROTx to be non-bufferable, trusted for R/W,
92 ; # not forced to user-mode.
93 global AIPS1_BASE_ADDR
94 global AIPS2_BASE_ADDR
98 mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
99 mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
100 mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
101 mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
106 proc init_clock { } {
107 global AIPS1_BASE_ADDR
108 global AIPS2_BASE_ADDR
109 set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
111 set CLKCTL_CBCDR 0x14
112 set CLKCTL_CBCMR 0x18
113 set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
114 set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
115 set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
116 set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
117 set CLKCTL_CSCMR1 0x1C
118 set CLKCTL_CDHIPR 0x48
119 set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
120 set CLKCTL_CSCDR1 0x24
123 ; # Switch ARM to step clock
124 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
128 setup_pll $PLL1_BASE_ADDR 800
129 setup_pll $PLL3_BASE_ADDR 400
131 ; # Switch peripheral to PLL3
132 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
133 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
134 while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
136 setup_pll $PLL2_BASE_ADDR 400
138 ; # Switch peripheral to PLL2
139 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
141 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
143 ; # change uart clk parent to pll2
144 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
146 ; # make sure change is effective
147 while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
149 setup_pll $PLL3_BASE_ADDR 216
151 setup_pll $PLL4_BASE_ADDR 455
153 ; # Set the platform clock dividers
154 mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
156 mww [expr {$CCM_BASE_ADDR + 0x10}] 0
158 ; # Switch ARM back to PLL 1.
159 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
162 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
164 ; # Restore the default values in the Gate registers
165 mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
166 mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
167 mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
168 mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
169 mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
170 mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
171 mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
172 mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
174 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
176 ; # for cko - for ARM div by 8
177 mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
181 proc setup_pll { PLL_ADDR CLK } {
183 set PLL_DP_CONFIG 0x04
185 set PLL_DP_HFS_OP 0x1C
187 set PLL_DP_HFS_MFD 0x20
189 set PLL_DP_HFS_MFN 0x24
192 set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
193 set DP_MFD [expr {12 - 1}]
195 } elseif {$CLK == 850} {
196 set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
197 set DP_MFD [expr {48 - 1}]
199 } elseif {$CLK == 800} {
200 set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
201 set DP_MFD [expr {3 - 1}]
203 } elseif {$CLK == 700} {
204 set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
205 set DP_MFD [expr {24 - 1}]
207 } elseif {$CLK == 600} {
208 set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
209 set DP_MFD [expr {4 - 1}]
211 } elseif {$CLK == 665} {
212 set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
213 set DP_MFD [expr {96 - 1}]
215 } elseif {$CLK == 532} {
216 set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
217 set DP_MFD [expr {24 - 1}]
219 } elseif {$CLK == 455} {
220 set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
221 set DP_MFD [expr {48 - 1}]
223 } elseif {$CLK == 400} {
224 set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
225 set DP_MFD [expr {3 - 1}]
227 } elseif {$CLK == 216} {
228 set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
229 set DP_MFD [expr {4 - 1}]
232 error "Error (setup_dll): clock not found!"
235 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
236 mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
238 mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
239 mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
241 mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
242 mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
244 mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
245 mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
247 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
248 while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
252 proc CPU_2_BE_32 { L } {
253 return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
257 # Device Configuration Data
260 #*========================================================================================== ======
261 # Initialization script for 32 bit DDR3 (CS0+CS1)
262 #*========================================================================================== ======
263 # Remux D24/D25 to perform Flash-access
264 mww 0x53fa818C 0x00000000 ; #EIM_RW
265 mww 0x53fa8180 0x00000000 ; #EIM_CS0
266 mww 0x53fa8188 0x00000000 ; #EIM_OE
267 mww 0x53fa817C 0x00000000 ; #A16
268 mww 0x53fa8178 0x00000000 ; #A17
269 mww 0x53fa8174 0x00000000 ; #A18
270 mww 0x53fa8170 0x00000000 ; #A19
271 mww 0x53fa816C 0x00000000 ; #A20
272 mww 0x53fa8168 0x00000000 ; #A21
273 mww 0x53fa819C 0x00000000 ; #DA0
274 mww 0x53fa81A0 0x00000000 ; #DA1
275 mww 0x53fa81A4 0x00000000 ; #DA2
276 mww 0x53fa81A8 0x00000000 ; #DA3
277 mww 0x53fa81AC 0x00000000 ; #DA4
278 mww 0x53fa81B0 0x00000000 ; #DA5
279 mww 0x53fa81B4 0x00000000 ; #DA6
280 mww 0x53fa81B8 0x00000000 ; #DA7
281 mww 0x53fa81BC 0x00000000 ; #DA8
282 mww 0x53fa81C0 0x00000000 ; #DA9
283 mww 0x53fa81C4 0x00000000 ; #DA10
284 mww 0x53fa81C8 0x00000000 ; #DA11
285 mww 0x53fa81CC 0x00000000 ; #DA12
286 mww 0x53fa81D0 0x00000000 ; #DA13
287 mww 0x53fa81D4 0x00000000 ; #DA14
288 mww 0x53fa81D8 0x00000000 ; #DA15
289 mww 0x53fa8118 0x00000000 ; #D16
290 mww 0x53fa811C 0x00000000 ; #D17
291 mww 0x53fa8120 0x00000000 ; #D18
292 mww 0x53fa8124 0x00000000 ; #D19
293 mww 0x53fa8128 0x00000000 ; #D20
294 mww 0x53fa812C 0x00000000 ; #D21
295 mww 0x53fa8130 0x00000000 ; #D22
296 mww 0x53fa8134 0x00000000 ; #D23
297 mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
298 mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
299 mww 0x53fa8144 0x00000000 ; #D26
300 mww 0x53fa8148 0x00000000 ; #D27
301 mww 0x53fa814C 0x00000000 ; #D28
302 mww 0x53fa8150 0x00000000 ; #D29
303 mww 0x53fa8154 0x00000000 ; #D30
304 mww 0x53fa8158 0x00000000 ; #D31
306 # DDR3 IOMUX configuration
307 #* Global pad control options */
308 mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
309 mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
310 mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
311 mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
312 mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
313 mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
314 mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
315 mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
316 mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
317 mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
318 mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
319 mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
320 mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
321 mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
322 mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
323 mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
324 mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
325 # mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
326 mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
327 mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
328 mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
329 mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
330 mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
331 mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
332 mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
333 # mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
334 # mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
335 # mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
336 # mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
338 #* Data bus byte lane pad drive strength control options */
339 # mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
340 # mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
341 # mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
342 # mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
343 # mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
344 # mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
345 # mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
346 # mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
347 # mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
348 # mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
349 # mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
350 # mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
352 #* SDCLK pad drive strength control options */
353 # mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
354 # mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
356 #* Control and addr bus pad drive strength control options */
357 # mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
358 # mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
359 # mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
360 # mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
362 # mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
363 # mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
365 # Initialize DDR3 memory - Micron MT41J128M16-187Er
366 #** Keep for now, same setting as CPU3 board **#
367 mww 0x63fd901c 0x00008000
368 # mww 0x63fd904c 0x01680172 ; #write leveling reg 0
369 # mww 0x63fd9050 0x0021017f ; #write leveling reg 1
370 mww 0x63fd9088 0x32383535 ; #read delay lines
371 mww 0x63fd9090 0x40383538 ; #write delay lines
372 # mww 0x63fd90F8 0x00000800 ; #Measure unit
373 mww 0x63fd907c 0x0136014d ; #DQS gating 0
374 mww 0x63fd9080 0x01510141 ; #DQS gating 1
375 #* CPU3 Board settingr
376 # Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
377 # mww 0x63fd9018 0x00091740 ; #Misc register:
378 #* Quick Silver board setting
379 # Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
380 mww 0x63fd9018 0x00011740 ; #Misc register
382 # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
383 # mww 0x63fd9000 0xc3190000 ; #Main control register
384 # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
385 mww 0x63fd9000 0x83190000 ; #Main control register
386 # tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
387 mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
388 # tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
389 mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
390 # tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
391 mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
392 mww 0x63fd902c 0x000026d2 ; #command delay (default)
393 mww 0x63fd9030 0x009f0e21 ; #out of reset delays
394 # Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
395 mww 0x63fd9008 0x12273030 ; #ODT timings
396 # tCKE=3; tCKSRX=5; tCKSRE=5
397 mww 0x63fd9004 0x0002002d
399 #**********************************
400 #DDR device configuration:
401 #**********************************
402 #**********************************
404 #**********************************
405 mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
406 # Full array self refresh
407 # Rtt_WR disabled (no ODT at IO CMOS operation)
408 # Manual self refresh
410 mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
411 mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
412 # out impedance = RZQ/7
413 # Rtt_nom disabled (no ODT at IO CMOS operation)
414 # Aditive latency off
415 # write leveling disabled
416 # tdqs (differential?) disabled
418 mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
419 mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
420 #**********************************
422 #**********************************
423 # mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
424 # mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
425 # mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
426 # mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
427 # mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
428 #**********************************
431 mww 0x63fd9020 0x00001800 ; # Refresh control register
432 mww 0x63fd9040 0x04b80003 ; # ZQ HW control
433 mww 0x63fd9058 0x00022227 ; # ODT control register
435 mww 0x63fd901c 0x00000000
437 # CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
440 # mww 0x53FD4060 0x01e900f0
446 $_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
448 flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME