1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # CALAO Systems USB-A9G20-C01
4 # Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang
7 ftdi device_desc "USB-A9G20"
8 ftdi vid_pid 0x0403 0x6010
9 ftdi layout_init 0x0c08 0x0f1b
10 ftdi layout_signal nTRST -data 0x0100 -noe 0x0400
11 ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
15 source [find target/at91sam9g20.cfg]
16 source [find mem_helper.tcl]
18 proc at91sam9g20_reset_start { } {
20 # Make sure that the jtag is running slow, since there are a number of different ways the board
21 # can be configured coming into this state that can cause communication problems with the jtag
22 # adapter. Also since this call can be made following a "reset init" where fast memory accesses
23 # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower
24 # jtag speed without causing GDB keep alive problem.
26 arm7_9 fast_memory_access disable
27 adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
28 halt 0 ;# Make sure processor is halted, or error will result in following steps.
30 # RSTC_MR : enable user reset, MMU may be enabled... use physical address
31 mww phys 0xfffffd08 0xa5000501
34 proc at91sam9g20_reset_init { } {
36 # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
37 # a number of steps that must be carefully performed. The process outline below follows the
38 # recommended procedure outlined in the AT91SAM9G20 technical manual.
40 # Several key and very important things to keep in mind:
41 # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
42 # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
43 # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
45 mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
47 # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register.
49 mww 0xfffffc20 0x00000002
51 # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).
52 # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
54 mww 0xfffffc28 0x20843F02
55 while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }
57 # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
58 # Wait for MCKRDY signal from PMC_SR to assert.
60 mww 0xfffffc30 0x00001300
61 while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
63 # Now change PMC_MCKR register to select PLLA.
64 # Wait for MCKRDY signal from PMC_SR to assert.
66 mww 0xfffffc30 0x00001302
67 while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
69 # Processor and master clocks are now operating and stable at maximum frequency possible:
70 # -> MCLK = 133.000 MHz
71 # -> PCLK = 400.000 MHz
73 # Switch to fast JTAG speed
77 # Enable faster DCC downloads.
79 arm7_9 dcc_downloads enable
80 arm7_9 fast_memory_access enable
82 # To be able to use external SDRAM, several peripheral configuration registers must
83 # be modified. The first change is made to PIO_ASR to select peripheral functions
84 # for D15 through D31. The second change is made to the PIO_PDR register to disable
85 # this for D15 through D31.
87 mww 0xfffff870 0xffff0000
88 mww 0xfffff804 0xffff0000
90 # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
91 # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
92 # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller.
94 mww 0xffffef1c 0x000000a
96 # The USB-A9G20 Embedded computer has built-in NandFlash. The exact physical timing characteristics
97 # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
98 # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
100 mww 0xffffec30 0x00020002
101 mww 0xffffec34 0x04040404
102 mww 0xffffec38 0x00070007
103 mww 0xffffec3c 0x00030003
105 # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
106 # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
107 # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
108 # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
109 # of 133.000 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
111 # CAS latency = 3 cycles
118 # 9 column, 13 row, 4 banks
119 # refresh equal to or less then 7.8 us for commercial/industrial rated devices
121 # Thus SDRAM_CR = 0xa6339279
123 mww 0xffffea08 0xa6339279
125 # Memory Device Type: SDRAM (low-power would be 0x1)
126 mww 0xffffea24 0x00000000
128 # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
129 # the starting memory location for the SDRAM.
131 mww 0xffffea00 0x00000001
134 # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
135 # value into the starting memory location for the SDRAM.
137 mww 0xffffea00 0x00000002
140 # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
141 # zero values eight times into the starting memory location for the SDRAM.
153 # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
154 # the starting memory location for the SDRAM.
159 # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
160 # memory location for the SDRAM.
165 # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
167 mww 0xffffea04 0x0000039c
170 $_TARGETNAME configure -event gdb-attach { reset init }
171 $_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
172 $_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}