1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
4 # Ampere Altra Max ("Mystique") processors
6 # Copyright (c) 2019-2021, Ampere Computing LLC
11 # Set the JTAG clock frequency
12 # Syntax: -c "set JTAGFREQ {freq_in_khz}"
16 # If not specified, defaults to "qs"
17 # Syntax: -c "set SYSNAME {qs}"
19 # Life-Cycle State (LCS)
20 # If not specified, defaults to "Secure LCS"
22 # LCS=1, "Chip Manufacturing LCS"
23 # Syntax: -c "set LCS {0}"
24 # Syntax: -c "set LCS {1}"
26 # CORELIST_S0, CORELIST_S1
27 # Specify available physical cores by number
28 # Example syntax to connect to physical cores 16 and 17 for S0 and S1
29 # Syntax: -c "set CORELIST_S0 {16 17}"
30 # Syntax: -c "set CORELIST_S1 {16 17}"
32 # COREMASK_S0_LO, COREMASK_S1_LO
33 # Specify available physical cores 0-63 by mask
34 # Example syntax to connect to physical cores 16 and 17 for S0 and S1
35 # Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
36 # Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}"
38 # COREMASK_S0_HI, COREMASK_S1_HI
39 # Specify available physical cores 64 and above by mask
40 # Example syntax to connect to physical cores 94 and 95 for S0 and S1
41 # Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
42 # Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}"
45 # Group all ARMv8 cores per socket into individual SMP sessions
46 # If not specified, group ARMv8 cores from both sockets into one SMP session
47 # Syntax: -c "set SPLITSMP {}"
50 # Enable OpenOCD ARMv8 core target physical indexing
51 # If not specified, defaults to OpenOCD ARMv8 core target logical indexing
52 # Syntax: -c "set PHYS_IDX {}"
55 # Configure JTAG speed
58 if { [info exists JTAGFREQ] } {
59 adapter speed $JTAGFREQ
68 if { [info exists SYSNAME] } {
75 # Configure Board level SMP configuration if necessary
78 if { ![info exists SPLITSMP] } {
79 # Group dual chip into a single SMP configuration
80 set SMP_STR "target smp"
81 set CORE_INDEX_OFFSET 0
82 set DUAL_SOCKET_SMP_ENABLED ""
90 reset_config trst_only
96 if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \
97 [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {
98 set CHIPNAME ${_SYSNAME}1
99 if { [info exists CORELIST_S1] } {
100 set CORELIST $CORELIST_S1
102 if { [info exists COREMASK_S1_LO] } {
103 set COREMASK_LO $COREMASK_S1_LO
108 if { [info exists COREMASK_S1_HI] } {
109 set COREMASK_HI $COREMASK_S1_HI
114 source [find target/ampere_qs_mq.cfg]
116 if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
117 if { [info exists MQ_ENABLE] } {
118 set CORE_INDEX_OFFSET 128
120 set CORE_INDEX_OFFSET 80
124 set CHIPNAME ${_SYSNAME}0
125 if { [info exists CORELIST_S0] } {
126 set CORELIST $CORELIST_S0
128 if { [info exists COREMASK_S0_LO] } {
129 set COREMASK_LO $COREMASK_S0_LO
134 if { [info exists COREMASK_S0_HI] } {
135 set COREMASK_HI $COREMASK_S0_HI
140 source [find target/ampere_qs_mq.cfg]
142 set CHIPNAME ${_SYSNAME}1
145 source [find target/ampere_qs_mq.cfg]
147 if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {
148 if { [info exists MQ_ENABLE] } {
149 set CORE_INDEX_OFFSET 128
151 set CORE_INDEX_OFFSET 80
155 set CHIPNAME ${_SYSNAME}0
158 source [find target/ampere_qs_mq.cfg]
161 if { [info exists DUAL_SOCKET_SMP_ENABLED] } {
162 # For dual socket SMP configuration, evaluate the string