1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Copyright (C) 2010-2011 by Karl Kurbjun
5 # Copyright (C) 2009-2011 by Øyvind Harboe
6 # Copyright (C) 2009 by David Brownell
7 # Copyright (C) 2009 by Magnus Lundin
9 # TI AM/DM37x Technical Reference Manual (Version R)
10 # http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf
12 # This script is based on the AM3517 initialization. It should be considered
13 # preliminary since it needs more complete testing and only the basic
17 ###############################################################################
18 # User modifiable parameters
19 ###############################################################################
21 # This script uses the variable CHIPTYPE to determine whether this is an AM35x
22 # or DM37x target. If CHIPTYPE is not set it will error out.
23 if { [info exists CHIPTYPE] } {
25 if { [info exists CHIPNAME] } {
26 set _CHIPNAME $CHIPNAME
28 set _CHIPNAME $CHIPTYPE
33 # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
34 set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
37 # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
38 set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f"
41 error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
45 error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
48 # Run the adapter at the fastest acceptable speed with the slowest possible
52 ###############################################################################
54 # The OpenOCD commands are described in the TAP Declaration section
55 # http://openocd.org/doc/html/TAP-Declaration.html
56 ###############################################################################
58 # The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
59 # can be read about this module in sprugn4r in chapter 27: "Debug and
60 # Emulation". The module is used to route the JTAG chain to the various
61 # subsystems in the chip.
62 source [find target/icepick.cfg]
64 # The TAP order should be described from the TDO connection in OpenOCD to the
65 # TDI pin. The OpenOCD FAQ describes this in more detail:
66 # http://openocd.org/doc/html/FAQ.html
68 # From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
71 # ---------|------------
73 # Sequencer| 2 Note: The sequencer is an ARM968
77 # Right now the only secondary tap enabled is the DAP so the rest are left
81 # Start of Chain Description
82 # The Secondary TAPs all have enable functions defined for use with the ICEPick
83 # Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
84 # the TAP numbers for ICEPick do not change.
86 # TODO: A disable function should also be added.
89 # Secondary TAP: DAP is closest to the TDO output
90 # The TAP enable event also needs to be described
91 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
92 jtag configure $_CHIPNAME.cpu -event tap-enable \
93 "icepick_c_tapenable $_CHIPNAME.jrc 3"
95 # These taps are only present in the DM37x series.
96 if { $CHIPTYPE == "dm37x" } {
97 # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
98 # The ICEPick can be used to enable it in the chain.
99 jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
100 jtag configure $_CHIPNAME.arm2 -event tap-enable \
101 "icepick_c_tapenable $_CHIPNAME.jrc 2"
103 # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
104 # The ICEPick can be used to enable it in the chain.
105 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
106 jtag configure $_CHIPNAME.dsp -event tap-enable \
107 "icepick_c_tapenable $_CHIPNAME.jrc 1"
110 # Secondary TAP: D2D it is not in the chain by default (-disable)
111 # The ICEPick can be used to enable it in the chain.
112 # This IRLEN is probably incorrect - not sure where the documentation is.
113 jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
114 jtag configure $_CHIPNAME.d2d -event tap-enable \
115 "icepick_c_tapenable $_CHIPNAME.jrc 0"
117 # Primary TAP: ICEPick - it is closest to TDI so last in the chain
118 eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
121 # End of Chain Description
125 # Start JTAG TAP events
128 # some TCK tycles are required to activate the DEBUG power domain
129 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
132 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
135 # End JTAG TAP events
138 ###############################################################################
140 # This section is described in the OpenOCD documentation under CPU Configuration
141 # http://openocd.org/doc/html/CPU-Configuration.html
142 ###############################################################################
144 # Create the CPU target to be used with GDB: Cortex-A8, using DAP
145 set _TARGETNAME $_CHIPNAME.cpu
146 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
147 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
149 # The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
150 # 16K to be used as a scratchpad for OpenOCD.
152 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
155 # Start Target Reset Event Setup:
158 # Set the JTAG clock down to 10 kHz to be sure that it will work with the
159 # slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
160 # *after* PLL and clock tree setup.
162 $_TARGETNAME configure -event "reset-start" { adapter speed 10 }
164 # Describe the reset assert process for openocd - this is asserted with the
166 $_TARGETNAME configure -event "reset-assert" {
170 # assert warm system reset through ICEPick
171 icepick_c_wreset $_CHIPNAME.jrc
174 # After the reset is asserted we need to re-initialize debugging and speed up
177 $_TARGETNAME configure -event reset-assert-post {
180 amdm37x_dbginit $_TARGETNAME
184 $_TARGETNAME configure -event gdb-attach {
187 amdm37x_dbginit $_TARGETNAME
189 echo "Halting target"
194 # End Target Reset Event Setup:
197 ###############################################################################
199 # Add any functions needed for the target here
200 ###############################################################################
202 # Run this to enable invasive debugging. This is run automatically in the
204 proc amdm37x_dbginit {target} {
205 # General Cortex-A8 debug initialisation
208 # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
209 # access to the signal appears to be implementation specific. TI does not
210 # describe this register much except a quick line that states DBGEM (sic) is
211 # at this address and this bit.
212 $target mww phys 0x5401d030 0x00002000