1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
4 # Ampere Altra Max ("Mystique") processors
6 # Copyright (c) 2019-2021, Ampere Computing LLC
11 # Set the JTAG clock frequency
12 # Syntax: -c "set JTAGFREQ {freq_in_khz}"
16 # If not specified, defaults to "qs"
17 # Syntax: -c "set SYSNAME {qs}"
19 # Life-Cycle State (LCS)
20 # If not specified, defaults to "Secure LCS"
22 # LCS=1, "Chip Manufacturing LCS"
23 # Syntax: -c "set LCS {0}"
24 # Syntax: -c "set LCS {1}"
27 # Specify available physical cores by number
28 # Example syntax to connect to physical cores 16 and 17 for S0
29 # Syntax: -c "set CORELIST_S0 {16 17}"
32 # Specify available physical cores 0-63 by mask
33 # Example syntax to connect to physical cores 16 and 17 for S0
34 # Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
37 # Specify available physical cores 64 and above by mask
38 # Example syntax to connect to physical cores 94 and 95 for S0
39 # Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
42 # Enable OpenOCD ARMv8 core target physical indexing
43 # If not specified, defaults to OpenOCD ARMv8 core target logical indexing
44 # Syntax: -c "set PHYS_IDX {}"
47 # Configure JTAG speed
50 if { [info exists JTAGFREQ] } {
51 adapter speed $JTAGFREQ
60 if { [info exists SYSNAME] } {
71 reset_config trst_only
77 if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
78 set CHIPNAME ${_SYSNAME}0
79 if { [info exists CORELIST_S0] } {
80 set CORELIST $CORELIST_S0
82 if { [info exists COREMASK_S0_LO] } {
83 set COREMASK_LO $COREMASK_S0_LO
88 if { [info exists COREMASK_S0_HI] } {
89 set COREMASK_HI $COREMASK_S0_HI
95 set CHIPNAME ${_SYSNAME}0
100 source [find target/ampere_qs_mq.cfg]