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ipdbg: fix double free of virtual-ir data
[openocd.git] / src / target / riscv / riscv.c
blob9cd4922d20d7f0974d1d72410f7bfb663111eb70
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include <assert.h>
4 #include <stdlib.h>
5 #include <time.h>
6
7 #ifdef HAVE_CONFIG_H
8 #include "config.h"
9 #endif
10
11 #include <helper/log.h>
12 #include <helper/time_support.h>
13 #include "target/target.h"
14 #include "target/algorithm.h"
15 #include "target/target_type.h"
16 #include <target/smp.h>
17 #include "jtag/jtag.h"
18 #include "target/register.h"
19 #include "target/breakpoints.h"
20 #include "riscv.h"
21 #include "gdb_regs.h"
22 #include "rtos/rtos.h"
23 #include "debug_defines.h"
24 #include <helper/bits.h>
25
26 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
27 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
28
29 /* Constants for legacy SiFive hardware breakpoints. */
30 #define CSR_BPCONTROL_X (1<<0)
31 #define CSR_BPCONTROL_W (1<<1)
32 #define CSR_BPCONTROL_R (1<<2)
33 #define CSR_BPCONTROL_U (1<<3)
34 #define CSR_BPCONTROL_S (1<<4)
35 #define CSR_BPCONTROL_H (1<<5)
36 #define CSR_BPCONTROL_M (1<<6)
37 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
38 #define CSR_BPCONTROL_BPACTION (0xff<<11)
39
40 #define DEBUG_ROM_START 0x800
41 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
42 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
43 #define DEBUG_RAM_START 0x400
44
45 #define SETHALTNOT 0x10c
46
47 /*** JTAG registers. ***/
48
49 #define DTMCONTROL 0x10
50 #define DTMCONTROL_DBUS_RESET (1<<16)
51 #define DTMCONTROL_IDLE (7<<10)
52 #define DTMCONTROL_ADDRBITS (0xf<<4)
53 #define DTMCONTROL_VERSION (0xf)
54
55 #define DBUS 0x11
56 #define DBUS_OP_START 0
57 #define DBUS_OP_SIZE 2
58 typedef enum {
59 DBUS_OP_NOP = 0,
60 DBUS_OP_READ = 1,
61 DBUS_OP_WRITE = 2
62 } dbus_op_t;
63 typedef enum {
64 DBUS_STATUS_SUCCESS = 0,
65 DBUS_STATUS_FAILED = 2,
66 DBUS_STATUS_BUSY = 3
67 } dbus_status_t;
68 #define DBUS_DATA_START 2
69 #define DBUS_DATA_SIZE 34
70 #define DBUS_ADDRESS_START 36
71
72 typedef enum slot {
73 SLOT0,
74 SLOT1,
75 SLOT_LAST,
76 } slot_t;
77
78 /*** Debug Bus registers. ***/
79
80 #define DMCONTROL 0x10
81 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
82 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
83 #define DMCONTROL_BUSERROR (7<<19)
84 #define DMCONTROL_SERIAL (3<<16)
85 #define DMCONTROL_AUTOINCREMENT (1<<15)
86 #define DMCONTROL_ACCESS (7<<12)
87 #define DMCONTROL_HARTID (0x3ff<<2)
88 #define DMCONTROL_NDRESET (1<<1)
89 #define DMCONTROL_FULLRESET 1
90
91 #define DMINFO 0x11
92 #define DMINFO_ABUSSIZE (0x7fU<<25)
93 #define DMINFO_SERIALCOUNT (0xf<<21)
94 #define DMINFO_ACCESS128 (1<<20)
95 #define DMINFO_ACCESS64 (1<<19)
96 #define DMINFO_ACCESS32 (1<<18)
97 #define DMINFO_ACCESS16 (1<<17)
98 #define DMINFO_ACCESS8 (1<<16)
99 #define DMINFO_DRAMSIZE (0x3f<<10)
100 #define DMINFO_AUTHENTICATED (1<<5)
101 #define DMINFO_AUTHBUSY (1<<4)
102 #define DMINFO_AUTHTYPE (3<<2)
103 #define DMINFO_VERSION 3
104
105 /*** Info about the core being debugged. ***/
106
107 #define DBUS_ADDRESS_UNKNOWN 0xffff
108
109 #define MAX_HWBPS 16
110 #define DRAM_CACHE_SIZE 16
111
112 static uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
113 struct scan_field select_dtmcontrol = {
114 .in_value = NULL,
115 .out_value = ir_dtmcontrol
116 };
117 static uint8_t ir_dbus[4] = {DBUS};
118 struct scan_field select_dbus = {
119 .in_value = NULL,
120 .out_value = ir_dbus
121 };
122 static uint8_t ir_idcode[4] = {0x1};
123 struct scan_field select_idcode = {
124 .in_value = NULL,
125 .out_value = ir_idcode
126 };
127
128 static bscan_tunnel_type_t bscan_tunnel_type;
129 int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
130
131 static const uint8_t bscan_zero[4] = {0};
132 static const uint8_t bscan_one[4] = {1};
133
134 static uint8_t ir_user4[4];
135 static struct scan_field select_user4 = {
136 .in_value = NULL,
137 .out_value = ir_user4
138 };
139
140
141 static uint8_t bscan_tunneled_ir_width[4] = {5}; /* overridden by assignment in riscv_init_target */
142 static struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
143 {
144 .num_bits = 3,
145 .out_value = bscan_zero,
146 .in_value = NULL,
147 },
148 {
149 .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
150 .out_value = ir_dbus,
151 .in_value = NULL,
152 },
153 {
154 .num_bits = 7,
155 .out_value = bscan_tunneled_ir_width,
156 .in_value = NULL,
157 },
158 {
159 .num_bits = 1,
160 .out_value = bscan_zero,
161 .in_value = NULL,
162 }
163 };
164
165 static struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
166 {
167 .num_bits = 1,
168 .out_value = bscan_zero,
169 .in_value = NULL,
170 },
171 {
172 .num_bits = 7,
173 .out_value = bscan_tunneled_ir_width,
174 .in_value = NULL,
175 },
176 {
177 .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
178 .out_value = ir_dbus,
179 .in_value = NULL,
180 },
181 {
182 .num_bits = 3,
183 .out_value = bscan_zero,
184 .in_value = NULL,
185 }
186 };
187 static struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
188 static uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
189
190 static struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
191 static uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
192
193 struct trigger {
194 uint64_t address;
195 uint32_t length;
196 uint64_t mask;
197 uint64_t value;
198 bool read, write, execute;
199 int unique_id;
200 };
201
202 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
203 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
204
205 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
206 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
207
208 static bool riscv_enable_virt2phys = true;
209 bool riscv_ebreakm = true;
210 bool riscv_ebreaks = true;
211 bool riscv_ebreaku = true;
212
213 bool riscv_enable_virtual;
214
215 static enum {
216 RO_NORMAL,
217 RO_REVERSED
218 } resume_order;
219
220 static const virt2phys_info_t sv32 = {
221 .name = "Sv32",
222 .va_bits = 32,
223 .level = 2,
224 .pte_shift = 2,
225 .vpn_shift = {12, 22},
226 .vpn_mask = {0x3ff, 0x3ff},
227 .pte_ppn_shift = {10, 20},
228 .pte_ppn_mask = {0x3ff, 0xfff},
229 .pa_ppn_shift = {12, 22},
230 .pa_ppn_mask = {0x3ff, 0xfff},
231 };
232
233 static const virt2phys_info_t sv39 = {
234 .name = "Sv39",
235 .va_bits = 39,
236 .level = 3,
237 .pte_shift = 3,
238 .vpn_shift = {12, 21, 30},
239 .vpn_mask = {0x1ff, 0x1ff, 0x1ff},
240 .pte_ppn_shift = {10, 19, 28},
241 .pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
242 .pa_ppn_shift = {12, 21, 30},
243 .pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
244 };
245
246 static const virt2phys_info_t sv48 = {
247 .name = "Sv48",
248 .va_bits = 48,
249 .level = 4,
250 .pte_shift = 3,
251 .vpn_shift = {12, 21, 30, 39},
252 .vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
253 .pte_ppn_shift = {10, 19, 28, 37},
254 .pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
255 .pa_ppn_shift = {12, 21, 30, 39},
256 .pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
257 };
258
259 static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
260 static void riscv_info_init(struct target *target, struct riscv_info *r);
261 static void riscv_invalidate_register_cache(struct target *target);
262 static int riscv_step_rtos_hart(struct target *target);
263
264 static void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before)
265 {
266 RISCV_INFO(r);
267 uint32_t now = timeval_ms() & 0xffffffff;
268 if (r->sample_buf.used + 5 < r->sample_buf.size) {
269 if (before)
270 r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE;
271 else
272 r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER;
273 r->sample_buf.buf[r->sample_buf.used++] = now & 0xff;
274 r->sample_buf.buf[r->sample_buf.used++] = (now >> 8) & 0xff;
275 r->sample_buf.buf[r->sample_buf.used++] = (now >> 16) & 0xff;
276 r->sample_buf.buf[r->sample_buf.used++] = (now >> 24) & 0xff;
277 }
278 }
279
280 static int riscv_resume_go_all_harts(struct target *target);
281
282 void select_dmi_via_bscan(struct target *target)
283 {
284 jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
285 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
286 jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
287 bscan_tunnel_data_register_select_dmi, TAP_IDLE);
288 else /* BSCAN_TUNNEL_NESTED_TAP */
289 jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
290 bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
291 }
292
293 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
294 {
295 /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
296 uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
297 uint8_t tunneled_dr_width[4] = {32};
298 uint8_t out_value[5] = {0};
299 uint8_t in_value[5] = {0};
300
301 buf_set_u32(out_value, 0, 32, out);
302 struct scan_field tunneled_ir[4] = {};
303 struct scan_field tunneled_dr[4] = {};
304
305 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
306 tunneled_ir[0].num_bits = 3;
307 tunneled_ir[0].out_value = bscan_zero;
308 tunneled_ir[0].in_value = NULL;
309 tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
310 tunneled_ir[1].out_value = ir_dtmcontrol;
311 tunneled_ir[1].in_value = NULL;
312 tunneled_ir[2].num_bits = 7;
313 tunneled_ir[2].out_value = tunneled_ir_width;
314 tunneled_ir[2].in_value = NULL;
315 tunneled_ir[3].num_bits = 1;
316 tunneled_ir[3].out_value = bscan_zero;
317 tunneled_ir[3].in_value = NULL;
318
319 tunneled_dr[0].num_bits = 3;
320 tunneled_dr[0].out_value = bscan_zero;
321 tunneled_dr[0].in_value = NULL;
322 tunneled_dr[1].num_bits = 32 + 1;
323 tunneled_dr[1].out_value = out_value;
324 tunneled_dr[1].in_value = in_value;
325 tunneled_dr[2].num_bits = 7;
326 tunneled_dr[2].out_value = tunneled_dr_width;
327 tunneled_dr[2].in_value = NULL;
328 tunneled_dr[3].num_bits = 1;
329 tunneled_dr[3].out_value = bscan_one;
330 tunneled_dr[3].in_value = NULL;
331 } else {
332 /* BSCAN_TUNNEL_NESTED_TAP */
333 tunneled_ir[3].num_bits = 3;
334 tunneled_ir[3].out_value = bscan_zero;
335 tunneled_ir[3].in_value = NULL;
336 tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
337 tunneled_ir[2].out_value = ir_dtmcontrol;
338 tunneled_ir[1].in_value = NULL;
339 tunneled_ir[1].num_bits = 7;
340 tunneled_ir[1].out_value = tunneled_ir_width;
341 tunneled_ir[2].in_value = NULL;
342 tunneled_ir[0].num_bits = 1;
343 tunneled_ir[0].out_value = bscan_zero;
344 tunneled_ir[0].in_value = NULL;
345
346 tunneled_dr[3].num_bits = 3;
347 tunneled_dr[3].out_value = bscan_zero;
348 tunneled_dr[3].in_value = NULL;
349 tunneled_dr[2].num_bits = 32 + 1;
350 tunneled_dr[2].out_value = out_value;
351 tunneled_dr[2].in_value = in_value;
352 tunneled_dr[1].num_bits = 7;
353 tunneled_dr[1].out_value = tunneled_dr_width;
354 tunneled_dr[1].in_value = NULL;
355 tunneled_dr[0].num_bits = 1;
356 tunneled_dr[0].out_value = bscan_one;
357 tunneled_dr[0].in_value = NULL;
358 }
359 jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
360 jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE);
361 jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE);
362 select_dmi_via_bscan(target);
363
364 int retval = jtag_execute_queue();
365 if (retval != ERROR_OK) {
366 LOG_ERROR("failed jtag scan: %d", retval);
367 return retval;
368 }
369 /* Note the starting offset is bit 1, not bit 0. In BSCAN tunnel, there is a one-bit TCK skew between
370 output and input */
371 uint32_t in = buf_get_u32(in_value, 1, 32);
372 LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
373
374 return in;
375 }
376
377 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
378 {
379 struct scan_field field;
380 uint8_t in_value[4];
381 uint8_t out_value[4] = { 0 };
382
383 if (bscan_tunnel_ir_width != 0)
384 return dtmcontrol_scan_via_bscan(target, out);
385
386
387 buf_set_u32(out_value, 0, 32, out);
388
389 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
390
391 field.num_bits = 32;
392 field.out_value = out_value;
393 field.in_value = in_value;
394 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
395
396 /* Always return to dbus. */
397 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
398
399 int retval = jtag_execute_queue();
400 if (retval != ERROR_OK) {
401 LOG_ERROR("failed jtag scan: %d", retval);
402 return retval;
403 }
404
405 uint32_t in = buf_get_u32(field.in_value, 0, 32);
406 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
407
408 return in;
409 }
410
411 static struct target_type *get_target_type(struct target *target)
412 {
413 if (!target->arch_info) {
414 LOG_ERROR("Target has not been initialized");
415 return NULL;
416 }
417
418 RISCV_INFO(info);
419 switch (info->dtm_version) {
420 case 0:
421 return &riscv011_target;
422 case 1:
423 return &riscv013_target;
424 default:
425 LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
426 return NULL;
427 }
428 }
429
430 static int riscv_create_target(struct target *target, Jim_Interp *interp)
431 {
432 LOG_DEBUG("riscv_create_target()");
433 target->arch_info = calloc(1, sizeof(struct riscv_info));
434 if (!target->arch_info) {
435 LOG_ERROR("Failed to allocate RISC-V target structure.");
436 return ERROR_FAIL;
437 }
438 riscv_info_init(target, target->arch_info);
439 return ERROR_OK;
440 }
441
442 static int riscv_init_target(struct command_context *cmd_ctx,
443 struct target *target)
444 {
445 LOG_DEBUG("riscv_init_target()");
446 RISCV_INFO(info);
447 info->cmd_ctx = cmd_ctx;
448
449 select_dtmcontrol.num_bits = target->tap->ir_length;
450 select_dbus.num_bits = target->tap->ir_length;
451 select_idcode.num_bits = target->tap->ir_length;
452
453 if (bscan_tunnel_ir_width != 0) {
454 assert(target->tap->ir_length >= 6);
455 uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
456 h_u32_to_le(ir_user4, ir_user4_raw);
457 select_user4.num_bits = target->tap->ir_length;
458 bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
459 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
460 bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
461 else /* BSCAN_TUNNEL_NESTED_TAP */
462 bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
463 }
464
465 riscv_semihosting_init(target);
466
467 target->debug_reason = DBG_REASON_DBGRQ;
468
469 return ERROR_OK;
470 }
471
472 static void riscv_free_registers(struct target *target)
473 {
474 /* Free the shared structure use for most registers. */
475 if (target->reg_cache) {
476 if (target->reg_cache->reg_list) {
477 free(target->reg_cache->reg_list[0].arch_info);
478 /* Free the ones we allocated separately. */
479 for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
480 free(target->reg_cache->reg_list[i].arch_info);
481 for (unsigned int i = 0; i < target->reg_cache->num_regs; i++)
482 free(target->reg_cache->reg_list[i].value);
483 free(target->reg_cache->reg_list);
484 }
485 free(target->reg_cache);
486 }
487 }
488
489 static void riscv_deinit_target(struct target *target)
490 {
491 LOG_DEBUG("riscv_deinit_target()");
492
493 struct riscv_info *info = target->arch_info;
494 struct target_type *tt = get_target_type(target);
495
496 if (tt && info && info->version_specific)
497 tt->deinit_target(target);
498
499 riscv_free_registers(target);
500
501 if (!info)
502 return;
503
504 range_list_t *entry, *tmp;
505 list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
506 free(entry->name);
507 free(entry);
508 }
509
510 list_for_each_entry_safe(entry, tmp, &info->expose_custom, list) {
511 free(entry->name);
512 free(entry);
513 }
514
515 free(info->reg_names);
516 free(target->arch_info);
517
518 target->arch_info = NULL;
519 }
520
521 static void trigger_from_breakpoint(struct trigger *trigger,
522 const struct breakpoint *breakpoint)
523 {
524 trigger->address = breakpoint->address;
525 trigger->length = breakpoint->length;
526 trigger->mask = ~0LL;
527 trigger->read = false;
528 trigger->write = false;
529 trigger->execute = true;
530 /* unique_id is unique across both breakpoints and watchpoints. */
531 trigger->unique_id = breakpoint->unique_id;
532 }
533
534 static int maybe_add_trigger_t1(struct target *target,
535 struct trigger *trigger, uint64_t tdata1)
536 {
537 RISCV_INFO(r);
538
539 const uint32_t bpcontrol_x = 1<<0;
540 const uint32_t bpcontrol_w = 1<<1;
541 const uint32_t bpcontrol_r = 1<<2;
542 const uint32_t bpcontrol_u = 1<<3;
543 const uint32_t bpcontrol_s = 1<<4;
544 const uint32_t bpcontrol_h = 1<<5;
545 const uint32_t bpcontrol_m = 1<<6;
546 const uint32_t bpcontrol_bpmatch = 0xf << 7;
547 const uint32_t bpcontrol_bpaction = 0xff << 11;
548
549 if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
550 /* Trigger is already in use, presumably by user code. */
551 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
552 }
553
554 tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
555 tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
556 tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
557 tdata1 = set_field(tdata1, bpcontrol_u,
558 !!(r->misa & BIT('U' - 'A')));
559 tdata1 = set_field(tdata1, bpcontrol_s,
560 !!(r->misa & BIT('S' - 'A')));
561 tdata1 = set_field(tdata1, bpcontrol_h,
562 !!(r->misa & BIT('H' - 'A')));
563 tdata1 |= bpcontrol_m;
564 tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
565 tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
566
567 riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
568
569 riscv_reg_t tdata1_rb;
570 if (riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1) != ERROR_OK)
571 return ERROR_FAIL;
572 LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
573
574 if (tdata1 != tdata1_rb) {
575 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
576 PRIx64 " to tdata1 it contains 0x%" PRIx64,
577 tdata1, tdata1_rb);
578 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
579 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
580 }
581
582 riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
583
584 return ERROR_OK;
585 }
586
587 static int maybe_add_trigger_t2(struct target *target,
588 struct trigger *trigger, uint64_t tdata1)
589 {
590 RISCV_INFO(r);
591
592 /* tselect is already set */
593 if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
594 /* Trigger is already in use, presumably by user code. */
595 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
596 }
597
598 /* address/data match trigger */
599 tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
600 tdata1 = set_field(tdata1, MCONTROL_ACTION,
601 MCONTROL_ACTION_DEBUG_MODE);
602 tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
603 tdata1 |= MCONTROL_M;
604 if (r->misa & (1 << ('S' - 'A')))
605 tdata1 |= MCONTROL_S;
606 if (r->misa & (1 << ('U' - 'A')))
607 tdata1 |= MCONTROL_U;
608
609 if (trigger->execute)
610 tdata1 |= MCONTROL_EXECUTE;
611 if (trigger->read)
612 tdata1 |= MCONTROL_LOAD;
613 if (trigger->write)
614 tdata1 |= MCONTROL_STORE;
615
616 riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
617
618 uint64_t tdata1_rb;
619 int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
620 if (result != ERROR_OK)
621 return result;
622 LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
623
624 if (tdata1 != tdata1_rb) {
625 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
626 PRIx64 " to tdata1 it contains 0x%" PRIx64,
627 tdata1, tdata1_rb);
628 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
629 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
630 }
631
632 riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
633
634 return ERROR_OK;
635 }
636
637 static int maybe_add_trigger_t6(struct target *target,
638 struct trigger *trigger, uint64_t tdata1)
639 {
640 RISCV_INFO(r);
641
642 /* tselect is already set */
643 if (tdata1 & (CSR_MCONTROL6_EXECUTE | CSR_MCONTROL6_STORE | CSR_MCONTROL6_LOAD)) {
644 /* Trigger is already in use, presumably by user code. */
645 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
646 }
647
648 /* address/data match trigger */
649 tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
650 tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION,
651 MCONTROL_ACTION_DEBUG_MODE);
652 tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, MCONTROL_MATCH_EQUAL);
653 tdata1 |= CSR_MCONTROL6_M;
654 if (r->misa & (1 << ('H' - 'A')))
655 tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU;
656 if (r->misa & (1 << ('S' - 'A')))
657 tdata1 |= CSR_MCONTROL6_S;
658 if (r->misa & (1 << ('U' - 'A')))
659 tdata1 |= CSR_MCONTROL6_U;
660
661 if (trigger->execute)
662 tdata1 |= CSR_MCONTROL6_EXECUTE;
663 if (trigger->read)
664 tdata1 |= CSR_MCONTROL6_LOAD;
665 if (trigger->write)
666 tdata1 |= CSR_MCONTROL6_STORE;
667
668 riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
669
670 uint64_t tdata1_rb;
671 int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
672 if (result != ERROR_OK)
673 return result;
674 LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
675
676 if (tdata1 != tdata1_rb) {
677 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
678 PRIx64 " to tdata1 it contains 0x%" PRIx64,
679 tdata1, tdata1_rb);
680 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
681 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
682 }
683
684 riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
685
686 return ERROR_OK;
687 }
688
689 static int add_trigger(struct target *target, struct trigger *trigger)
690 {
691 RISCV_INFO(r);
692
693 if (riscv_enumerate_triggers(target) != ERROR_OK)
694 return ERROR_FAIL;
695
696 riscv_reg_t tselect;
697 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
698 return ERROR_FAIL;
699
700 unsigned int i;
701 for (i = 0; i < r->trigger_count; i++) {
702 if (r->trigger_unique_id[i] != -1)
703 continue;
704
705 riscv_set_register(target, GDB_REGNO_TSELECT, i);
706
707 uint64_t tdata1;
708 int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
709 if (result != ERROR_OK)
710 return result;
711 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
712
713 switch (type) {
714 case 1:
715 result = maybe_add_trigger_t1(target, trigger, tdata1);
716 break;
717 case 2:
718 result = maybe_add_trigger_t2(target, trigger, tdata1);
719 break;
720 case 6:
721 result = maybe_add_trigger_t6(target, trigger, tdata1);
722 break;
723 default:
724 LOG_DEBUG("trigger %d has unknown type %d", i, type);
725 continue;
726 }
727
728 if (result != ERROR_OK)
729 continue;
730
731 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
732 i, type, trigger->unique_id);
733 r->trigger_unique_id[i] = trigger->unique_id;
734 break;
735 }
736
737 riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
738
739 if (i >= r->trigger_count) {
740 LOG_ERROR("Couldn't find an available hardware trigger.");
741 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
742 }
743
744 return ERROR_OK;
745 }
746
747 /**
748 * Write one memory item of given "size". Use memory access of given "access_size".
749 * Utilize read-modify-write, if needed.
750 * */
751 static int write_by_given_size(struct target *target, target_addr_t address,
752 uint32_t size, uint8_t *buffer, uint32_t access_size)
753 {
754 assert(size == 1 || size == 2 || size == 4 || size == 8);
755 assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
756
757 if (access_size <= size && address % access_size == 0)
758 /* Can do the memory access directly without a helper buffer. */
759 return target_write_memory(target, address, access_size, size / access_size, buffer);
760
761 unsigned int offset_head = address % access_size;
762 unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
763 uint8_t helper_buf[n_blocks * access_size];
764
765 /* Read from memory */
766 if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
767 return ERROR_FAIL;
768
769 /* Modify and write back */
770 memcpy(helper_buf + offset_head, buffer, size);
771 return target_write_memory(target, address - offset_head, access_size, n_blocks, helper_buf);
772 }
773
774 /**
775 * Read one memory item of given "size". Use memory access of given "access_size".
776 * Read larger section of memory and pick out the required portion, if needed.
777 * */
778 static int read_by_given_size(struct target *target, target_addr_t address,
779 uint32_t size, uint8_t *buffer, uint32_t access_size)
780 {
781 assert(size == 1 || size == 2 || size == 4 || size == 8);
782 assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
783
784 if (access_size <= size && address % access_size == 0)
785 /* Can do the memory access directly without a helper buffer. */
786 return target_read_memory(target, address, access_size, size / access_size, buffer);
787
788 unsigned int offset_head = address % access_size;
789 unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
790 uint8_t helper_buf[n_blocks * access_size];
791
792 /* Read from memory */
793 if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
794 return ERROR_FAIL;
795
796 /* Pick the requested portion from the buffer */
797 memcpy(buffer, helper_buf + offset_head, size);
798 return ERROR_OK;
799 }
800
801 /**
802 * Write one memory item using any memory access size that will work.
803 * Utilize read-modify-write, if needed.
804 * */
805 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
806 {
807 assert(size == 1 || size == 2 || size == 4 || size == 8);
808
809 /* Find access size that correspond to data size and the alignment. */
810 unsigned int preferred_size = size;
811 while (address % preferred_size != 0)
812 preferred_size /= 2;
813
814 /* First try the preferred (most natural) access size. */
815 if (write_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
816 return ERROR_OK;
817
818 /* On failure, try other access sizes.
819 Minimize the number of accesses by trying first the largest size. */
820 for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
821 if (access_size == preferred_size)
822 /* Already tried this size. */
823 continue;
824
825 if (write_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
826 return ERROR_OK;
827 }
828
829 /* No access attempt succeeded. */
830 return ERROR_FAIL;
831 }
832
833 /**
834 * Read one memory item using any memory access size that will work.
835 * Read larger section of memory and pick out the required portion, if needed.
836 * */
837 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
838 {
839 assert(size == 1 || size == 2 || size == 4 || size == 8);
840
841 /* Find access size that correspond to data size and the alignment. */
842 unsigned int preferred_size = size;
843 while (address % preferred_size != 0)
844 preferred_size /= 2;
845
846 /* First try the preferred (most natural) access size. */
847 if (read_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
848 return ERROR_OK;
849
850 /* On failure, try other access sizes.
851 Minimize the number of accesses by trying first the largest size. */
852 for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
853 if (access_size == preferred_size)
854 /* Already tried this size. */
855 continue;
856
857 if (read_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
858 return ERROR_OK;
859 }
860
861 /* No access attempt succeeded. */
862 return ERROR_FAIL;
863 }
864
865 static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
866 {
867 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
868 assert(breakpoint);
869 if (breakpoint->type == BKPT_SOFT) {
870 /** @todo check RVC for size/alignment */
871 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
872 LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
873 return ERROR_FAIL;
874 }
875
876 if (0 != (breakpoint->address % 2)) {
877 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
878 return ERROR_FAIL;
879 }
880
881 /* Read the original instruction. */
882 if (riscv_read_by_any_size(
883 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
884 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
885 breakpoint->address);
886 return ERROR_FAIL;
887 }
888
889 uint8_t buff[4] = { 0 };
890 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
891 /* Write the ebreak instruction. */
892 if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
893 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
894 TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
895 return ERROR_FAIL;
896 }
897
898 } else if (breakpoint->type == BKPT_HARD) {
899 struct trigger trigger;
900 trigger_from_breakpoint(&trigger, breakpoint);
901 int const result = add_trigger(target, &trigger);
902 if (result != ERROR_OK)
903 return result;
904 } else {
905 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
906 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
907 }
908
909 breakpoint->is_set = true;
910 return ERROR_OK;
911 }
912
913 static int remove_trigger(struct target *target, struct trigger *trigger)
914 {
915 RISCV_INFO(r);
916
917 if (riscv_enumerate_triggers(target) != ERROR_OK)
918 return ERROR_FAIL;
919
920 unsigned int i;
921 for (i = 0; i < r->trigger_count; i++) {
922 if (r->trigger_unique_id[i] == trigger->unique_id)
923 break;
924 }
925 if (i >= r->trigger_count) {
926 LOG_ERROR("Couldn't find the hardware resources used by hardware "
927 "trigger.");
928 return ERROR_FAIL;
929 }
930 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
931 trigger->unique_id);
932
933 riscv_reg_t tselect;
934 int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
935 if (result != ERROR_OK)
936 return result;
937 riscv_set_register(target, GDB_REGNO_TSELECT, i);
938 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
939 riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
940 r->trigger_unique_id[i] = -1;
941
942 return ERROR_OK;
943 }
944
945 static int riscv_remove_breakpoint(struct target *target,
946 struct breakpoint *breakpoint)
947 {
948 if (breakpoint->type == BKPT_SOFT) {
949 /* Write the original instruction. */
950 if (riscv_write_by_any_size(
951 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
952 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
953 "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
954 return ERROR_FAIL;
955 }
956
957 } else if (breakpoint->type == BKPT_HARD) {
958 struct trigger trigger;
959 trigger_from_breakpoint(&trigger, breakpoint);
960 int result = remove_trigger(target, &trigger);
961 if (result != ERROR_OK)
962 return result;
963
964 } else {
965 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
966 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
967 }
968
969 breakpoint->is_set = false;
970
971 return ERROR_OK;
972 }
973
974 static void trigger_from_watchpoint(struct trigger *trigger,
975 const struct watchpoint *watchpoint)
976 {
977 trigger->address = watchpoint->address;
978 trigger->length = watchpoint->length;
979 trigger->mask = watchpoint->mask;
980 trigger->value = watchpoint->value;
981 trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
982 trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
983 trigger->execute = false;
984 /* unique_id is unique across both breakpoints and watchpoints. */
985 trigger->unique_id = watchpoint->unique_id;
986 }
987
988 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
989 {
990 struct trigger trigger;
991 trigger_from_watchpoint(&trigger, watchpoint);
992
993 int result = add_trigger(target, &trigger);
994 if (result != ERROR_OK)
995 return result;
996 watchpoint->is_set = true;
997
998 return ERROR_OK;
999 }
1000
1001 int riscv_remove_watchpoint(struct target *target,
1002 struct watchpoint *watchpoint)
1003 {
1004 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
1005
1006 struct trigger trigger;
1007 trigger_from_watchpoint(&trigger, watchpoint);
1008
1009 int result = remove_trigger(target, &trigger);
1010 if (result != ERROR_OK)
1011 return result;
1012 watchpoint->is_set = false;
1013
1014 return ERROR_OK;
1015 }
1016
1017 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1018 * current halt.
1019 *
1020 * The GDB server uses this information to tell GDB what data address has
1021 * been hit, which enables GDB to print the hit variable along with its old
1022 * and new value. */
1023 static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1024 {
1025 struct watchpoint *wp = target->watchpoints;
1026
1027 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
1028
1029 /*TODO instead of disassembling the instruction that we think caused the
1030 * trigger, check the hit bit of each watchpoint first. The hit bit is
1031 * simpler and more reliable to check but as it is optional and relatively
1032 * new, not all hardware will implement it */
1033 riscv_reg_t dpc;
1034 riscv_get_register(target, &dpc, GDB_REGNO_DPC);
1035 const uint8_t length = 4;
1036 LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
1037
1038 /* fetch the instruction at dpc */
1039 uint8_t buffer[length];
1040 if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
1041 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
1042 return ERROR_FAIL;
1043 }
1044
1045 uint32_t instruction = 0;
1046
1047 for (int i = 0; i < length; i++) {
1048 LOG_DEBUG("Next byte is %x", buffer[i]);
1049 instruction += (buffer[i] << 8 * i);
1050 }
1051 LOG_DEBUG("Full instruction is %x", instruction);
1052
1053 /* find out which memory address is accessed by the instruction at dpc */
1054 /* opcode is first 7 bits of the instruction */
1055 uint8_t opcode = instruction & 0x7F;
1056 uint32_t rs1;
1057 int16_t imm;
1058 riscv_reg_t mem_addr;
1059
1060 if (opcode == MATCH_LB || opcode == MATCH_SB) {
1061 rs1 = (instruction & 0xf8000) >> 15;
1062 riscv_get_register(target, &mem_addr, rs1);
1063
1064 if (opcode == MATCH_SB) {
1065 LOG_DEBUG("%x is store instruction", instruction);
1066 imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
1067 } else {
1068 LOG_DEBUG("%x is load instruction", instruction);
1069 imm = (instruction & 0xfff00000) >> 20;
1070 }
1071 /* sign extend 12-bit imm to 16-bits */
1072 if (imm & (1 << 11))
1073 imm |= 0xf000;
1074 mem_addr += imm;
1075 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
1076 } else {
1077 LOG_DEBUG("%x is not a RV32I load or store", instruction);
1078 return ERROR_FAIL;
1079 }
1080
1081 while (wp) {
1082 /*TODO support length/mask */
1083 if (wp->address == mem_addr) {
1084 *hit_watchpoint = wp;
1085 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
1086 return ERROR_OK;
1087 }
1088 wp = wp->next;
1089 }
1090
1091 /* No match found - either we hit a watchpoint caused by an instruction that
1092 * this function does not yet disassemble, or we hit a breakpoint.
1093 *
1094 * OpenOCD will behave as if this function had never been implemented i.e.
1095 * report the halt to GDB with no address information. */
1096 return ERROR_FAIL;
1097 }
1098
1099
1100 static int oldriscv_step(struct target *target, int current, uint32_t address,
1101 int handle_breakpoints)
1102 {
1103 struct target_type *tt = get_target_type(target);
1104 return tt->step(target, current, address, handle_breakpoints);
1105 }
1106
1107 static int old_or_new_riscv_step(struct target *target, int current,
1108 target_addr_t address, int handle_breakpoints)
1109 {
1110 RISCV_INFO(r);
1111 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1112 if (!r->is_halted)
1113 return oldriscv_step(target, current, address, handle_breakpoints);
1114 else
1115 return riscv_openocd_step(target, current, address, handle_breakpoints);
1116 }
1117
1118
1119 static int riscv_examine(struct target *target)
1120 {
1121 LOG_DEBUG("riscv_examine()");
1122 if (target_was_examined(target)) {
1123 LOG_DEBUG("Target was already examined.");
1124 return ERROR_OK;
1125 }
1126
1127 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1128
1129 RISCV_INFO(info);
1130 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1131 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1132 info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
1133 LOG_DEBUG(" version=0x%x", info->dtm_version);
1134
1135 struct target_type *tt = get_target_type(target);
1136 if (!tt)
1137 return ERROR_FAIL;
1138
1139 int result = tt->init_target(info->cmd_ctx, target);
1140 if (result != ERROR_OK)
1141 return result;
1142
1143 return tt->examine(target);
1144 }
1145
1146 static int oldriscv_poll(struct target *target)
1147 {
1148 struct target_type *tt = get_target_type(target);
1149 return tt->poll(target);
1150 }
1151
1152 static int old_or_new_riscv_poll(struct target *target)
1153 {
1154 RISCV_INFO(r);
1155 if (!r->is_halted)
1156 return oldriscv_poll(target);
1157 else
1158 return riscv_openocd_poll(target);
1159 }
1160
1161 int riscv_select_current_hart(struct target *target)
1162 {
1163 return riscv_set_current_hartid(target, target->coreid);
1164 }
1165
1166 static int halt_prep(struct target *target)
1167 {
1168 RISCV_INFO(r);
1169
1170 LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
1171 target->debug_reason);
1172 if (riscv_select_current_hart(target) != ERROR_OK)
1173 return ERROR_FAIL;
1174 if (riscv_is_halted(target)) {
1175 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1176 target_name(target), target->debug_reason);
1177 } else {
1178 if (r->halt_prep(target) != ERROR_OK)
1179 return ERROR_FAIL;
1180 r->prepped = true;
1181 }
1182
1183 return ERROR_OK;
1184 }
1185
1186 static int riscv_halt_go_all_harts(struct target *target)
1187 {
1188 RISCV_INFO(r);
1189
1190 if (riscv_select_current_hart(target) != ERROR_OK)
1191 return ERROR_FAIL;
1192 if (riscv_is_halted(target)) {
1193 LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
1194 } else {
1195 if (r->halt_go(target) != ERROR_OK)
1196 return ERROR_FAIL;
1197 }
1198
1199 riscv_invalidate_register_cache(target);
1200
1201 return ERROR_OK;
1202 }
1203
1204 static int halt_go(struct target *target)
1205 {
1206 RISCV_INFO(r);
1207 int result;
1208 if (!r->is_halted) {
1209 struct target_type *tt = get_target_type(target);
1210 result = tt->halt(target);
1211 } else {
1212 result = riscv_halt_go_all_harts(target);
1213 }
1214 target->state = TARGET_HALTED;
1215 if (target->debug_reason == DBG_REASON_NOTHALTED)
1216 target->debug_reason = DBG_REASON_DBGRQ;
1217
1218 return result;
1219 }
1220
1221 static int halt_finish(struct target *target)
1222 {
1223 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1224 }
1225
1226 int riscv_halt(struct target *target)
1227 {
1228 RISCV_INFO(r);
1229
1230 if (!r->is_halted) {
1231 struct target_type *tt = get_target_type(target);
1232 return tt->halt(target);
1233 }
1234
1235 LOG_DEBUG("[%d] halting all harts", target->coreid);
1236
1237 int result = ERROR_OK;
1238 if (target->smp) {
1239 struct target_list *tlist;
1240 foreach_smp_target(tlist, target->smp_targets) {
1241 struct target *t = tlist->target;
1242 if (halt_prep(t) != ERROR_OK)
1243 result = ERROR_FAIL;
1244 }
1245
1246 foreach_smp_target(tlist, target->smp_targets) {
1247 struct target *t = tlist->target;
1248 struct riscv_info *i = riscv_info(t);
1249 if (i->prepped) {
1250 if (halt_go(t) != ERROR_OK)
1251 result = ERROR_FAIL;
1252 }
1253 }
1254
1255 foreach_smp_target(tlist, target->smp_targets) {
1256 struct target *t = tlist->target;
1257 if (halt_finish(t) != ERROR_OK)
1258 return ERROR_FAIL;
1259 }
1260
1261 } else {
1262 if (halt_prep(target) != ERROR_OK)
1263 result = ERROR_FAIL;
1264 if (halt_go(target) != ERROR_OK)
1265 result = ERROR_FAIL;
1266 if (halt_finish(target) != ERROR_OK)
1267 return ERROR_FAIL;
1268 }
1269
1270 return result;
1271 }
1272
1273 static int riscv_assert_reset(struct target *target)
1274 {
1275 LOG_DEBUG("[%d]", target->coreid);
1276 struct target_type *tt = get_target_type(target);
1277 riscv_invalidate_register_cache(target);
1278 return tt->assert_reset(target);
1279 }
1280
1281 static int riscv_deassert_reset(struct target *target)
1282 {
1283 LOG_DEBUG("[%d]", target->coreid);
1284 struct target_type *tt = get_target_type(target);
1285 return tt->deassert_reset(target);
1286 }
1287
1288 static int riscv_resume_prep_all_harts(struct target *target)
1289 {
1290 RISCV_INFO(r);
1291
1292 LOG_DEBUG("[%s] prep hart", target_name(target));
1293 if (riscv_select_current_hart(target) != ERROR_OK)
1294 return ERROR_FAIL;
1295 if (riscv_is_halted(target)) {
1296 if (r->resume_prep(target) != ERROR_OK)
1297 return ERROR_FAIL;
1298 } else {
1299 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1300 target_name(target));
1301 }
1302
1303 LOG_DEBUG("[%s] mark as prepped", target_name(target));
1304 r->prepped = true;
1305
1306 return ERROR_OK;
1307 }
1308
1309 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1310 static int disable_triggers(struct target *target, riscv_reg_t *state)
1311 {
1312 RISCV_INFO(r);
1313
1314 LOG_DEBUG("deal with triggers");
1315
1316 if (riscv_enumerate_triggers(target) != ERROR_OK)
1317 return ERROR_FAIL;
1318
1319 if (r->manual_hwbp_set) {
1320 /* Look at every trigger that may have been set. */
1321 riscv_reg_t tselect;
1322 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1323 return ERROR_FAIL;
1324 for (unsigned int t = 0; t < r->trigger_count; t++) {
1325 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1326 return ERROR_FAIL;
1327 riscv_reg_t tdata1;
1328 if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
1329 return ERROR_FAIL;
1330 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
1331 state[t] = tdata1;
1332 if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
1333 return ERROR_FAIL;
1334 }
1335 }
1336 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1337 return ERROR_FAIL;
1338
1339 } else {
1340 /* Just go through the triggers we manage. */
1341 struct watchpoint *watchpoint = target->watchpoints;
1342 int i = 0;
1343 while (watchpoint) {
1344 LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set);
1345 state[i] = watchpoint->is_set;
1346 if (watchpoint->is_set) {
1347 if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
1348 return ERROR_FAIL;
1349 }
1350 watchpoint = watchpoint->next;
1351 i++;
1352 }
1353 }
1354
1355 return ERROR_OK;
1356 }
1357
1358 static int enable_triggers(struct target *target, riscv_reg_t *state)
1359 {
1360 RISCV_INFO(r);
1361
1362 if (r->manual_hwbp_set) {
1363 /* Look at every trigger that may have been set. */
1364 riscv_reg_t tselect;
1365 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1366 return ERROR_FAIL;
1367 for (unsigned int t = 0; t < r->trigger_count; t++) {
1368 if (state[t] != 0) {
1369 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1370 return ERROR_FAIL;
1371 if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
1372 return ERROR_FAIL;
1373 }
1374 }
1375 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1376 return ERROR_FAIL;
1377
1378 } else {
1379 struct watchpoint *watchpoint = target->watchpoints;
1380 int i = 0;
1381 while (watchpoint) {
1382 LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
1383 if (state[i]) {
1384 if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
1385 return ERROR_FAIL;
1386 }
1387 watchpoint = watchpoint->next;
1388 i++;
1389 }
1390 }
1391
1392 return ERROR_OK;
1393 }
1394
1395 /**
1396 * Get everything ready to resume.
1397 */
1398 static int resume_prep(struct target *target, int current,
1399 target_addr_t address, int handle_breakpoints, int debug_execution)
1400 {
1401 RISCV_INFO(r);
1402 LOG_DEBUG("[%d]", target->coreid);
1403
1404 if (!current)
1405 riscv_set_register(target, GDB_REGNO_PC, address);
1406
1407 if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1408 /* To be able to run off a trigger, disable all the triggers, step, and
1409 * then resume as usual. */
1410 riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
1411
1412 if (disable_triggers(target, trigger_state) != ERROR_OK)
1413 return ERROR_FAIL;
1414
1415 if (old_or_new_riscv_step(target, true, 0, false) != ERROR_OK)
1416 return ERROR_FAIL;
1417
1418 if (enable_triggers(target, trigger_state) != ERROR_OK)
1419 return ERROR_FAIL;
1420 }
1421
1422 if (r->is_halted) {
1423 if (riscv_resume_prep_all_harts(target) != ERROR_OK)
1424 return ERROR_FAIL;
1425 }
1426
1427 LOG_DEBUG("[%d] mark as prepped", target->coreid);
1428 r->prepped = true;
1429
1430 return ERROR_OK;
1431 }
1432
1433 /**
1434 * Resume all the harts that have been prepped, as close to instantaneous as
1435 * possible.
1436 */
1437 static int resume_go(struct target *target, int current,
1438 target_addr_t address, int handle_breakpoints, int debug_execution)
1439 {
1440 RISCV_INFO(r);
1441 int result;
1442 if (!r->is_halted) {
1443 struct target_type *tt = get_target_type(target);
1444 result = tt->resume(target, current, address, handle_breakpoints,
1445 debug_execution);
1446 } else {
1447 result = riscv_resume_go_all_harts(target);
1448 }
1449
1450 return result;
1451 }
1452
1453 static int resume_finish(struct target *target)
1454 {
1455 register_cache_invalidate(target->reg_cache);
1456
1457 target->state = TARGET_RUNNING;
1458 target->debug_reason = DBG_REASON_NOTHALTED;
1459 return target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1460 }
1461
1462 /**
1463 * @par single_hart When true, only resume a single hart even if SMP is
1464 * configured. This is used to run algorithms on just one hart.
1465 */
1466 static int riscv_resume(
1467 struct target *target,
1468 int current,
1469 target_addr_t address,
1470 int handle_breakpoints,
1471 int debug_execution,
1472 bool single_hart)
1473 {
1474 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1475 int result = ERROR_OK;
1476 if (target->smp && !single_hart) {
1477 struct target_list *tlist;
1478 foreach_smp_target_direction(resume_order == RO_NORMAL,
1479 tlist, target->smp_targets) {
1480 struct target *t = tlist->target;
1481 if (resume_prep(t, current, address, handle_breakpoints,
1482 debug_execution) != ERROR_OK)
1483 result = ERROR_FAIL;
1484 }
1485
1486 foreach_smp_target_direction(resume_order == RO_NORMAL,
1487 tlist, target->smp_targets) {
1488 struct target *t = tlist->target;
1489 struct riscv_info *i = riscv_info(t);
1490 if (i->prepped) {
1491 if (resume_go(t, current, address, handle_breakpoints,
1492 debug_execution) != ERROR_OK)
1493 result = ERROR_FAIL;
1494 }
1495 }
1496
1497 foreach_smp_target_direction(resume_order == RO_NORMAL,
1498 tlist, target->smp_targets) {
1499 struct target *t = tlist->target;
1500 if (resume_finish(t) != ERROR_OK)
1501 return ERROR_FAIL;
1502 }
1503
1504 } else {
1505 if (resume_prep(target, current, address, handle_breakpoints,
1506 debug_execution) != ERROR_OK)
1507 result = ERROR_FAIL;
1508 if (resume_go(target, current, address, handle_breakpoints,
1509 debug_execution) != ERROR_OK)
1510 result = ERROR_FAIL;
1511 if (resume_finish(target) != ERROR_OK)
1512 return ERROR_FAIL;
1513 }
1514
1515 return result;
1516 }
1517
1518 static int riscv_target_resume(struct target *target, int current, target_addr_t address,
1519 int handle_breakpoints, int debug_execution)
1520 {
1521 return riscv_resume(target, current, address, handle_breakpoints,
1522 debug_execution, false);
1523 }
1524
1525 static int riscv_mmu(struct target *target, int *enabled)
1526 {
1527 if (!riscv_enable_virt2phys) {
1528 *enabled = 0;
1529 return ERROR_OK;
1530 }
1531
1532 /* Don't use MMU in explicit or effective M (machine) mode */
1533 riscv_reg_t priv;
1534 if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
1535 LOG_ERROR("Failed to read priv register.");
1536 return ERROR_FAIL;
1537 }
1538
1539 riscv_reg_t mstatus;
1540 if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
1541 LOG_ERROR("Failed to read mstatus register.");
1542 return ERROR_FAIL;
1543 }
1544
1545 if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
1546 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
1547 *enabled = 0;
1548 return ERROR_OK;
1549 }
1550
1551 riscv_reg_t satp;
1552 if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
1553 LOG_DEBUG("Couldn't read SATP.");
1554 /* If we can't read SATP, then there must not be an MMU. */
1555 *enabled = 0;
1556 return ERROR_OK;
1557 }
1558
1559 if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
1560 LOG_DEBUG("MMU is disabled.");
1561 *enabled = 0;
1562 } else {
1563 LOG_DEBUG("MMU is enabled.");
1564 *enabled = 1;
1565 }
1566
1567 return ERROR_OK;
1568 }
1569
1570 static int riscv_address_translate(struct target *target,
1571 target_addr_t virtual, target_addr_t *physical)
1572 {
1573 RISCV_INFO(r);
1574 riscv_reg_t satp_value;
1575 int mode;
1576 uint64_t ppn_value;
1577 target_addr_t table_address;
1578 const virt2phys_info_t *info;
1579 uint64_t pte = 0;
1580 int i;
1581
1582 int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
1583 if (result != ERROR_OK)
1584 return result;
1585
1586 unsigned xlen = riscv_xlen(target);
1587 mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
1588 switch (mode) {
1589 case SATP_MODE_SV32:
1590 info = &sv32;
1591 break;
1592 case SATP_MODE_SV39:
1593 info = &sv39;
1594 break;
1595 case SATP_MODE_SV48:
1596 info = &sv48;
1597 break;
1598 case SATP_MODE_OFF:
1599 LOG_ERROR("No translation or protection." \
1600 " (satp: 0x%" PRIx64 ")", satp_value);
1601 return ERROR_FAIL;
1602 default:
1603 LOG_ERROR("The translation mode is not supported." \
1604 " (satp: 0x%" PRIx64 ")", satp_value);
1605 return ERROR_FAIL;
1606 }
1607 LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
1608
1609 /* verify bits xlen-1:va_bits-1 are all equal */
1610 assert(xlen >= info->va_bits);
1611 target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
1612 target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
1613 if (masked_msbs != 0 && masked_msbs != mask) {
1614 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
1615 "for %s mode.", virtual, info->name);
1616 return ERROR_FAIL;
1617 }
1618
1619 ppn_value = get_field(satp_value, RISCV_SATP_PPN(xlen));
1620 table_address = ppn_value << RISCV_PGSHIFT;
1621 i = info->level - 1;
1622 while (i >= 0) {
1623 uint64_t vpn = virtual >> info->vpn_shift[i];
1624 vpn &= info->vpn_mask[i];
1625 target_addr_t pte_address = table_address +
1626 (vpn << info->pte_shift);
1627 uint8_t buffer[8];
1628 assert(info->pte_shift <= 3);
1629 int retval = r->read_memory(target, pte_address,
1630 4, (1 << info->pte_shift) / 4, buffer, 4);
1631 if (retval != ERROR_OK)
1632 return ERROR_FAIL;
1633
1634 if (info->pte_shift == 2)
1635 pte = buf_get_u32(buffer, 0, 32);
1636 else
1637 pte = buf_get_u64(buffer, 0, 64);
1638
1639 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
1640 pte_address, pte);
1641
1642 if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
1643 return ERROR_FAIL;
1644
1645 if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
1646 break;
1647
1648 i--;
1649 if (i < 0)
1650 break;
1651 ppn_value = pte >> PTE_PPN_SHIFT;
1652 table_address = ppn_value << RISCV_PGSHIFT;
1653 }
1654
1655 if (i < 0) {
1656 LOG_ERROR("Couldn't find the PTE.");
1657 return ERROR_FAIL;
1658 }
1659
1660 /* Make sure to clear out the high bits that may be set. */
1661 *physical = virtual & (((target_addr_t)1 << info->va_bits) - 1);
1662
1663 while (i < info->level) {
1664 ppn_value = pte >> info->pte_ppn_shift[i];
1665 ppn_value &= info->pte_ppn_mask[i];
1666 *physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
1667 info->pa_ppn_shift[i]);
1668 *physical |= (ppn_value << info->pa_ppn_shift[i]);
1669 i++;
1670 }
1671 LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
1672 *physical);
1673
1674 return ERROR_OK;
1675 }
1676
1677 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
1678 {
1679 int enabled;
1680 if (riscv_mmu(target, &enabled) == ERROR_OK) {
1681 if (!enabled)
1682 return ERROR_FAIL;
1683
1684 if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
1685 return ERROR_OK;
1686 }
1687
1688 return ERROR_FAIL;
1689 }
1690
1691 static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
1692 uint32_t size, uint32_t count, uint8_t *buffer)
1693 {
1694 RISCV_INFO(r);
1695 if (riscv_select_current_hart(target) != ERROR_OK)
1696 return ERROR_FAIL;
1697 return r->read_memory(target, phys_address, size, count, buffer, size);
1698 }
1699
1700 static int riscv_read_memory(struct target *target, target_addr_t address,
1701 uint32_t size, uint32_t count, uint8_t *buffer)
1702 {
1703 if (count == 0) {
1704 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address);
1705 return ERROR_OK;
1706 }
1707
1708 if (riscv_select_current_hart(target) != ERROR_OK)
1709 return ERROR_FAIL;
1710
1711 target_addr_t physical_addr;
1712 if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1713 address = physical_addr;
1714
1715 RISCV_INFO(r);
1716 return r->read_memory(target, address, size, count, buffer, size);
1717 }
1718
1719 static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
1720 uint32_t size, uint32_t count, const uint8_t *buffer)
1721 {
1722 if (riscv_select_current_hart(target) != ERROR_OK)
1723 return ERROR_FAIL;
1724 struct target_type *tt = get_target_type(target);
1725 return tt->write_memory(target, phys_address, size, count, buffer);
1726 }
1727
1728 static int riscv_write_memory(struct target *target, target_addr_t address,
1729 uint32_t size, uint32_t count, const uint8_t *buffer)
1730 {
1731 if (count == 0) {
1732 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address);
1733 return ERROR_OK;
1734 }
1735
1736 if (riscv_select_current_hart(target) != ERROR_OK)
1737 return ERROR_FAIL;
1738
1739 target_addr_t physical_addr;
1740 if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1741 address = physical_addr;
1742
1743 struct target_type *tt = get_target_type(target);
1744 return tt->write_memory(target, address, size, count, buffer);
1745 }
1746
1747 static const char *riscv_get_gdb_arch(const struct target *target)
1748 {
1749 switch (riscv_xlen(target)) {
1750 case 32:
1751 return "riscv:rv32";
1752 case 64:
1753 return "riscv:rv64";
1754 }
1755 LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
1756 return NULL;
1757 }
1758
1759 static int riscv_get_gdb_reg_list_internal(struct target *target,
1760 struct reg **reg_list[], int *reg_list_size,
1761 enum target_register_class reg_class, bool read)
1762 {
1763 RISCV_INFO(r);
1764 LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1765 target_name(target), r->current_hartid, reg_class, read);
1766
1767 if (!target->reg_cache) {
1768 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1769 return ERROR_FAIL;
1770 }
1771
1772 if (riscv_select_current_hart(target) != ERROR_OK)
1773 return ERROR_FAIL;
1774
1775 switch (reg_class) {
1776 case REG_CLASS_GENERAL:
1777 *reg_list_size = 33;
1778 break;
1779 case REG_CLASS_ALL:
1780 *reg_list_size = target->reg_cache->num_regs;
1781 break;
1782 default:
1783 LOG_ERROR("Unsupported reg_class: %d", reg_class);
1784 return ERROR_FAIL;
1785 }
1786
1787 *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1788 if (!*reg_list)
1789 return ERROR_FAIL;
1790
1791 for (int i = 0; i < *reg_list_size; i++) {
1792 assert(!target->reg_cache->reg_list[i].valid ||
1793 target->reg_cache->reg_list[i].size > 0);
1794 (*reg_list)[i] = &target->reg_cache->reg_list[i];
1795 if (read &&
1796 target->reg_cache->reg_list[i].exist &&
1797 !target->reg_cache->reg_list[i].valid) {
1798 if (target->reg_cache->reg_list[i].type->get(
1799 &target->reg_cache->reg_list[i]) != ERROR_OK)
1800 return ERROR_FAIL;
1801 }
1802 }
1803
1804 return ERROR_OK;
1805 }
1806
1807 static int riscv_get_gdb_reg_list_noread(struct target *target,
1808 struct reg **reg_list[], int *reg_list_size,
1809 enum target_register_class reg_class)
1810 {
1811 return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1812 reg_class, false);
1813 }
1814
1815 static int riscv_get_gdb_reg_list(struct target *target,
1816 struct reg **reg_list[], int *reg_list_size,
1817 enum target_register_class reg_class)
1818 {
1819 return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1820 reg_class, true);
1821 }
1822
1823 static int riscv_arch_state(struct target *target)
1824 {
1825 struct target_type *tt = get_target_type(target);
1826 return tt->arch_state(target);
1827 }
1828
1829 /* Algorithm must end with a software breakpoint instruction. */
1830 static int riscv_run_algorithm(struct target *target, int num_mem_params,
1831 struct mem_param *mem_params, int num_reg_params,
1832 struct reg_param *reg_params, target_addr_t entry_point,
1833 target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
1834 {
1835 RISCV_INFO(info);
1836
1837 if (num_mem_params > 0) {
1838 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1839 return ERROR_FAIL;
1840 }
1841
1842 if (target->state != TARGET_HALTED) {
1843 LOG_TARGET_ERROR(target, "not halted (run target algo)");
1844 return ERROR_TARGET_NOT_HALTED;
1845 }
1846
1847 /* Save registers */
1848 struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", true);
1849 if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1850 return ERROR_FAIL;
1851 uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1852 LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
1853
1854 uint64_t saved_regs[32];
1855 for (int i = 0; i < num_reg_params; i++) {
1856 LOG_DEBUG("save %s", reg_params[i].reg_name);
1857 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1858 if (!r) {
1859 LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1860 return ERROR_FAIL;
1861 }
1862
1863 if (r->size != reg_params[i].size) {
1864 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1865 reg_params[i].reg_name, r->size, reg_params[i].size);
1866 return ERROR_FAIL;
1867 }
1868
1869 if (r->number > GDB_REGNO_XPR31) {
1870 LOG_ERROR("Only GPRs can be use as argument registers.");
1871 return ERROR_FAIL;
1872 }
1873
1874 if (r->type->get(r) != ERROR_OK)
1875 return ERROR_FAIL;
1876 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1877
1878 if (reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT) {
1879 if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1880 return ERROR_FAIL;
1881 }
1882 }
1883
1884
1885 /* Disable Interrupts before attempting to run the algorithm. */
1886 uint64_t current_mstatus;
1887 uint8_t mstatus_bytes[8] = { 0 };
1888
1889 LOG_DEBUG("Disabling Interrupts");
1890 struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1891 "mstatus", true);
1892 if (!reg_mstatus) {
1893 LOG_ERROR("Couldn't find mstatus!");
1894 return ERROR_FAIL;
1895 }
1896
1897 reg_mstatus->type->get(reg_mstatus);
1898 current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1899 uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1900 buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
1901 ie_mask, 0));
1902
1903 reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1904
1905 /* Run algorithm */
1906 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1907 if (riscv_resume(target, 0, entry_point, 0, 0, true) != ERROR_OK)
1908 return ERROR_FAIL;
1909
1910 int64_t start = timeval_ms();
1911 while (target->state != TARGET_HALTED) {
1912 LOG_DEBUG("poll()");
1913 int64_t now = timeval_ms();
1914 if (now - start > timeout_ms) {
1915 LOG_ERROR("Algorithm timed out after %" PRId64 " ms.", now - start);
1916 riscv_halt(target);
1917 old_or_new_riscv_poll(target);
1918 enum gdb_regno regnums[] = {
1919 GDB_REGNO_RA, GDB_REGNO_SP, GDB_REGNO_GP, GDB_REGNO_TP,
1920 GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_FP,
1921 GDB_REGNO_S1, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2,
1922 GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6,
1923 GDB_REGNO_A7, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4,
1924 GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8,
1925 GDB_REGNO_S9, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_T3,
1926 GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6,
1927 GDB_REGNO_PC,
1928 GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
1929 };
1930 for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
1931 enum gdb_regno regno = regnums[i];
1932 riscv_reg_t reg_value;
1933 if (riscv_get_register(target, &reg_value, regno) != ERROR_OK)
1934 break;
1935 LOG_ERROR("%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value);
1936 }
1937 return ERROR_TARGET_TIMEOUT;
1938 }
1939
1940 int result = old_or_new_riscv_poll(target);
1941 if (result != ERROR_OK)
1942 return result;
1943 }
1944
1945 /* The current hart id might have been changed in poll(). */
1946 if (riscv_select_current_hart(target) != ERROR_OK)
1947 return ERROR_FAIL;
1948
1949 if (reg_pc->type->get(reg_pc) != ERROR_OK)
1950 return ERROR_FAIL;
1951 uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1952 if (exit_point && final_pc != exit_point) {
1953 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1954 TARGET_PRIxADDR, final_pc, exit_point);
1955 return ERROR_FAIL;
1956 }
1957
1958 /* Restore Interrupts */
1959 LOG_DEBUG("Restoring Interrupts");
1960 buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
1961 reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1962
1963 /* Restore registers */
1964 uint8_t buf[8] = { 0 };
1965 buf_set_u64(buf, 0, info->xlen, saved_pc);
1966 if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1967 return ERROR_FAIL;
1968
1969 for (int i = 0; i < num_reg_params; i++) {
1970 if (reg_params[i].direction == PARAM_IN ||
1971 reg_params[i].direction == PARAM_IN_OUT) {
1972 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1973 if (r->type->get(r) != ERROR_OK) {
1974 LOG_ERROR("get(%s) failed", r->name);
1975 return ERROR_FAIL;
1976 }
1977 buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
1978 }
1979 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1980 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1981 buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
1982 if (r->type->set(r, buf) != ERROR_OK) {
1983 LOG_ERROR("set(%s) failed", r->name);
1984 return ERROR_FAIL;
1985 }
1986 }
1987
1988 return ERROR_OK;
1989 }
1990
1991 static int riscv_checksum_memory(struct target *target,
1992 target_addr_t address, uint32_t count,
1993 uint32_t *checksum)
1994 {
1995 struct working_area *crc_algorithm;
1996 struct reg_param reg_params[2];
1997 int retval;
1998
1999 LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
2000
2001 static const uint8_t riscv32_crc_code[] = {
2002 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
2003 };
2004 static const uint8_t riscv64_crc_code[] = {
2005 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
2006 };
2007
2008 static const uint8_t *crc_code;
2009
2010 unsigned xlen = riscv_xlen(target);
2011 unsigned crc_code_size;
2012 if (xlen == 32) {
2013 crc_code = riscv32_crc_code;
2014 crc_code_size = sizeof(riscv32_crc_code);
2015 } else {
2016 crc_code = riscv64_crc_code;
2017 crc_code_size = sizeof(riscv64_crc_code);
2018 }
2019
2020 if (count < crc_code_size * 4) {
2021 /* Don't use the algorithm for relatively small buffers. It's faster
2022 * just to read the memory. target_checksum_memory() will take care of
2023 * that if we fail. */
2024 return ERROR_FAIL;
2025 }
2026
2027 retval = target_alloc_working_area(target, crc_code_size, &crc_algorithm);
2028 if (retval != ERROR_OK)
2029 return retval;
2030
2031 if (crc_algorithm->address + crc_algorithm->size > address &&
2032 crc_algorithm->address < address + count) {
2033 /* Region to checksum overlaps with the work area we've been assigned.
2034 * Bail. (Would be better to manually checksum what we read there, and
2035 * use the algorithm for the rest.) */
2036 target_free_working_area(target, crc_algorithm);
2037 return ERROR_FAIL;
2038 }
2039
2040 retval = target_write_buffer(target, crc_algorithm->address, crc_code_size,
2041 crc_code);
2042 if (retval != ERROR_OK) {
2043 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
2044 crc_algorithm->address, retval);
2045 target_free_working_area(target, crc_algorithm);
2046 return retval;
2047 }
2048
2049 init_reg_param(&reg_params[0], "a0", xlen, PARAM_IN_OUT);
2050 init_reg_param(&reg_params[1], "a1", xlen, PARAM_OUT);
2051 buf_set_u64(reg_params[0].value, 0, xlen, address);
2052 buf_set_u64(reg_params[1].value, 0, xlen, count);
2053
2054 /* 20 second timeout/megabyte */
2055 unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
2056
2057 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
2058 crc_algorithm->address,
2059 0, /* Leave exit point unspecified because we don't know. */
2060 timeout, NULL);
2061
2062 if (retval == ERROR_OK)
2063 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2064 else
2065 LOG_ERROR("error executing RISC-V CRC algorithm");
2066
2067 destroy_reg_param(&reg_params[0]);
2068 destroy_reg_param(&reg_params[1]);
2069
2070 target_free_working_area(target, crc_algorithm);
2071
2072 LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
2073
2074 return retval;
2075 }
2076
2077 /*** OpenOCD Helper Functions ***/
2078
2079 enum riscv_poll_hart {
2080 RPH_NO_CHANGE,
2081 RPH_DISCOVERED_HALTED,
2082 RPH_DISCOVERED_RUNNING,
2083 RPH_ERROR
2084 };
2085 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
2086 {
2087 RISCV_INFO(r);
2088 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2089 return RPH_ERROR;
2090
2091 LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
2092
2093 /* If OpenOCD thinks we're running but this hart is halted then it's time
2094 * to raise an event. */
2095 bool halted = riscv_is_halted(target);
2096 if (target->state != TARGET_HALTED && halted) {
2097 LOG_DEBUG(" triggered a halt");
2098 r->on_halt(target);
2099 return RPH_DISCOVERED_HALTED;
2100 } else if (target->state != TARGET_RUNNING && !halted) {
2101 LOG_DEBUG(" triggered running");
2102 target->state = TARGET_RUNNING;
2103 target->debug_reason = DBG_REASON_NOTHALTED;
2104 return RPH_DISCOVERED_RUNNING;
2105 }
2106
2107 return RPH_NO_CHANGE;
2108 }
2109
2110 static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
2111 {
2112 switch (halt_reason) {
2113 case RISCV_HALT_BREAKPOINT:
2114 target->debug_reason = DBG_REASON_BREAKPOINT;
2115 break;
2116 case RISCV_HALT_TRIGGER:
2117 target->debug_reason = DBG_REASON_WATCHPOINT;
2118 break;
2119 case RISCV_HALT_INTERRUPT:
2120 case RISCV_HALT_GROUP:
2121 target->debug_reason = DBG_REASON_DBGRQ;
2122 break;
2123 case RISCV_HALT_SINGLESTEP:
2124 target->debug_reason = DBG_REASON_SINGLESTEP;
2125 break;
2126 case RISCV_HALT_UNKNOWN:
2127 target->debug_reason = DBG_REASON_UNDEFINED;
2128 break;
2129 case RISCV_HALT_ERROR:
2130 return ERROR_FAIL;
2131 }
2132 LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
2133 return ERROR_OK;
2134 }
2135
2136 static int sample_memory(struct target *target)
2137 {
2138 RISCV_INFO(r);
2139
2140 if (!r->sample_buf.buf || !r->sample_config.enabled)
2141 return ERROR_OK;
2142
2143 LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
2144
2145 uint64_t start = timeval_ms();
2146 riscv_sample_buf_maybe_add_timestamp(target, true);
2147 int result = ERROR_OK;
2148 if (r->sample_memory) {
2149 result = r->sample_memory(target, &r->sample_buf, &r->sample_config,
2150 start + TARGET_DEFAULT_POLLING_INTERVAL);
2151 if (result != ERROR_NOT_IMPLEMENTED)
2152 goto exit;
2153 }
2154
2155 /* Default slow path. */
2156 while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
2157 for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
2158 if (r->sample_config.bucket[i].enabled &&
2159 r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
2160 assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
2161 r->sample_buf.buf[r->sample_buf.used] = i;
2162 result = riscv_read_phys_memory(
2163 target, r->sample_config.bucket[i].address,
2164 r->sample_config.bucket[i].size_bytes, 1,
2165 r->sample_buf.buf + r->sample_buf.used + 1);
2166 if (result == ERROR_OK)
2167 r->sample_buf.used += 1 + r->sample_config.bucket[i].size_bytes;
2168 else
2169 goto exit;
2170 }
2171 }
2172 }
2173
2174 exit:
2175 riscv_sample_buf_maybe_add_timestamp(target, false);
2176 if (result != ERROR_OK) {
2177 LOG_INFO("Turning off memory sampling because it failed.");
2178 r->sample_config.enabled = false;
2179 }
2180 return result;
2181 }
2182
2183 /*** OpenOCD Interface ***/
2184 int riscv_openocd_poll(struct target *target)
2185 {
2186 LOG_DEBUG("polling all harts");
2187 int halted_hart = -1;
2188
2189 if (target->smp) {
2190 unsigned should_remain_halted = 0;
2191 unsigned should_resume = 0;
2192 struct target_list *list;
2193 foreach_smp_target(list, target->smp_targets) {
2194 struct target *t = list->target;
2195 struct riscv_info *r = riscv_info(t);
2196 enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
2197 switch (out) {
2198 case RPH_NO_CHANGE:
2199 break;
2200 case RPH_DISCOVERED_RUNNING:
2201 t->state = TARGET_RUNNING;
2202 t->debug_reason = DBG_REASON_NOTHALTED;
2203 break;
2204 case RPH_DISCOVERED_HALTED:
2205 t->state = TARGET_HALTED;
2206 enum riscv_halt_reason halt_reason =
2207 riscv_halt_reason(t, r->current_hartid);
2208 if (set_debug_reason(t, halt_reason) != ERROR_OK)
2209 return ERROR_FAIL;
2210
2211 if (halt_reason == RISCV_HALT_BREAKPOINT) {
2212 int retval;
2213 switch (riscv_semihosting(t, &retval)) {
2214 case SEMIHOSTING_NONE:
2215 case SEMIHOSTING_WAITING:
2216 /* This hart should remain halted. */
2217 should_remain_halted++;
2218 break;
2219 case SEMIHOSTING_HANDLED:
2220 /* This hart should be resumed, along with any other
2221 * harts that halted due to haltgroups. */
2222 should_resume++;
2223 break;
2224 case SEMIHOSTING_ERROR:
2225 return retval;
2226 }
2227 } else if (halt_reason != RISCV_HALT_GROUP) {
2228 should_remain_halted++;
2229 }
2230 break;
2231
2232 case RPH_ERROR:
2233 return ERROR_FAIL;
2234 }
2235 }
2236
2237 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2238 should_remain_halted, should_resume);
2239 if (should_remain_halted && should_resume) {
2240 LOG_WARNING("%d harts should remain halted, and %d should resume.",
2241 should_remain_halted, should_resume);
2242 }
2243 if (should_remain_halted) {
2244 LOG_DEBUG("halt all");
2245 riscv_halt(target);
2246 } else if (should_resume) {
2247 LOG_DEBUG("resume all");
2248 riscv_resume(target, true, 0, 0, 0, false);
2249 }
2250
2251 /* Sample memory if any target is running. */
2252 foreach_smp_target(list, target->smp_targets) {
2253 struct target *t = list->target;
2254 if (t->state == TARGET_RUNNING) {
2255 sample_memory(target);
2256 break;
2257 }
2258 }
2259
2260 return ERROR_OK;
2261
2262 } else {
2263 enum riscv_poll_hart out = riscv_poll_hart(target,
2264 riscv_current_hartid(target));
2265 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
2266 if (target->state == TARGET_RUNNING)
2267 sample_memory(target);
2268 return ERROR_OK;
2269 } else if (out == RPH_ERROR) {
2270 return ERROR_FAIL;
2271 }
2272
2273 halted_hart = riscv_current_hartid(target);
2274 LOG_DEBUG(" hart %d halted", halted_hart);
2275
2276 enum riscv_halt_reason halt_reason = riscv_halt_reason(target, halted_hart);
2277 if (set_debug_reason(target, halt_reason) != ERROR_OK)
2278 return ERROR_FAIL;
2279 target->state = TARGET_HALTED;
2280 }
2281
2282 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
2283 int retval;
2284 switch (riscv_semihosting(target, &retval)) {
2285 case SEMIHOSTING_NONE:
2286 case SEMIHOSTING_WAITING:
2287 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2288 break;
2289 case SEMIHOSTING_HANDLED:
2290 if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK)
2291 return ERROR_FAIL;
2292 break;
2293 case SEMIHOSTING_ERROR:
2294 return retval;
2295 }
2296 } else {
2297 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2298 }
2299
2300 return ERROR_OK;
2301 }
2302
2303 int riscv_openocd_step(struct target *target, int current,
2304 target_addr_t address, int handle_breakpoints)
2305 {
2306 LOG_DEBUG("stepping rtos hart");
2307
2308 if (!current)
2309 riscv_set_register(target, GDB_REGNO_PC, address);
2310
2311 riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
2312 if (disable_triggers(target, trigger_state) != ERROR_OK)
2313 return ERROR_FAIL;
2314
2315 int out = riscv_step_rtos_hart(target);
2316 if (out != ERROR_OK) {
2317 LOG_ERROR("unable to step rtos hart");
2318 return out;
2319 }
2320
2321 register_cache_invalidate(target->reg_cache);
2322
2323 if (enable_triggers(target, trigger_state) != ERROR_OK)
2324 return ERROR_FAIL;
2325
2326 target->state = TARGET_RUNNING;
2327 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
2328 target->state = TARGET_HALTED;
2329 target->debug_reason = DBG_REASON_SINGLESTEP;
2330 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2331 return out;
2332 }
2333
2334 /* Command Handlers */
2335 COMMAND_HANDLER(riscv_set_command_timeout_sec)
2336 {
2337 if (CMD_ARGC != 1) {
2338 LOG_ERROR("Command takes exactly 1 parameter");
2339 return ERROR_COMMAND_SYNTAX_ERROR;
2340 }
2341 int timeout = atoi(CMD_ARGV[0]);
2342 if (timeout <= 0) {
2343 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2344 return ERROR_FAIL;
2345 }
2346
2347 riscv_command_timeout_sec = timeout;
2348
2349 return ERROR_OK;
2350 }
2351
2352 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
2353 {
2354 if (CMD_ARGC != 1) {
2355 LOG_ERROR("Command takes exactly 1 parameter");
2356 return ERROR_COMMAND_SYNTAX_ERROR;
2357 }
2358 int timeout = atoi(CMD_ARGV[0]);
2359 if (timeout <= 0) {
2360 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2361 return ERROR_FAIL;
2362 }
2363
2364 riscv_reset_timeout_sec = timeout;
2365 return ERROR_OK;
2366 }
2367
2368 COMMAND_HANDLER(riscv_set_mem_access)
2369 {
2370 struct target *target = get_current_target(CMD_CTX);
2371 RISCV_INFO(r);
2372 int progbuf_cnt = 0;
2373 int sysbus_cnt = 0;
2374 int abstract_cnt = 0;
2375
2376 if (CMD_ARGC < 1 || CMD_ARGC > RISCV_NUM_MEM_ACCESS_METHODS) {
2377 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS);
2378 return ERROR_COMMAND_SYNTAX_ERROR;
2379 }
2380
2381 /* Check argument validity */
2382 for (unsigned int i = 0; i < CMD_ARGC; i++) {
2383 if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
2384 progbuf_cnt++;
2385 } else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
2386 sysbus_cnt++;
2387 } else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
2388 abstract_cnt++;
2389 } else {
2390 LOG_ERROR("Unknown argument '%s'. "
2391 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
2392 return ERROR_COMMAND_SYNTAX_ERROR;
2393 }
2394 }
2395 if (progbuf_cnt > 1 || sysbus_cnt > 1 || abstract_cnt > 1) {
2396 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2397 return ERROR_COMMAND_SYNTAX_ERROR;
2398 }
2399
2400 /* Args are valid, store them */
2401 for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
2402 r->mem_access_methods[i] = RISCV_MEM_ACCESS_UNSPECIFIED;
2403 for (unsigned int i = 0; i < CMD_ARGC; i++) {
2404 if (strcmp("progbuf", CMD_ARGV[i]) == 0)
2405 r->mem_access_methods[i] = RISCV_MEM_ACCESS_PROGBUF;
2406 else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
2407 r->mem_access_methods[i] = RISCV_MEM_ACCESS_SYSBUS;
2408 else if (strcmp("abstract", CMD_ARGV[i]) == 0)
2409 r->mem_access_methods[i] = RISCV_MEM_ACCESS_ABSTRACT;
2410 }
2411
2412 /* Reset warning flags */
2413 r->mem_access_progbuf_warn = true;
2414 r->mem_access_sysbus_warn = true;
2415 r->mem_access_abstract_warn = true;
2416
2417 return ERROR_OK;
2418 }
2419
2420 COMMAND_HANDLER(riscv_set_enable_virtual)
2421 {
2422 if (CMD_ARGC != 1) {
2423 LOG_ERROR("Command takes exactly 1 parameter");
2424 return ERROR_COMMAND_SYNTAX_ERROR;
2425 }
2426 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virtual);
2427 return ERROR_OK;
2428 }
2429
2430 static int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
2431 {
2432 char *args = strdup(tcl_arg);
2433 if (!args)
2434 return ERROR_FAIL;
2435
2436 /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2437 char *arg = strtok(args, ",");
2438 while (arg) {
2439 unsigned low = 0;
2440 unsigned high = 0;
2441 char *name = NULL;
2442
2443 char *dash = strchr(arg, '-');
2444 char *equals = strchr(arg, '=');
2445 unsigned int pos;
2446
2447 if (!dash && !equals) {
2448 /* Expecting single register number. */
2449 if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2450 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2451 free(args);
2452 return ERROR_COMMAND_SYNTAX_ERROR;
2453 }
2454 } else if (dash && !equals) {
2455 /* Expecting register range - two numbers separated by a dash: ##-## */
2456 *dash = 0;
2457 dash++;
2458 if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2459 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2460 free(args);
2461 return ERROR_COMMAND_SYNTAX_ERROR;
2462 }
2463 if (sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash)) {
2464 LOG_ERROR("Failed to parse single register number from '%s'.", dash);
2465 free(args);
2466 return ERROR_COMMAND_SYNTAX_ERROR;
2467 }
2468 if (high < low) {
2469 LOG_ERROR("Incorrect range encountered [%u, %u].", low, high);
2470 free(args);
2471 return ERROR_FAIL;
2472 }
2473 } else if (!dash && equals) {
2474 /* Expecting single register number with textual name specified: ##=name */
2475 *equals = 0;
2476 equals++;
2477 if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2478 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2479 free(args);
2480 return ERROR_COMMAND_SYNTAX_ERROR;
2481 }
2482
2483 name = calloc(1, strlen(equals) + strlen(reg_type) + 2);
2484 if (!name) {
2485 LOG_ERROR("Failed to allocate register name.");
2486 free(args);
2487 return ERROR_FAIL;
2488 }
2489
2490 /* Register prefix: "csr_" or "custom_" */
2491 strcpy(name, reg_type);
2492 name[strlen(reg_type)] = '_';
2493
2494 if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals)) {
2495 LOG_ERROR("Failed to parse register name from '%s'.", equals);
2496 free(args);
2497 free(name);
2498 return ERROR_COMMAND_SYNTAX_ERROR;
2499 }
2500 } else {
2501 LOG_ERROR("Invalid argument '%s'.", arg);
2502 free(args);
2503 return ERROR_COMMAND_SYNTAX_ERROR;
2504 }
2505
2506 high = high > low ? high : low;
2507
2508 if (high > max_val) {
2509 LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type, high, max_val);
2510 free(name);
2511 free(args);
2512 return ERROR_FAIL;
2513 }
2514
2515 /* Check for overlap, name uniqueness. */
2516 range_list_t *entry;
2517 list_for_each_entry(entry, ranges, list) {
2518 if ((entry->low <= high) && (low <= entry->high)) {
2519 if (low == high)
2520 LOG_WARNING("Duplicate %s register number - "
2521 "Register %u has already been exposed previously", reg_type, low);
2522 else
2523 LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2524 "with already exposed register/range at %u.", low, entry->low);
2525 }
2526
2527 if (entry->name && name && (strcasecmp(entry->name, name) == 0)) {
2528 LOG_ERROR("Duplicate register name \"%s\" found.", name);
2529 free(name);
2530 free(args);
2531 return ERROR_FAIL;
2532 }
2533 }
2534
2535 range_list_t *range = calloc(1, sizeof(range_list_t));
2536 if (!range) {
2537 LOG_ERROR("Failed to allocate range list.");
2538 free(name);
2539 free(args);
2540 return ERROR_FAIL;
2541 }
2542
2543 range->low = low;
2544 range->high = high;
2545 range->name = name;
2546 list_add(&range->list, ranges);
2547
2548 arg = strtok(NULL, ",");
2549 }
2550
2551 free(args);
2552 return ERROR_OK;
2553 }
2554
2555 COMMAND_HANDLER(riscv_set_expose_csrs)
2556 {
2557 if (CMD_ARGC == 0) {
2558 LOG_ERROR("Command expects parameters");
2559 return ERROR_COMMAND_SYNTAX_ERROR;
2560 }
2561
2562 struct target *target = get_current_target(CMD_CTX);
2563 RISCV_INFO(info);
2564 int ret = ERROR_OK;
2565
2566 for (unsigned int i = 0; i < CMD_ARGC; i++) {
2567 ret = parse_ranges(&info->expose_csr, CMD_ARGV[i], "csr", 0xfff);
2568 if (ret != ERROR_OK)
2569 break;
2570 }
2571
2572 return ret;
2573 }
2574
2575 COMMAND_HANDLER(riscv_set_expose_custom)
2576 {
2577 if (CMD_ARGC == 0) {
2578 LOG_ERROR("Command expects parameters");
2579 return ERROR_COMMAND_SYNTAX_ERROR;
2580 }
2581
2582 struct target *target = get_current_target(CMD_CTX);
2583 RISCV_INFO(info);
2584 int ret = ERROR_OK;
2585
2586 for (unsigned int i = 0; i < CMD_ARGC; i++) {
2587 ret = parse_ranges(&info->expose_custom, CMD_ARGV[i], "custom", 0x3fff);
2588 if (ret != ERROR_OK)
2589 break;
2590 }
2591
2592 return ret;
2593 }
2594
2595 COMMAND_HANDLER(riscv_authdata_read)
2596 {
2597 unsigned int index = 0;
2598 if (CMD_ARGC == 0) {
2599 /* nop */
2600 } else if (CMD_ARGC == 1) {
2601 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2602 } else {
2603 LOG_ERROR("Command takes at most one parameter");
2604 return ERROR_COMMAND_SYNTAX_ERROR;
2605 }
2606
2607 struct target *target = get_current_target(CMD_CTX);
2608 if (!target) {
2609 LOG_ERROR("target is NULL!");
2610 return ERROR_FAIL;
2611 }
2612
2613 RISCV_INFO(r);
2614 if (!r) {
2615 LOG_ERROR("riscv_info is NULL!");
2616 return ERROR_FAIL;
2617 }
2618
2619 if (r->authdata_read) {
2620 uint32_t value;
2621 if (r->authdata_read(target, &value, index) != ERROR_OK)
2622 return ERROR_FAIL;
2623 command_print_sameline(CMD, "0x%08" PRIx32, value);
2624 return ERROR_OK;
2625 } else {
2626 LOG_ERROR("authdata_read is not implemented for this target.");
2627 return ERROR_FAIL;
2628 }
2629 }
2630
2631 COMMAND_HANDLER(riscv_authdata_write)
2632 {
2633 uint32_t value;
2634 unsigned int index = 0;
2635
2636 if (CMD_ARGC == 0 || CMD_ARGC > 2)
2637 return ERROR_COMMAND_SYNTAX_ERROR;
2638
2639 if (CMD_ARGC == 1) {
2640 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
2641 } else {
2642 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2643 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2644 }
2645
2646 struct target *target = get_current_target(CMD_CTX);
2647 RISCV_INFO(r);
2648
2649 if (!r->authdata_write) {
2650 LOG_ERROR("authdata_write is not implemented for this target.");
2651 return ERROR_FAIL;
2652 }
2653
2654 return r->authdata_write(target, value, index);
2655 }
2656
2657 COMMAND_HANDLER(riscv_dmi_read)
2658 {
2659 if (CMD_ARGC != 1) {
2660 LOG_ERROR("Command takes 1 parameter");
2661 return ERROR_COMMAND_SYNTAX_ERROR;
2662 }
2663
2664 struct target *target = get_current_target(CMD_CTX);
2665 if (!target) {
2666 LOG_ERROR("target is NULL!");
2667 return ERROR_FAIL;
2668 }
2669
2670 RISCV_INFO(r);
2671 if (!r) {
2672 LOG_ERROR("riscv_info is NULL!");
2673 return ERROR_FAIL;
2674 }
2675
2676 if (r->dmi_read) {
2677 uint32_t address, value;
2678 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2679 if (r->dmi_read(target, &value, address) != ERROR_OK)
2680 return ERROR_FAIL;
2681 command_print(CMD, "0x%" PRIx32, value);
2682 return ERROR_OK;
2683 } else {
2684 LOG_ERROR("dmi_read is not implemented for this target.");
2685 return ERROR_FAIL;
2686 }
2687 }
2688
2689
2690 COMMAND_HANDLER(riscv_dmi_write)
2691 {
2692 if (CMD_ARGC != 2) {
2693 LOG_ERROR("Command takes exactly 2 arguments");
2694 return ERROR_COMMAND_SYNTAX_ERROR;
2695 }
2696
2697 struct target *target = get_current_target(CMD_CTX);
2698 RISCV_INFO(r);
2699
2700 uint32_t address, value;
2701 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2702 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2703
2704 if (r->dmi_write) {
2705 return r->dmi_write(target, address, value);
2706 } else {
2707 LOG_ERROR("dmi_write is not implemented for this target.");
2708 return ERROR_FAIL;
2709 }
2710 }
2711
2712 COMMAND_HANDLER(riscv_reset_delays)
2713 {
2714 int wait = 0;
2715
2716 if (CMD_ARGC > 1) {
2717 LOG_ERROR("Command takes at most one argument");
2718 return ERROR_COMMAND_SYNTAX_ERROR;
2719 }
2720
2721 if (CMD_ARGC == 1)
2722 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
2723
2724 struct target *target = get_current_target(CMD_CTX);
2725 RISCV_INFO(r);
2726 r->reset_delays_wait = wait;
2727 return ERROR_OK;
2728 }
2729
2730 COMMAND_HANDLER(riscv_set_ir)
2731 {
2732 if (CMD_ARGC != 2) {
2733 LOG_ERROR("Command takes exactly 2 arguments");
2734 return ERROR_COMMAND_SYNTAX_ERROR;
2735 }
2736
2737 uint32_t value;
2738 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2739
2740 if (!strcmp(CMD_ARGV[0], "idcode"))
2741 buf_set_u32(ir_idcode, 0, 32, value);
2742 else if (!strcmp(CMD_ARGV[0], "dtmcs"))
2743 buf_set_u32(ir_dtmcontrol, 0, 32, value);
2744 else if (!strcmp(CMD_ARGV[0], "dmi"))
2745 buf_set_u32(ir_dbus, 0, 32, value);
2746 else
2747 return ERROR_FAIL;
2748
2749 return ERROR_OK;
2750 }
2751
2752 COMMAND_HANDLER(riscv_resume_order)
2753 {
2754 if (CMD_ARGC > 1) {
2755 LOG_ERROR("Command takes at most one argument");
2756 return ERROR_COMMAND_SYNTAX_ERROR;
2757 }
2758
2759 if (!strcmp(CMD_ARGV[0], "normal")) {
2760 resume_order = RO_NORMAL;
2761 } else if (!strcmp(CMD_ARGV[0], "reversed")) {
2762 resume_order = RO_REVERSED;
2763 } else {
2764 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV[0]);
2765 return ERROR_FAIL;
2766 }
2767
2768 return ERROR_OK;
2769 }
2770
2771 COMMAND_HANDLER(riscv_use_bscan_tunnel)
2772 {
2773 int irwidth = 0;
2774 int tunnel_type = BSCAN_TUNNEL_NESTED_TAP;
2775
2776 if (CMD_ARGC > 2) {
2777 LOG_ERROR("Command takes at most two arguments");
2778 return ERROR_COMMAND_SYNTAX_ERROR;
2779 } else if (CMD_ARGC == 1) {
2780 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2781 } else if (CMD_ARGC == 2) {
2782 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2783 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tunnel_type);
2784 }
2785 if (tunnel_type == BSCAN_TUNNEL_NESTED_TAP)
2786 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2787 else if (tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
2788 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2789 else
2790 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2791
2792 bscan_tunnel_type = tunnel_type;
2793 bscan_tunnel_ir_width = irwidth;
2794 return ERROR_OK;
2795 }
2796
2797 COMMAND_HANDLER(riscv_set_enable_virt2phys)
2798 {
2799 if (CMD_ARGC != 1) {
2800 LOG_ERROR("Command takes exactly 1 parameter");
2801 return ERROR_COMMAND_SYNTAX_ERROR;
2802 }
2803 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virt2phys);
2804 return ERROR_OK;
2805 }
2806
2807 COMMAND_HANDLER(riscv_set_ebreakm)
2808 {
2809 if (CMD_ARGC != 1) {
2810 LOG_ERROR("Command takes exactly 1 parameter");
2811 return ERROR_COMMAND_SYNTAX_ERROR;
2812 }
2813 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreakm);
2814 return ERROR_OK;
2815 }
2816
2817 COMMAND_HANDLER(riscv_set_ebreaks)
2818 {
2819 if (CMD_ARGC != 1) {
2820 LOG_ERROR("Command takes exactly 1 parameter");
2821 return ERROR_COMMAND_SYNTAX_ERROR;
2822 }
2823 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaks);
2824 return ERROR_OK;
2825 }
2826
2827 COMMAND_HANDLER(riscv_set_ebreaku)
2828 {
2829 if (CMD_ARGC != 1) {
2830 LOG_ERROR("Command takes exactly 1 parameter");
2831 return ERROR_COMMAND_SYNTAX_ERROR;
2832 }
2833 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaku);
2834 return ERROR_OK;
2835 }
2836
2837 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
2838 unsigned int value)
2839 {
2840 char full_key[80];
2841 snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
2842 command_print(CMD, "%-21s %3d", full_key, value);
2843 return 0;
2844 }
2845
2846 COMMAND_HANDLER(handle_info)
2847 {
2848 struct target *target = get_current_target(CMD_CTX);
2849 RISCV_INFO(r);
2850
2851 /* This output format can be fed directly into TCL's "array set". */
2852
2853 riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
2854 riscv_enumerate_triggers(target);
2855 riscv_print_info_line(CMD, "hart", "trigger_count",
2856 r->trigger_count);
2857
2858 if (r->print_info)
2859 return CALL_COMMAND_HANDLER(r->print_info, target);
2860
2861 return 0;
2862 }
2863
2864 static const struct command_registration riscv_exec_command_handlers[] = {
2865 {
2866 .name = "info",
2867 .handler = handle_info,
2868 .mode = COMMAND_EXEC,
2869 .usage = "",
2870 .help = "Displays some information OpenOCD detected about the target."
2871 },
2872 {
2873 .name = "set_command_timeout_sec",
2874 .handler = riscv_set_command_timeout_sec,
2875 .mode = COMMAND_ANY,
2876 .usage = "[sec]",
2877 .help = "Set the wall-clock timeout (in seconds) for individual commands"
2878 },
2879 {
2880 .name = "set_reset_timeout_sec",
2881 .handler = riscv_set_reset_timeout_sec,
2882 .mode = COMMAND_ANY,
2883 .usage = "[sec]",
2884 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
2885 },
2886 {
2887 .name = "set_mem_access",
2888 .handler = riscv_set_mem_access,
2889 .mode = COMMAND_ANY,
2890 .usage = "method1 [method2] [method3]",
2891 .help = "Set which memory access methods shall be used and in which order "
2892 "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2893 },
2894 {
2895 .name = "set_enable_virtual",
2896 .handler = riscv_set_enable_virtual,
2897 .mode = COMMAND_ANY,
2898 .usage = "on|off",
2899 .help = "When on, memory accesses are performed on physical or virtual "
2900 "memory depending on the current system configuration. "
2901 "When off (default), all memory accessses are performed on physical memory."
2902 },
2903 {
2904 .name = "expose_csrs",
2905 .handler = riscv_set_expose_csrs,
2906 .mode = COMMAND_CONFIG,
2907 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2908 .help = "Configure a list of inclusive ranges for CSRs to expose in "
2909 "addition to the standard ones. This must be executed before "
2910 "`init`."
2911 },
2912 {
2913 .name = "expose_custom",
2914 .handler = riscv_set_expose_custom,
2915 .mode = COMMAND_CONFIG,
2916 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2917 .help = "Configure a list of inclusive ranges for custom registers to "
2918 "expose. custom0 is accessed as abstract register number 0xc000, "
2919 "etc. This must be executed before `init`."
2920 },
2921 {
2922 .name = "authdata_read",
2923 .handler = riscv_authdata_read,
2924 .usage = "[index]",
2925 .mode = COMMAND_ANY,
2926 .help = "Return the 32-bit value read from authdata or authdata0 "
2927 "(index=0), or authdata1 (index=1)."
2928 },
2929 {
2930 .name = "authdata_write",
2931 .handler = riscv_authdata_write,
2932 .mode = COMMAND_ANY,
2933 .usage = "[index] value",
2934 .help = "Write the 32-bit value to authdata or authdata0 (index=0), "
2935 "or authdata1 (index=1)."
2936 },
2937 {
2938 .name = "dmi_read",
2939 .handler = riscv_dmi_read,
2940 .mode = COMMAND_ANY,
2941 .usage = "address",
2942 .help = "Perform a 32-bit DMI read at address, returning the value."
2943 },
2944 {
2945 .name = "dmi_write",
2946 .handler = riscv_dmi_write,
2947 .mode = COMMAND_ANY,
2948 .usage = "address value",
2949 .help = "Perform a 32-bit DMI write of value at address."
2950 },
2951 {
2952 .name = "reset_delays",
2953 .handler = riscv_reset_delays,
2954 .mode = COMMAND_ANY,
2955 .usage = "[wait]",
2956 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
2957 "between scans to avoid encountering the target being busy. This "
2958 "command resets those learned values after `wait` scans. It's only "
2959 "useful for testing OpenOCD itself."
2960 },
2961 {
2962 .name = "resume_order",
2963 .handler = riscv_resume_order,
2964 .mode = COMMAND_ANY,
2965 .usage = "normal|reversed",
2966 .help = "Choose the order that harts are resumed in when `hasel` is not "
2967 "supported. Normal order is from lowest hart index to highest. "
2968 "Reversed order is from highest hart index to lowest."
2969 },
2970 {
2971 .name = "set_ir",
2972 .handler = riscv_set_ir,
2973 .mode = COMMAND_ANY,
2974 .usage = "[idcode|dtmcs|dmi] value",
2975 .help = "Set IR value for specified JTAG register."
2976 },
2977 {
2978 .name = "use_bscan_tunnel",
2979 .handler = riscv_use_bscan_tunnel,
2980 .mode = COMMAND_ANY,
2981 .usage = "value [type]",
2982 .help = "Enable or disable use of a BSCAN tunnel to reach DM. Supply "
2983 "the width of the DM transport TAP's instruction register to "
2984 "enable. Supply a value of 0 to disable. Pass A second argument "
2985 "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
2986 "1: DATA_REGISTER}"
2987 },
2988 {
2989 .name = "set_enable_virt2phys",
2990 .handler = riscv_set_enable_virt2phys,
2991 .mode = COMMAND_ANY,
2992 .usage = "on|off",
2993 .help = "When on (default), enable translation from virtual address to "
2994 "physical address."
2995 },
2996 {
2997 .name = "set_ebreakm",
2998 .handler = riscv_set_ebreakm,
2999 .mode = COMMAND_ANY,
3000 .usage = "on|off",
3001 .help = "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3002 "don't trap to OpenOCD. Defaults to on."
3003 },
3004 {
3005 .name = "set_ebreaks",
3006 .handler = riscv_set_ebreaks,
3007 .mode = COMMAND_ANY,
3008 .usage = "on|off",
3009 .help = "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3010 "don't trap to OpenOCD. Defaults to on."
3011 },
3012 {
3013 .name = "set_ebreaku",
3014 .handler = riscv_set_ebreaku,
3015 .mode = COMMAND_ANY,
3016 .usage = "on|off",
3017 .help = "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3018 "don't trap to OpenOCD. Defaults to on."
3019 },
3020 COMMAND_REGISTRATION_DONE
3021 };
3022
3023 /*
3024 * To be noted that RISC-V targets use the same semihosting commands as
3025 * ARM targets.
3026 *
3027 * The main reason is compatibility with existing tools. For example the
3028 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3029 * configure semihosting, which generate commands like `arm semihosting
3030 * enable`.
3031 * A secondary reason is the fact that the protocol used is exactly the
3032 * one specified by ARM. If RISC-V will ever define its own semihosting
3033 * protocol, then a command like `riscv semihosting enable` will make
3034 * sense, but for now all semihosting commands are prefixed with `arm`.
3035 */
3036
3037 static const struct command_registration riscv_command_handlers[] = {
3038 {
3039 .name = "riscv",
3040 .mode = COMMAND_ANY,
3041 .help = "RISC-V Command Group",
3042 .usage = "",
3043 .chain = riscv_exec_command_handlers
3044 },
3045 {
3046 .name = "arm",
3047 .mode = COMMAND_ANY,
3048 .help = "ARM Command Group",
3049 .usage = "",
3050 .chain = semihosting_common_handlers
3051 },
3052 COMMAND_REGISTRATION_DONE
3053 };
3054
3055 static unsigned riscv_xlen_nonconst(struct target *target)
3056 {
3057 return riscv_xlen(target);
3058 }
3059
3060 static unsigned int riscv_data_bits(struct target *target)
3061 {
3062 RISCV_INFO(r);
3063 if (r->data_bits)
3064 return r->data_bits(target);
3065 return riscv_xlen(target);
3066 }
3067
3068 struct target_type riscv_target = {
3069 .name = "riscv",
3070
3071 .target_create = riscv_create_target,
3072 .init_target = riscv_init_target,
3073 .deinit_target = riscv_deinit_target,
3074 .examine = riscv_examine,
3075
3076 /* poll current target status */
3077 .poll = old_or_new_riscv_poll,
3078
3079 .halt = riscv_halt,
3080 .resume = riscv_target_resume,
3081 .step = old_or_new_riscv_step,
3082
3083 .assert_reset = riscv_assert_reset,
3084 .deassert_reset = riscv_deassert_reset,
3085
3086 .read_memory = riscv_read_memory,
3087 .write_memory = riscv_write_memory,
3088 .read_phys_memory = riscv_read_phys_memory,
3089 .write_phys_memory = riscv_write_phys_memory,
3090
3091 .checksum_memory = riscv_checksum_memory,
3092
3093 .mmu = riscv_mmu,
3094 .virt2phys = riscv_virt2phys,
3095
3096 .get_gdb_arch = riscv_get_gdb_arch,
3097 .get_gdb_reg_list = riscv_get_gdb_reg_list,
3098 .get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
3099
3100 .add_breakpoint = riscv_add_breakpoint,
3101 .remove_breakpoint = riscv_remove_breakpoint,
3102
3103 .add_watchpoint = riscv_add_watchpoint,
3104 .remove_watchpoint = riscv_remove_watchpoint,
3105 .hit_watchpoint = riscv_hit_watchpoint,
3106
3107 .arch_state = riscv_arch_state,
3108
3109 .run_algorithm = riscv_run_algorithm,
3110
3111 .commands = riscv_command_handlers,
3112
3113 .address_bits = riscv_xlen_nonconst,
3114 .data_bits = riscv_data_bits
3115 };
3116
3117 /*** RISC-V Interface ***/
3118
3119 /* Initializes the shared RISC-V structure. */
3120 static void riscv_info_init(struct target *target, struct riscv_info *r)
3121 {
3122 memset(r, 0, sizeof(*r));
3123
3124 r->common_magic = RISCV_COMMON_MAGIC;
3125
3126 r->dtm_version = 1;
3127 r->current_hartid = target->coreid;
3128 r->version_specific = NULL;
3129
3130 memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
3131
3132 r->xlen = -1;
3133
3134 r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
3135 r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
3136 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
3137
3138 r->mem_access_progbuf_warn = true;
3139 r->mem_access_sysbus_warn = true;
3140 r->mem_access_abstract_warn = true;
3141
3142 INIT_LIST_HEAD(&r->expose_csr);
3143 INIT_LIST_HEAD(&r->expose_custom);
3144 }
3145
3146 static int riscv_resume_go_all_harts(struct target *target)
3147 {
3148 RISCV_INFO(r);
3149
3150 LOG_DEBUG("[%s] resuming hart", target_name(target));
3151 if (riscv_select_current_hart(target) != ERROR_OK)
3152 return ERROR_FAIL;
3153 if (riscv_is_halted(target)) {
3154 if (r->resume_go(target) != ERROR_OK)
3155 return ERROR_FAIL;
3156 } else {
3157 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3158 target_name(target));
3159 }
3160
3161 riscv_invalidate_register_cache(target);
3162 return ERROR_OK;
3163 }
3164
3165 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
3166 * then the only hart. */
3167 static int riscv_step_rtos_hart(struct target *target)
3168 {
3169 RISCV_INFO(r);
3170 if (riscv_select_current_hart(target) != ERROR_OK)
3171 return ERROR_FAIL;
3172 LOG_DEBUG("[%s] stepping", target_name(target));
3173
3174 if (!riscv_is_halted(target)) {
3175 LOG_ERROR("Hart isn't halted before single step!");
3176 return ERROR_FAIL;
3177 }
3178 riscv_invalidate_register_cache(target);
3179 r->on_step(target);
3180 if (r->step_current_hart(target) != ERROR_OK)
3181 return ERROR_FAIL;
3182 riscv_invalidate_register_cache(target);
3183 r->on_halt(target);
3184 if (!riscv_is_halted(target)) {
3185 LOG_ERROR("Hart was not halted after single step!");
3186 return ERROR_FAIL;
3187 }
3188 return ERROR_OK;
3189 }
3190
3191 bool riscv_supports_extension(struct target *target, char letter)
3192 {
3193 RISCV_INFO(r);
3194 unsigned num;
3195 if (letter >= 'a' && letter <= 'z')
3196 num = letter - 'a';
3197 else if (letter >= 'A' && letter <= 'Z')
3198 num = letter - 'A';
3199 else
3200 return false;
3201 return r->misa & BIT(num);
3202 }
3203
3204 unsigned riscv_xlen(const struct target *target)
3205 {
3206 RISCV_INFO(r);
3207 return r->xlen;
3208 }
3209
3210 int riscv_set_current_hartid(struct target *target, int hartid)
3211 {
3212 RISCV_INFO(r);
3213 if (!r->select_current_hart)
3214 return ERROR_OK;
3215
3216 int previous_hartid = riscv_current_hartid(target);
3217 r->current_hartid = hartid;
3218 LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
3219 if (r->select_current_hart(target) != ERROR_OK)
3220 return ERROR_FAIL;
3221
3222 return ERROR_OK;
3223 }
3224
3225 /* Invalidates the register cache. */
3226 static void riscv_invalidate_register_cache(struct target *target)
3227 {
3228 LOG_DEBUG("[%d]", target->coreid);
3229 register_cache_invalidate(target->reg_cache);
3230 for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
3231 struct reg *reg = &target->reg_cache->reg_list[i];
3232 reg->valid = false;
3233 }
3234 }
3235
3236 int riscv_current_hartid(const struct target *target)
3237 {
3238 RISCV_INFO(r);
3239 return r->current_hartid;
3240 }
3241
3242 int riscv_count_harts(struct target *target)
3243 {
3244 if (!target)
3245 return 1;
3246 RISCV_INFO(r);
3247 if (!r || !r->hart_count)
3248 return 1;
3249 return r->hart_count(target);
3250 }
3251
3252 /**
3253 * If write is true:
3254 * return true iff we are guaranteed that the register will contain exactly
3255 * the value we just wrote when it's read.
3256 * If write is false:
3257 * return true iff we are guaranteed that the register will read the same
3258 * value in the future as the value we just read.
3259 */
3260 static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
3261 {
3262 /* GPRs, FPRs, vector registers are just normal data stores. */
3263 if (regno <= GDB_REGNO_XPR31 ||
3264 (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
3265 (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
3266 return true;
3267
3268 /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3269 * CSRs. */
3270 switch (regno) {
3271 case GDB_REGNO_DPC:
3272 return true;
3273
3274 case GDB_REGNO_VSTART:
3275 case GDB_REGNO_VXSAT:
3276 case GDB_REGNO_VXRM:
3277 case GDB_REGNO_VLENB:
3278 case GDB_REGNO_VL:
3279 case GDB_REGNO_VTYPE:
3280 case GDB_REGNO_MISA:
3281 case GDB_REGNO_DCSR:
3282 case GDB_REGNO_DSCRATCH0:
3283 case GDB_REGNO_MSTATUS:
3284 case GDB_REGNO_MEPC:
3285 case GDB_REGNO_MCAUSE:
3286 case GDB_REGNO_SATP:
3287 /*
3288 * WARL registers might not contain the value we just wrote, but
3289 * these ones won't spontaneously change their value either. *
3290 */
3291 return !write;
3292
3293 case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
3294 case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */
3295 case GDB_REGNO_TDATA2: /* Changse value when tselect is changed. */
3296 default:
3297 return false;
3298 }
3299 }
3300
3301 /**
3302 * This function is called when the debug user wants to change the value of a
3303 * register. The new value may be cached, and may not be written until the hart
3304 * is resumed. */
3305 int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t value)
3306 {
3307 RISCV_INFO(r);
3308 LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
3309 assert(r->set_register);
3310
3311 keep_alive();
3312
3313 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3314 if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
3315 riscv_supports_extension(target, 'E'))
3316 return ERROR_OK;
3317
3318 struct reg *reg = &target->reg_cache->reg_list[regid];
3319 buf_set_u64(reg->value, 0, reg->size, value);
3320
3321 int result = r->set_register(target, regid, value);
3322 if (result == ERROR_OK)
3323 reg->valid = gdb_regno_cacheable(regid, true);
3324 else
3325 reg->valid = false;
3326 LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
3327 target_name(target), value, reg->name, reg->valid);
3328 return result;
3329 }
3330
3331 int riscv_get_register(struct target *target, riscv_reg_t *value,
3332 enum gdb_regno regid)
3333 {
3334 RISCV_INFO(r);
3335
3336 keep_alive();
3337
3338 struct reg *reg = &target->reg_cache->reg_list[regid];
3339 if (!reg->exist) {
3340 LOG_DEBUG("[%s] %s does not exist.",
3341 target_name(target), gdb_regno_name(regid));
3342 return ERROR_FAIL;
3343 }
3344
3345 if (reg && reg->valid) {
3346 *value = buf_get_u64(reg->value, 0, reg->size);
3347 LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
3348 gdb_regno_name(regid), *value);
3349 return ERROR_OK;
3350 }
3351
3352 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3353 if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
3354 riscv_supports_extension(target, 'E')) {
3355 *value = 0;
3356 return ERROR_OK;
3357 }
3358
3359 int result = r->get_register(target, value, regid);
3360
3361 if (result == ERROR_OK)
3362 reg->valid = gdb_regno_cacheable(regid, false);
3363
3364 LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
3365 gdb_regno_name(regid), *value);
3366 return result;
3367 }
3368
3369 bool riscv_is_halted(struct target *target)
3370 {
3371 RISCV_INFO(r);
3372 assert(r->is_halted);
3373 return r->is_halted(target);
3374 }
3375
3376 static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
3377 {
3378 RISCV_INFO(r);
3379 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
3380 return RISCV_HALT_ERROR;
3381 if (!riscv_is_halted(target)) {
3382 LOG_ERROR("Hart is not halted!");
3383 return RISCV_HALT_UNKNOWN;
3384 }
3385 return r->halt_reason(target);
3386 }
3387
3388 size_t riscv_debug_buffer_size(struct target *target)
3389 {
3390 RISCV_INFO(r);
3391 return r->debug_buffer_size;
3392 }
3393
3394 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
3395 {
3396 RISCV_INFO(r);
3397 r->write_debug_buffer(target, index, insn);
3398 return ERROR_OK;
3399 }
3400
3401 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
3402 {
3403 RISCV_INFO(r);
3404 return r->read_debug_buffer(target, index);
3405 }
3406
3407 int riscv_execute_debug_buffer(struct target *target)
3408 {
3409 RISCV_INFO(r);
3410 return r->execute_debug_buffer(target);
3411 }
3412
3413 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
3414 {
3415 RISCV_INFO(r);
3416 r->fill_dmi_write_u64(target, buf, a, d);
3417 }
3418
3419 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
3420 {
3421 RISCV_INFO(r);
3422 r->fill_dmi_read_u64(target, buf, a);
3423 }
3424
3425 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
3426 {
3427 RISCV_INFO(r);
3428 r->fill_dmi_nop_u64(target, buf);
3429 }
3430
3431 int riscv_dmi_write_u64_bits(struct target *target)
3432 {
3433 RISCV_INFO(r);
3434 return r->dmi_write_u64_bits(target);
3435 }
3436
3437 /**
3438 * Count triggers, and initialize trigger_count for each hart.
3439 * trigger_count is initialized even if this function fails to discover
3440 * something.
3441 * Disable any hardware triggers that have dmode set. We can't have set them
3442 * ourselves. Maybe they're left over from some killed debug session.
3443 * */
3444 int riscv_enumerate_triggers(struct target *target)
3445 {
3446 RISCV_INFO(r);
3447
3448 if (r->triggers_enumerated)
3449 return ERROR_OK;
3450
3451 r->triggers_enumerated = true; /* At the very least we tried. */
3452
3453 riscv_reg_t tselect;
3454 int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
3455 /* If tselect is not readable, the trigger module is likely not
3456 * implemented. There are no triggers to enumerate then and no error
3457 * should be thrown. */
3458 if (result != ERROR_OK) {
3459 LOG_DEBUG("[%s] Cannot access tselect register. "
3460 "Assuming that triggers are not implemented.", target_name(target));
3461 r->trigger_count = 0;
3462 return ERROR_OK;
3463 }
3464
3465 for (unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
3466 r->trigger_count = t;
3467
3468 /* If we can't write tselect, then this hart does not support triggers. */
3469 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
3470 break;
3471 uint64_t tselect_rb;
3472 result = riscv_get_register(target, &tselect_rb, GDB_REGNO_TSELECT);
3473 if (result != ERROR_OK)
3474 return result;
3475 /* Mask off the top bit, which is used as tdrmode in old
3476 * implementations. */
3477 tselect_rb &= ~(1ULL << (riscv_xlen(target) - 1));
3478 if (tselect_rb != t)
3479 break;
3480 uint64_t tdata1;
3481 result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
3482 if (result != ERROR_OK)
3483 return result;
3484
3485 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
3486 if (type == 0)
3487 break;
3488 switch (type) {
3489 case 1:
3490 /* On these older cores we don't support software using
3491 * triggers. */
3492 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3493 break;
3494 case 2:
3495 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3496 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3497 break;
3498 case 6:
3499 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3500 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3501 break;
3502 }
3503 }
3504
3505 riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
3506
3507 LOG_INFO("[%s] Found %d triggers", target_name(target), r->trigger_count);
3508
3509 return ERROR_OK;
3510 }
3511
3512 const char *gdb_regno_name(enum gdb_regno regno)
3513 {
3514 static char buf[32];
3515
3516 switch (regno) {
3517 case GDB_REGNO_ZERO:
3518 return "zero";
3519 case GDB_REGNO_RA:
3520 return "ra";
3521 case GDB_REGNO_SP:
3522 return "sp";
3523 case GDB_REGNO_GP:
3524 return "gp";
3525 case GDB_REGNO_TP:
3526 return "tp";
3527 case GDB_REGNO_T0:
3528 return "t0";
3529 case GDB_REGNO_T1:
3530 return "t1";
3531 case GDB_REGNO_T2:
3532 return "t2";
3533 case GDB_REGNO_S0:
3534 return "s0";
3535 case GDB_REGNO_S1:
3536 return "s1";
3537 case GDB_REGNO_A0:
3538 return "a0";
3539 case GDB_REGNO_A1:
3540 return "a1";
3541 case GDB_REGNO_A2:
3542 return "a2";
3543 case GDB_REGNO_A3:
3544 return "a3";
3545 case GDB_REGNO_A4:
3546 return "a4";
3547 case GDB_REGNO_A5:
3548 return "a5";
3549 case GDB_REGNO_A6:
3550 return "a6";
3551 case GDB_REGNO_A7:
3552 return "a7";
3553 case GDB_REGNO_S2:
3554 return "s2";
3555 case GDB_REGNO_S3:
3556 return "s3";
3557 case GDB_REGNO_S4:
3558 return "s4";
3559 case GDB_REGNO_S5:
3560 return "s5";
3561 case GDB_REGNO_S6:
3562 return "s6";
3563 case GDB_REGNO_S7:
3564 return "s7";
3565 case GDB_REGNO_S8:
3566 return "s8";
3567 case GDB_REGNO_S9:
3568 return "s9";
3569 case GDB_REGNO_S10:
3570 return "s10";
3571 case GDB_REGNO_S11:
3572 return "s11";
3573 case GDB_REGNO_T3:
3574 return "t3";
3575 case GDB_REGNO_T4:
3576 return "t4";
3577 case GDB_REGNO_T5:
3578 return "t5";
3579 case GDB_REGNO_T6:
3580 return "t6";
3581 case GDB_REGNO_PC:
3582 return "pc";
3583 case GDB_REGNO_FPR0:
3584 return "fpr0";
3585 case GDB_REGNO_FPR31:
3586 return "fpr31";
3587 case GDB_REGNO_CSR0:
3588 return "csr0";
3589 case GDB_REGNO_TSELECT:
3590 return "tselect";
3591 case GDB_REGNO_TDATA1:
3592 return "tdata1";
3593 case GDB_REGNO_TDATA2:
3594 return "tdata2";
3595 case GDB_REGNO_MISA:
3596 return "misa";
3597 case GDB_REGNO_DPC:
3598 return "dpc";
3599 case GDB_REGNO_DCSR:
3600 return "dcsr";
3601 case GDB_REGNO_DSCRATCH0:
3602 return "dscratch0";
3603 case GDB_REGNO_MSTATUS:
3604 return "mstatus";
3605 case GDB_REGNO_MEPC:
3606 return "mepc";
3607 case GDB_REGNO_MCAUSE:
3608 return "mcause";
3609 case GDB_REGNO_PRIV:
3610 return "priv";
3611 case GDB_REGNO_SATP:
3612 return "satp";
3613 case GDB_REGNO_VTYPE:
3614 return "vtype";
3615 case GDB_REGNO_VL:
3616 return "vl";
3617 case GDB_REGNO_V0:
3618 return "v0";
3619 case GDB_REGNO_V1:
3620 return "v1";
3621 case GDB_REGNO_V2:
3622 return "v2";
3623 case GDB_REGNO_V3:
3624 return "v3";
3625 case GDB_REGNO_V4:
3626 return "v4";
3627 case GDB_REGNO_V5:
3628 return "v5";
3629 case GDB_REGNO_V6:
3630 return "v6";
3631 case GDB_REGNO_V7:
3632 return "v7";
3633 case GDB_REGNO_V8:
3634 return "v8";
3635 case GDB_REGNO_V9:
3636 return "v9";
3637 case GDB_REGNO_V10:
3638 return "v10";
3639 case GDB_REGNO_V11:
3640 return "v11";
3641 case GDB_REGNO_V12:
3642 return "v12";
3643 case GDB_REGNO_V13:
3644 return "v13";
3645 case GDB_REGNO_V14:
3646 return "v14";
3647 case GDB_REGNO_V15:
3648 return "v15";
3649 case GDB_REGNO_V16:
3650 return "v16";
3651 case GDB_REGNO_V17:
3652 return "v17";
3653 case GDB_REGNO_V18:
3654 return "v18";
3655 case GDB_REGNO_V19:
3656 return "v19";
3657 case GDB_REGNO_V20:
3658 return "v20";
3659 case GDB_REGNO_V21:
3660 return "v21";
3661 case GDB_REGNO_V22:
3662 return "v22";
3663 case GDB_REGNO_V23:
3664 return "v23";
3665 case GDB_REGNO_V24:
3666 return "v24";
3667 case GDB_REGNO_V25:
3668 return "v25";
3669 case GDB_REGNO_V26:
3670 return "v26";
3671 case GDB_REGNO_V27:
3672 return "v27";
3673 case GDB_REGNO_V28:
3674 return "v28";
3675 case GDB_REGNO_V29:
3676 return "v29";
3677 case GDB_REGNO_V30:
3678 return "v30";
3679 case GDB_REGNO_V31:
3680 return "v31";
3681 default:
3682 if (regno <= GDB_REGNO_XPR31)
3683 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
3684 else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
3685 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
3686 else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
3687 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
3688 else
3689 sprintf(buf, "gdb_regno_%d", regno);
3690 return buf;
3691 }
3692 }
3693
3694 static int register_get(struct reg *reg)
3695 {
3696 riscv_reg_info_t *reg_info = reg->arch_info;
3697 struct target *target = reg_info->target;
3698 RISCV_INFO(r);
3699
3700 if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3701 if (!r->get_register_buf) {
3702 LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3703 gdb_regno_name(reg->number));
3704 return ERROR_FAIL;
3705 }
3706
3707 if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
3708 return ERROR_FAIL;
3709 } else {
3710 uint64_t value;
3711 int result = riscv_get_register(target, &value, reg->number);
3712 if (result != ERROR_OK)
3713 return result;
3714 buf_set_u64(reg->value, 0, reg->size, value);
3715 }
3716 reg->valid = gdb_regno_cacheable(reg->number, false);
3717 char *str = buf_to_hex_str(reg->value, reg->size);
3718 LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
3719 str, reg->name, reg->valid);
3720 free(str);
3721 return ERROR_OK;
3722 }
3723
3724 static int register_set(struct reg *reg, uint8_t *buf)
3725 {
3726 riscv_reg_info_t *reg_info = reg->arch_info;
3727 struct target *target = reg_info->target;
3728 RISCV_INFO(r);
3729
3730 char *str = buf_to_hex_str(buf, reg->size);
3731 LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
3732 str, reg->name, reg->valid);
3733 free(str);
3734
3735 /* Exit early for writing x0, which on the hardware would be ignored, and we
3736 * don't want to update our cache. */
3737 if (reg->number == GDB_REGNO_ZERO)
3738 return ERROR_OK;
3739
3740 memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
3741 reg->valid = gdb_regno_cacheable(reg->number, true);
3742
3743 if (reg->number == GDB_REGNO_TDATA1 ||
3744 reg->number == GDB_REGNO_TDATA2) {
3745 r->manual_hwbp_set = true;
3746 /* When enumerating triggers, we clear any triggers with DMODE set,
3747 * assuming they were left over from a previous debug session. So make
3748 * sure that is done before a user might be setting their own triggers.
3749 */
3750 if (riscv_enumerate_triggers(target) != ERROR_OK)
3751 return ERROR_FAIL;
3752 }
3753
3754 if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3755 if (!r->set_register_buf) {
3756 LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3757 gdb_regno_name(reg->number));
3758 return ERROR_FAIL;
3759 }
3760
3761 if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
3762 return ERROR_FAIL;
3763 } else {
3764 uint64_t value = buf_get_u64(buf, 0, reg->size);
3765 if (riscv_set_register(target, reg->number, value) != ERROR_OK)
3766 return ERROR_FAIL;
3767 }
3768
3769 return ERROR_OK;
3770 }
3771
3772 static struct reg_arch_type riscv_reg_arch_type = {
3773 .get = register_get,
3774 .set = register_set
3775 };
3776
3777 struct csr_info {
3778 unsigned number;
3779 const char *name;
3780 };
3781
3782 static int cmp_csr_info(const void *p1, const void *p2)
3783 {
3784 return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
3785 }
3786
3787 int riscv_init_registers(struct target *target)
3788 {
3789 RISCV_INFO(info);
3790
3791 riscv_free_registers(target);
3792
3793 target->reg_cache = calloc(1, sizeof(*target->reg_cache));
3794 if (!target->reg_cache)
3795 return ERROR_FAIL;
3796 target->reg_cache->name = "RISC-V Registers";
3797 target->reg_cache->num_regs = GDB_REGNO_COUNT;
3798
3799 if (!list_empty(&info->expose_custom)) {
3800 range_list_t *entry;
3801 list_for_each_entry(entry, &info->expose_custom, list)
3802 target->reg_cache->num_regs += entry->high - entry->low + 1;
3803 }
3804
3805 LOG_DEBUG("create register cache for %d registers",
3806 target->reg_cache->num_regs);
3807
3808 target->reg_cache->reg_list =
3809 calloc(target->reg_cache->num_regs, sizeof(struct reg));
3810 if (!target->reg_cache->reg_list)
3811 return ERROR_FAIL;
3812
3813 const unsigned int max_reg_name_len = 12;
3814 free(info->reg_names);
3815 info->reg_names =
3816 calloc(target->reg_cache->num_regs, max_reg_name_len);
3817 if (!info->reg_names)
3818 return ERROR_FAIL;
3819 char *reg_name = info->reg_names;
3820
3821 static struct reg_feature feature_cpu = {
3822 .name = "org.gnu.gdb.riscv.cpu"
3823 };
3824 static struct reg_feature feature_fpu = {
3825 .name = "org.gnu.gdb.riscv.fpu"
3826 };
3827 static struct reg_feature feature_csr = {
3828 .name = "org.gnu.gdb.riscv.csr"
3829 };
3830 static struct reg_feature feature_vector = {
3831 .name = "org.gnu.gdb.riscv.vector"
3832 };
3833 static struct reg_feature feature_virtual = {
3834 .name = "org.gnu.gdb.riscv.virtual"
3835 };
3836 static struct reg_feature feature_custom = {
3837 .name = "org.gnu.gdb.riscv.custom"
3838 };
3839
3840 /* These types are built into gdb. */
3841 static struct reg_data_type type_ieee_single = { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" };
3842 static struct reg_data_type type_ieee_double = { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" };
3843 static struct reg_data_type_union_field single_double_fields[] = {
3844 {"float", &type_ieee_single, single_double_fields + 1},
3845 {"double", &type_ieee_double, NULL},
3846 };
3847 static struct reg_data_type_union single_double_union = {
3848 .fields = single_double_fields
3849 };
3850 static struct reg_data_type type_ieee_single_double = {
3851 .type = REG_TYPE_ARCH_DEFINED,
3852 .id = "FPU_FD",
3853 .type_class = REG_TYPE_CLASS_UNION,
3854 { .reg_type_union = &single_double_union }
3855 };
3856 static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" };
3857 static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" };
3858 static struct reg_data_type type_uint32 = { .type = REG_TYPE_UINT32, .id = "uint32" };
3859 static struct reg_data_type type_uint64 = { .type = REG_TYPE_UINT64, .id = "uint64" };
3860 static struct reg_data_type type_uint128 = { .type = REG_TYPE_UINT128, .id = "uint128" };
3861
3862 /* This is roughly the XML we want:
3863 * <vector id="bytes" type="uint8" count="16"/>
3864 * <vector id="shorts" type="uint16" count="8"/>
3865 * <vector id="words" type="uint32" count="4"/>
3866 * <vector id="longs" type="uint64" count="2"/>
3867 * <vector id="quads" type="uint128" count="1"/>
3868 * <union id="riscv_vector_type">
3869 * <field name="b" type="bytes"/>
3870 * <field name="s" type="shorts"/>
3871 * <field name="w" type="words"/>
3872 * <field name="l" type="longs"/>
3873 * <field name="q" type="quads"/>
3874 * </union>
3875 */
3876
3877 info->vector_uint8.type = &type_uint8;
3878 info->vector_uint8.count = info->vlenb;
3879 info->type_uint8_vector.type = REG_TYPE_ARCH_DEFINED;
3880 info->type_uint8_vector.id = "bytes";
3881 info->type_uint8_vector.type_class = REG_TYPE_CLASS_VECTOR;
3882 info->type_uint8_vector.reg_type_vector = &info->vector_uint8;
3883
3884 info->vector_uint16.type = &type_uint16;
3885 info->vector_uint16.count = info->vlenb / 2;
3886 info->type_uint16_vector.type = REG_TYPE_ARCH_DEFINED;
3887 info->type_uint16_vector.id = "shorts";
3888 info->type_uint16_vector.type_class = REG_TYPE_CLASS_VECTOR;
3889 info->type_uint16_vector.reg_type_vector = &info->vector_uint16;
3890
3891 info->vector_uint32.type = &type_uint32;
3892 info->vector_uint32.count = info->vlenb / 4;
3893 info->type_uint32_vector.type = REG_TYPE_ARCH_DEFINED;
3894 info->type_uint32_vector.id = "words";
3895 info->type_uint32_vector.type_class = REG_TYPE_CLASS_VECTOR;
3896 info->type_uint32_vector.reg_type_vector = &info->vector_uint32;
3897
3898 info->vector_uint64.type = &type_uint64;
3899 info->vector_uint64.count = info->vlenb / 8;
3900 info->type_uint64_vector.type = REG_TYPE_ARCH_DEFINED;
3901 info->type_uint64_vector.id = "longs";
3902 info->type_uint64_vector.type_class = REG_TYPE_CLASS_VECTOR;
3903 info->type_uint64_vector.reg_type_vector = &info->vector_uint64;
3904
3905 info->vector_uint128.type = &type_uint128;
3906 info->vector_uint128.count = info->vlenb / 16;
3907 info->type_uint128_vector.type = REG_TYPE_ARCH_DEFINED;
3908 info->type_uint128_vector.id = "quads";
3909 info->type_uint128_vector.type_class = REG_TYPE_CLASS_VECTOR;
3910 info->type_uint128_vector.reg_type_vector = &info->vector_uint128;
3911
3912 info->vector_fields[0].name = "b";
3913 info->vector_fields[0].type = &info->type_uint8_vector;
3914 if (info->vlenb >= 2) {
3915 info->vector_fields[0].next = info->vector_fields + 1;
3916 info->vector_fields[1].name = "s";
3917 info->vector_fields[1].type = &info->type_uint16_vector;
3918 } else {
3919 info->vector_fields[0].next = NULL;
3920 }
3921 if (info->vlenb >= 4) {
3922 info->vector_fields[1].next = info->vector_fields + 2;
3923 info->vector_fields[2].name = "w";
3924 info->vector_fields[2].type = &info->type_uint32_vector;
3925 } else {
3926 info->vector_fields[1].next = NULL;
3927 }
3928 if (info->vlenb >= 8) {
3929 info->vector_fields[2].next = info->vector_fields + 3;
3930 info->vector_fields[3].name = "l";
3931 info->vector_fields[3].type = &info->type_uint64_vector;
3932 } else {
3933 info->vector_fields[2].next = NULL;
3934 }
3935 if (info->vlenb >= 16) {
3936 info->vector_fields[3].next = info->vector_fields + 4;
3937 info->vector_fields[4].name = "q";
3938 info->vector_fields[4].type = &info->type_uint128_vector;
3939 } else {
3940 info->vector_fields[3].next = NULL;
3941 }
3942 info->vector_fields[4].next = NULL;
3943
3944 info->vector_union.fields = info->vector_fields;
3945
3946 info->type_vector.type = REG_TYPE_ARCH_DEFINED;
3947 info->type_vector.id = "riscv_vector";
3948 info->type_vector.type_class = REG_TYPE_CLASS_UNION;
3949 info->type_vector.reg_type_union = &info->vector_union;
3950
3951 struct csr_info csr_info[] = {
3952 #define DECLARE_CSR(name, number) { number, #name },
3953 #include "encoding.h"
3954 #undef DECLARE_CSR
3955 };
3956 /* encoding.h does not contain the registers in sorted order. */
3957 qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
3958 unsigned csr_info_index = 0;
3959
3960 int custom_within_range = 0;
3961
3962 riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
3963 if (!shared_reg_info)
3964 return ERROR_FAIL;
3965 shared_reg_info->target = target;
3966
3967 /* When gdb requests register N, gdb_get_register_packet() assumes that this
3968 * is register at index N in reg_list. So if there are certain registers
3969 * that don't exist, we need to leave holes in the list (or renumber, but
3970 * it would be nice not to have yet another set of numbers to translate
3971 * between). */
3972 for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
3973 struct reg *r = &target->reg_cache->reg_list[number];
3974 r->dirty = false;
3975 r->valid = false;
3976 r->exist = true;
3977 r->type = &riscv_reg_arch_type;
3978 r->arch_info = shared_reg_info;
3979 r->number = number;
3980 r->size = riscv_xlen(target);
3981 /* r->size is set in riscv_invalidate_register_cache, maybe because the
3982 * target is in theory allowed to change XLEN on us. But I expect a lot
3983 * of other things to break in that case as well. */
3984 if (number <= GDB_REGNO_XPR31) {
3985 r->exist = number <= GDB_REGNO_XPR15 ||
3986 !riscv_supports_extension(target, 'E');
3987 /* TODO: For now we fake that all GPRs exist because otherwise gdb
3988 * doesn't work. */
3989 r->exist = true;
3990 r->caller_save = true;
3991 switch (number) {
3992 case GDB_REGNO_ZERO:
3993 r->name = "zero";
3994 break;
3995 case GDB_REGNO_RA:
3996 r->name = "ra";
3997 break;
3998 case GDB_REGNO_SP:
3999 r->name = "sp";
4000 break;
4001 case GDB_REGNO_GP:
4002 r->name = "gp";
4003 break;
4004 case GDB_REGNO_TP:
4005 r->name = "tp";
4006 break;
4007 case GDB_REGNO_T0:
4008 r->name = "t0";
4009 break;
4010 case GDB_REGNO_T1:
4011 r->name = "t1";
4012 break;
4013 case GDB_REGNO_T2:
4014 r->name = "t2";
4015 break;
4016 case GDB_REGNO_FP:
4017 r->name = "fp";
4018 break;
4019 case GDB_REGNO_S1:
4020 r->name = "s1";
4021 break;
4022 case GDB_REGNO_A0:
4023 r->name = "a0";
4024 break;
4025 case GDB_REGNO_A1:
4026 r->name = "a1";
4027 break;
4028 case GDB_REGNO_A2:
4029 r->name = "a2";
4030 break;
4031 case GDB_REGNO_A3:
4032 r->name = "a3";
4033 break;
4034 case GDB_REGNO_A4:
4035 r->name = "a4";
4036 break;
4037 case GDB_REGNO_A5:
4038 r->name = "a5";
4039 break;
4040 case GDB_REGNO_A6:
4041 r->name = "a6";
4042 break;
4043 case GDB_REGNO_A7:
4044 r->name = "a7";
4045 break;
4046 case GDB_REGNO_S2:
4047 r->name = "s2";
4048 break;
4049 case GDB_REGNO_S3:
4050 r->name = "s3";
4051 break;
4052 case GDB_REGNO_S4:
4053 r->name = "s4";
4054 break;
4055 case GDB_REGNO_S5:
4056 r->name = "s5";
4057 break;
4058 case GDB_REGNO_S6:
4059 r->name = "s6";
4060 break;
4061 case GDB_REGNO_S7:
4062 r->name = "s7";
4063 break;
4064 case GDB_REGNO_S8:
4065 r->name = "s8";
4066 break;
4067 case GDB_REGNO_S9:
4068 r->name = "s9";
4069 break;
4070 case GDB_REGNO_S10:
4071 r->name = "s10";
4072 break;
4073 case GDB_REGNO_S11:
4074 r->name = "s11";
4075 break;
4076 case GDB_REGNO_T3:
4077 r->name = "t3";
4078 break;
4079 case GDB_REGNO_T4:
4080 r->name = "t4";
4081 break;
4082 case GDB_REGNO_T5:
4083 r->name = "t5";
4084 break;
4085 case GDB_REGNO_T6:
4086 r->name = "t6";
4087 break;
4088 }
4089 r->group = "general";
4090 r->feature = &feature_cpu;
4091 } else if (number == GDB_REGNO_PC) {
4092 r->caller_save = true;
4093 sprintf(reg_name, "pc");
4094 r->group = "general";
4095 r->feature = &feature_cpu;
4096 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
4097 r->caller_save = true;
4098 if (riscv_supports_extension(target, 'D')) {
4099 r->size = 64;
4100 if (riscv_supports_extension(target, 'F'))
4101 r->reg_data_type = &type_ieee_single_double;
4102 else
4103 r->reg_data_type = &type_ieee_double;
4104 } else if (riscv_supports_extension(target, 'F')) {
4105 r->reg_data_type = &type_ieee_single;
4106 r->size = 32;
4107 } else {
4108 r->exist = false;
4109 }
4110 switch (number) {
4111 case GDB_REGNO_FT0:
4112 r->name = "ft0";
4113 break;
4114 case GDB_REGNO_FT1:
4115 r->name = "ft1";
4116 break;
4117 case GDB_REGNO_FT2:
4118 r->name = "ft2";
4119 break;
4120 case GDB_REGNO_FT3:
4121 r->name = "ft3";
4122 break;
4123 case GDB_REGNO_FT4:
4124 r->name = "ft4";
4125 break;
4126 case GDB_REGNO_FT5:
4127 r->name = "ft5";
4128 break;
4129 case GDB_REGNO_FT6:
4130 r->name = "ft6";
4131 break;
4132 case GDB_REGNO_FT7:
4133 r->name = "ft7";
4134 break;
4135 case GDB_REGNO_FS0:
4136 r->name = "fs0";
4137 break;
4138 case GDB_REGNO_FS1:
4139 r->name = "fs1";
4140 break;
4141 case GDB_REGNO_FA0:
4142 r->name = "fa0";
4143 break;
4144 case GDB_REGNO_FA1:
4145 r->name = "fa1";
4146 break;
4147 case GDB_REGNO_FA2:
4148 r->name = "fa2";
4149 break;
4150 case GDB_REGNO_FA3:
4151 r->name = "fa3";
4152 break;
4153 case GDB_REGNO_FA4:
4154 r->name = "fa4";
4155 break;
4156 case GDB_REGNO_FA5:
4157 r->name = "fa5";
4158 break;
4159 case GDB_REGNO_FA6:
4160 r->name = "fa6";
4161 break;
4162 case GDB_REGNO_FA7:
4163 r->name = "fa7";
4164 break;
4165 case GDB_REGNO_FS2:
4166 r->name = "fs2";
4167 break;
4168 case GDB_REGNO_FS3:
4169 r->name = "fs3";
4170 break;
4171 case GDB_REGNO_FS4:
4172 r->name = "fs4";
4173 break;
4174 case GDB_REGNO_FS5:
4175 r->name = "fs5";
4176 break;
4177 case GDB_REGNO_FS6:
4178 r->name = "fs6";
4179 break;
4180 case GDB_REGNO_FS7:
4181 r->name = "fs7";
4182 break;
4183 case GDB_REGNO_FS8:
4184 r->name = "fs8";
4185 break;
4186 case GDB_REGNO_FS9:
4187 r->name = "fs9";
4188 break;
4189 case GDB_REGNO_FS10:
4190 r->name = "fs10";
4191 break;
4192 case GDB_REGNO_FS11:
4193 r->name = "fs11";
4194 break;
4195 case GDB_REGNO_FT8:
4196 r->name = "ft8";
4197 break;
4198 case GDB_REGNO_FT9:
4199 r->name = "ft9";
4200 break;
4201 case GDB_REGNO_FT10:
4202 r->name = "ft10";
4203 break;
4204 case GDB_REGNO_FT11:
4205 r->name = "ft11";
4206 break;
4207 }
4208 r->group = "float";
4209 r->feature = &feature_fpu;
4210 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
4211 r->group = "csr";
4212 r->feature = &feature_csr;
4213 unsigned csr_number = number - GDB_REGNO_CSR0;
4214
4215 while (csr_info[csr_info_index].number < csr_number &&
4216 csr_info_index < ARRAY_SIZE(csr_info) - 1) {
4217 csr_info_index++;
4218 }
4219 if (csr_info[csr_info_index].number == csr_number) {
4220 r->name = csr_info[csr_info_index].name;
4221 } else {
4222 sprintf(reg_name, "csr%d", csr_number);
4223 /* Assume unnamed registers don't exist, unless we have some
4224 * configuration that tells us otherwise. That's important
4225 * because eg. Eclipse crashes if a target has too many
4226 * registers, and apparently has no way of only showing a
4227 * subset of registers in any case. */
4228 r->exist = false;
4229 }
4230
4231 switch (csr_number) {
4232 case CSR_FFLAGS:
4233 case CSR_FRM:
4234 case CSR_FCSR:
4235 r->exist = riscv_supports_extension(target, 'F');
4236 r->group = "float";
4237 r->feature = &feature_fpu;
4238 break;
4239 case CSR_SSTATUS:
4240 case CSR_STVEC:
4241 case CSR_SIP:
4242 case CSR_SIE:
4243 case CSR_SCOUNTEREN:
4244 case CSR_SSCRATCH:
4245 case CSR_SEPC:
4246 case CSR_SCAUSE:
4247 case CSR_STVAL:
4248 case CSR_SATP:
4249 r->exist = riscv_supports_extension(target, 'S');
4250 break;
4251 case CSR_MEDELEG:
4252 case CSR_MIDELEG:
4253 /* "In systems with only M-mode, or with both M-mode and
4254 * U-mode but without U-mode trap support, the medeleg and
4255 * mideleg registers should not exist." */
4256 r->exist = riscv_supports_extension(target, 'S') ||
4257 riscv_supports_extension(target, 'N');
4258 break;
4259
4260 case CSR_PMPCFG1:
4261 case CSR_PMPCFG3:
4262 case CSR_CYCLEH:
4263 case CSR_TIMEH:
4264 case CSR_INSTRETH:
4265 case CSR_HPMCOUNTER3H:
4266 case CSR_HPMCOUNTER4H:
4267 case CSR_HPMCOUNTER5H:
4268 case CSR_HPMCOUNTER6H:
4269 case CSR_HPMCOUNTER7H:
4270 case CSR_HPMCOUNTER8H:
4271 case CSR_HPMCOUNTER9H:
4272 case CSR_HPMCOUNTER10H:
4273 case CSR_HPMCOUNTER11H:
4274 case CSR_HPMCOUNTER12H:
4275 case CSR_HPMCOUNTER13H:
4276 case CSR_HPMCOUNTER14H:
4277 case CSR_HPMCOUNTER15H:
4278 case CSR_HPMCOUNTER16H:
4279 case CSR_HPMCOUNTER17H:
4280 case CSR_HPMCOUNTER18H:
4281 case CSR_HPMCOUNTER19H:
4282 case CSR_HPMCOUNTER20H:
4283 case CSR_HPMCOUNTER21H:
4284 case CSR_HPMCOUNTER22H:
4285 case CSR_HPMCOUNTER23H:
4286 case CSR_HPMCOUNTER24H:
4287 case CSR_HPMCOUNTER25H:
4288 case CSR_HPMCOUNTER26H:
4289 case CSR_HPMCOUNTER27H:
4290 case CSR_HPMCOUNTER28H:
4291 case CSR_HPMCOUNTER29H:
4292 case CSR_HPMCOUNTER30H:
4293 case CSR_HPMCOUNTER31H:
4294 case CSR_MCYCLEH:
4295 case CSR_MINSTRETH:
4296 case CSR_MHPMCOUNTER3H:
4297 case CSR_MHPMCOUNTER4H:
4298 case CSR_MHPMCOUNTER5H:
4299 case CSR_MHPMCOUNTER6H:
4300 case CSR_MHPMCOUNTER7H:
4301 case CSR_MHPMCOUNTER8H:
4302 case CSR_MHPMCOUNTER9H:
4303 case CSR_MHPMCOUNTER10H:
4304 case CSR_MHPMCOUNTER11H:
4305 case CSR_MHPMCOUNTER12H:
4306 case CSR_MHPMCOUNTER13H:
4307 case CSR_MHPMCOUNTER14H:
4308 case CSR_MHPMCOUNTER15H:
4309 case CSR_MHPMCOUNTER16H:
4310 case CSR_MHPMCOUNTER17H:
4311 case CSR_MHPMCOUNTER18H:
4312 case CSR_MHPMCOUNTER19H:
4313 case CSR_MHPMCOUNTER20H:
4314 case CSR_MHPMCOUNTER21H:
4315 case CSR_MHPMCOUNTER22H:
4316 case CSR_MHPMCOUNTER23H:
4317 case CSR_MHPMCOUNTER24H:
4318 case CSR_MHPMCOUNTER25H:
4319 case CSR_MHPMCOUNTER26H:
4320 case CSR_MHPMCOUNTER27H:
4321 case CSR_MHPMCOUNTER28H:
4322 case CSR_MHPMCOUNTER29H:
4323 case CSR_MHPMCOUNTER30H:
4324 case CSR_MHPMCOUNTER31H:
4325 r->exist = riscv_xlen(target) == 32;
4326 break;
4327
4328 case CSR_VSTART:
4329 case CSR_VXSAT:
4330 case CSR_VXRM:
4331 case CSR_VL:
4332 case CSR_VTYPE:
4333 case CSR_VLENB:
4334 r->exist = riscv_supports_extension(target, 'V');
4335 break;
4336 }
4337
4338 if (!r->exist && !list_empty(&info->expose_csr)) {
4339 range_list_t *entry;
4340 list_for_each_entry(entry, &info->expose_csr, list)
4341 if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
4342 if (entry->name) {
4343 *reg_name = 0;
4344 r->name = entry->name;
4345 }
4346
4347 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4348 csr_number, entry->name ? entry->name : reg_name);
4349
4350 r->exist = true;
4351 break;
4352 }
4353 }
4354
4355 } else if (number == GDB_REGNO_PRIV) {
4356 sprintf(reg_name, "priv");
4357 r->group = "general";
4358 r->feature = &feature_virtual;
4359 r->size = 8;
4360
4361 } else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
4362 r->caller_save = false;
4363 r->exist = riscv_supports_extension(target, 'V') && info->vlenb;
4364 r->size = info->vlenb * 8;
4365 sprintf(reg_name, "v%d", number - GDB_REGNO_V0);
4366 r->group = "vector";
4367 r->feature = &feature_vector;
4368 r->reg_data_type = &info->type_vector;
4369
4370 } else if (number >= GDB_REGNO_COUNT) {
4371 /* Custom registers. */
4372 assert(!list_empty(&info->expose_custom));
4373
4374 range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
4375
4376 unsigned custom_number = range->low + custom_within_range;
4377
4378 r->group = "custom";
4379 r->feature = &feature_custom;
4380 r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
4381 if (!r->arch_info)
4382 return ERROR_FAIL;
4383 ((riscv_reg_info_t *) r->arch_info)->target = target;
4384 ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
4385 sprintf(reg_name, "custom%d", custom_number);
4386
4387 if (range->name) {
4388 *reg_name = 0;
4389 r->name = range->name;
4390 }
4391
4392 LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4393 number, range->name ? range->name : reg_name);
4394
4395 custom_within_range++;
4396 if (custom_within_range > range->high - range->low) {
4397 custom_within_range = 0;
4398 list_rotate_left(&info->expose_custom);
4399 }
4400 }
4401
4402 if (reg_name[0]) {
4403 r->name = reg_name;
4404 reg_name += strlen(reg_name) + 1;
4405 assert(reg_name < info->reg_names + target->reg_cache->num_regs *
4406 max_reg_name_len);
4407 }
4408 r->value = calloc(1, DIV_ROUND_UP(r->size, 8));
4409 }
4410
4411 return ERROR_OK;
4412 }
4413
4414
4415 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
4416 riscv_bscan_tunneled_scan_context_t *ctxt)
4417 {
4418 jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
4419
4420 memset(ctxt->tunneled_dr, 0, sizeof(ctxt->tunneled_dr));
4421 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
4422 ctxt->tunneled_dr[3].num_bits = 1;
4423 ctxt->tunneled_dr[3].out_value = bscan_one;
4424 ctxt->tunneled_dr[2].num_bits = 7;
4425 ctxt->tunneled_dr_width = field->num_bits;
4426 ctxt->tunneled_dr[2].out_value = &ctxt->tunneled_dr_width;
4427 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4428 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4429
4430 ctxt->tunneled_dr[1].num_bits = field->num_bits + 1;
4431 ctxt->tunneled_dr[1].out_value = field->out_value;
4432 ctxt->tunneled_dr[1].in_value = field->in_value;
4433
4434 ctxt->tunneled_dr[0].num_bits = 3;
4435 ctxt->tunneled_dr[0].out_value = bscan_zero;
4436 } else {
4437 /* BSCAN_TUNNEL_NESTED_TAP */
4438 ctxt->tunneled_dr[0].num_bits = 1;
4439 ctxt->tunneled_dr[0].out_value = bscan_one;
4440 ctxt->tunneled_dr[1].num_bits = 7;
4441 ctxt->tunneled_dr_width = field->num_bits;
4442 ctxt->tunneled_dr[1].out_value = &ctxt->tunneled_dr_width;
4443 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4444 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4445 ctxt->tunneled_dr[2].num_bits = field->num_bits + 1;
4446 ctxt->tunneled_dr[2].out_value = field->out_value;
4447 ctxt->tunneled_dr[2].in_value = field->in_value;
4448 ctxt->tunneled_dr[3].num_bits = 3;
4449 ctxt->tunneled_dr[3].out_value = bscan_zero;
4450 }
4451 jtag_add_dr_scan(target->tap, ARRAY_SIZE(ctxt->tunneled_dr), ctxt->tunneled_dr, TAP_IDLE);
4452 }
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