1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2018 by Square, Inc. *
5 * Steven Stallion <stallion@squareup.com> *
6 * James Zhao <hjz@squareup.com> *
7 ***************************************************************************/
13 #include <helper/binarybuffer.h>
14 #include <helper/command.h>
15 #include <helper/log.h>
16 #include <helper/time_support.h>
17 #include <helper/types.h>
18 #include <jtag/interface.h>
19 #include <target/breakpoints.h>
20 #include <target/register.h>
21 #include <target/target.h>
22 #include <target/target_type.h>
26 #define RESET_TIMEOUT 5000 /* 5s */
27 #define STEP_TIMEOUT 1000 /* 1s */
30 * eSi-RISC targets support a configurable number of interrupts;
31 * up to 32 interrupts are supported.
33 static const char * const esirisc_exception_strings
[] = {
34 [EID_RESET
] = "Reset",
35 [EID_HARDWARE_FAILURE
] = "HardwareFailure",
37 [EID_INST_BREAKPOINT
] = "InstBreakpoint",
38 [EID_DATA_BREAKPOINT
] = "DataBreakpoint",
39 [EID_UNSUPPORTED
] = "Unsupported",
40 [EID_PRIVILEGE_VIOLATION
] = "PrivilegeViolation",
41 [EID_INST_BUS_ERROR
] = "InstBusError",
42 [EID_DATA_BUS_ERROR
] = "DataBusError",
43 [EID_ALIGNMENT_ERROR
] = "AlignmentError",
44 [EID_ARITHMETIC_ERROR
] = "ArithmeticError",
45 [EID_SYSTEM_CALL
] = "SystemCall",
46 [EID_MEMORY_MANAGEMENT
] = "MemoryManagement",
47 [EID_UNRECOVERABLE
] = "Unrecoverable",
48 [EID_INTERRUPT_N
+0] = "Interrupt0",
49 [EID_INTERRUPT_N
+1] = "Interrupt1",
50 [EID_INTERRUPT_N
+2] = "Interrupt2",
51 [EID_INTERRUPT_N
+3] = "Interrupt3",
52 [EID_INTERRUPT_N
+4] = "Interrupt4",
53 [EID_INTERRUPT_N
+5] = "Interrupt5",
54 [EID_INTERRUPT_N
+6] = "Interrupt6",
55 [EID_INTERRUPT_N
+7] = "Interrupt7",
56 [EID_INTERRUPT_N
+8] = "Interrupt8",
57 [EID_INTERRUPT_N
+9] = "Interrupt9",
58 [EID_INTERRUPT_N
+10] = "Interrupt10",
59 [EID_INTERRUPT_N
+11] = "Interrupt11",
60 [EID_INTERRUPT_N
+12] = "Interrupt12",
61 [EID_INTERRUPT_N
+13] = "Interrupt13",
62 [EID_INTERRUPT_N
+14] = "Interrupt14",
63 [EID_INTERRUPT_N
+15] = "Interrupt15",
64 [EID_INTERRUPT_N
+16] = "Interrupt16",
65 [EID_INTERRUPT_N
+17] = "Interrupt17",
66 [EID_INTERRUPT_N
+18] = "Interrupt18",
67 [EID_INTERRUPT_N
+19] = "Interrupt19",
68 [EID_INTERRUPT_N
+20] = "Interrupt20",
69 [EID_INTERRUPT_N
+21] = "Interrupt21",
70 [EID_INTERRUPT_N
+22] = "Interrupt22",
71 [EID_INTERRUPT_N
+23] = "Interrupt23",
72 [EID_INTERRUPT_N
+24] = "Interrupt24",
73 [EID_INTERRUPT_N
+25] = "Interrupt25",
74 [EID_INTERRUPT_N
+26] = "Interrupt26",
75 [EID_INTERRUPT_N
+27] = "Interrupt27",
76 [EID_INTERRUPT_N
+28] = "Interrupt28",
77 [EID_INTERRUPT_N
+29] = "Interrupt29",
78 [EID_INTERRUPT_N
+30] = "Interrupt30",
79 [EID_INTERRUPT_N
+31] = "Interrupt31",
83 * eSi-RISC targets support a configurable number of general purpose
84 * registers; 8, 16, and 32 registers are supported.
87 enum esirisc_reg_num number
;
92 { ESIRISC_SP
, "sp", REG_TYPE_DATA_PTR
, "general" },
93 { ESIRISC_RA
, "ra", REG_TYPE_INT
, "general" },
94 { ESIRISC_R2
, "r2", REG_TYPE_INT
, "general" },
95 { ESIRISC_R3
, "r3", REG_TYPE_INT
, "general" },
96 { ESIRISC_R4
, "r4", REG_TYPE_INT
, "general" },
97 { ESIRISC_R5
, "r5", REG_TYPE_INT
, "general" },
98 { ESIRISC_R6
, "r6", REG_TYPE_INT
, "general" },
99 { ESIRISC_R7
, "r7", REG_TYPE_INT
, "general" },
100 { ESIRISC_R8
, "r8", REG_TYPE_INT
, "general" },
101 { ESIRISC_R9
, "r9", REG_TYPE_INT
, "general" },
102 { ESIRISC_R10
, "r10", REG_TYPE_INT
, "general" },
103 { ESIRISC_R11
, "r11", REG_TYPE_INT
, "general" },
104 { ESIRISC_R12
, "r12", REG_TYPE_INT
, "general" },
105 { ESIRISC_R13
, "r13", REG_TYPE_INT
, "general" },
106 { ESIRISC_R14
, "r14", REG_TYPE_INT
, "general" },
107 { ESIRISC_R15
, "r15", REG_TYPE_INT
, "general" },
108 { ESIRISC_R16
, "r16", REG_TYPE_INT
, "general" },
109 { ESIRISC_R17
, "r17", REG_TYPE_INT
, "general" },
110 { ESIRISC_R18
, "r18", REG_TYPE_INT
, "general" },
111 { ESIRISC_R19
, "r19", REG_TYPE_INT
, "general" },
112 { ESIRISC_R20
, "r20", REG_TYPE_INT
, "general" },
113 { ESIRISC_R21
, "r21", REG_TYPE_INT
, "general" },
114 { ESIRISC_R22
, "r22", REG_TYPE_INT
, "general" },
115 { ESIRISC_R23
, "r23", REG_TYPE_INT
, "general" },
116 { ESIRISC_R24
, "r24", REG_TYPE_INT
, "general" },
117 { ESIRISC_R25
, "r25", REG_TYPE_INT
, "general" },
118 { ESIRISC_R26
, "r26", REG_TYPE_INT
, "general" },
119 { ESIRISC_R27
, "r27", REG_TYPE_INT
, "general" },
120 { ESIRISC_R28
, "r28", REG_TYPE_INT
, "general" },
121 { ESIRISC_R29
, "r29", REG_TYPE_INT
, "general" },
122 { ESIRISC_R30
, "r30", REG_TYPE_INT
, "general" },
123 { ESIRISC_R31
, "r31", REG_TYPE_INT
, "general" },
127 * Control and Status Registers (CSRs) are largely defined as belonging
128 * to the system register group. The exception to this rule are the PC
129 * and CAS registers, which belong to the general group. While debug is
130 * active, EPC, ECAS, and ETC must be used to read and write the PC,
131 * CAS, and TC CSRs, respectively.
133 static const struct {
134 enum esirisc_reg_num number
;
141 { ESIRISC_PC
, CSR_THREAD
, CSR_THREAD_EPC
, "PC", REG_TYPE_CODE_PTR
, "general" }, /* PC -> EPC */
142 { ESIRISC_CAS
, CSR_THREAD
, CSR_THREAD_ECAS
, "CAS", REG_TYPE_INT
, "general" }, /* CAS -> ECAS */
143 { ESIRISC_TC
, CSR_THREAD
, CSR_THREAD_ETC
, "TC", REG_TYPE_INT
, "system" }, /* TC -> ETC */
144 { ESIRISC_ETA
, CSR_THREAD
, CSR_THREAD_ETA
, "ETA", REG_TYPE_INT
, "system" },
145 { ESIRISC_ETC
, CSR_THREAD
, CSR_THREAD_ETC
, "ETC", REG_TYPE_INT
, "system" },
146 { ESIRISC_EPC
, CSR_THREAD
, CSR_THREAD_EPC
, "EPC", REG_TYPE_CODE_PTR
, "system" },
147 { ESIRISC_ECAS
, CSR_THREAD
, CSR_THREAD_ECAS
, "ECAS", REG_TYPE_INT
, "system" },
148 { ESIRISC_EID
, CSR_THREAD
, CSR_THREAD_EID
, "EID", REG_TYPE_INT
, "system" },
149 { ESIRISC_ED
, CSR_THREAD
, CSR_THREAD_ED
, "ED", REG_TYPE_INT
, "system" },
150 { ESIRISC_IP
, CSR_INTERRUPT
, CSR_INTERRUPT_IP
, "IP", REG_TYPE_INT
, "system"},
151 { ESIRISC_IM
, CSR_INTERRUPT
, CSR_INTERRUPT_IM
, "IM", REG_TYPE_INT
, "system"},
152 { ESIRISC_IS
, CSR_INTERRUPT
, CSR_INTERRUPT_IS
, "IS", REG_TYPE_INT
, "system"},
153 { ESIRISC_IT
, CSR_INTERRUPT
, CSR_INTERRUPT_IT
, "IT", REG_TYPE_INT
, "system"},
156 static int esirisc_disable_interrupts(struct target
*target
)
158 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
159 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
165 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, &etc
);
166 if (retval
!= ERROR_OK
) {
167 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target
));
171 etc
&= ~(1<<0); /* TC.I */
173 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, etc
);
174 if (retval
!= ERROR_OK
) {
175 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target
));
183 static int esirisc_enable_interrupts(struct target
*target
)
185 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
186 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
192 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, &etc
);
193 if (retval
!= ERROR_OK
) {
194 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target
));
198 etc
|= (1<<0); /* TC.I */
200 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, etc
);
201 if (retval
!= ERROR_OK
) {
202 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target
));
210 static int esirisc_save_interrupts(struct target
*target
)
212 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
213 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
217 int retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
,
219 if (retval
!= ERROR_OK
) {
220 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target
));
227 static int esirisc_restore_interrupts(struct target
*target
)
229 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
230 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
234 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
,
236 if (retval
!= ERROR_OK
) {
237 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target
));
245 static int esirisc_save_hwdc(struct target
*target
)
247 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
248 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
252 int retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_HWDC
,
253 &esirisc
->hwdc_save
);
254 if (retval
!= ERROR_OK
) {
255 LOG_ERROR("%s: failed to read Thread CSR: HWDC", target_name(target
));
263 static int esirisc_restore_hwdc(struct target
*target
)
265 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
266 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
270 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_HWDC
,
272 if (retval
!= ERROR_OK
) {
273 LOG_ERROR("%s: failed to write Debug CSR: HWDC", target_name(target
));
280 static int esirisc_save_context(struct target
*target
)
282 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
286 for (unsigned i
= 0; i
< esirisc
->reg_cache
->num_regs
; ++i
) {
287 struct reg
*reg
= esirisc
->reg_cache
->reg_list
+ i
;
288 struct esirisc_reg
*reg_info
= reg
->arch_info
;
290 if (reg
->exist
&& !reg
->valid
)
297 static int esirisc_restore_context(struct target
*target
)
299 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
303 for (unsigned i
= 0; i
< esirisc
->reg_cache
->num_regs
; ++i
) {
304 struct reg
*reg
= esirisc
->reg_cache
->reg_list
+ i
;
305 struct esirisc_reg
*reg_info
= reg
->arch_info
;
307 if (reg
->exist
&& reg
->dirty
)
308 reg_info
->write(reg
);
314 static int esirisc_flush_caches(struct target
*target
)
316 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
317 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
321 if (target
->state
!= TARGET_HALTED
) {
322 LOG_TARGET_ERROR(target
, "not halted");
323 return ERROR_TARGET_NOT_HALTED
;
326 int retval
= esirisc_jtag_flush_caches(jtag_info
);
327 if (retval
!= ERROR_OK
) {
328 LOG_ERROR("%s: failed to flush caches", target_name(target
));
335 static int esirisc_wait_debug_active(struct esirisc_common
*esirisc
, int ms
)
337 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
344 int retval
= esirisc_jtag_enable_debug(jtag_info
);
345 if (retval
== ERROR_OK
&& esirisc_jtag_is_debug_active(jtag_info
))
348 if ((timeval_ms() - t
) > ms
)
349 return ERROR_TARGET_TIMEOUT
;
355 static int esirisc_read_memory(struct target
*target
, target_addr_t address
,
356 uint32_t size
, uint32_t count
, uint8_t *buffer
)
358 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
359 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
364 int num_bits
= 8 * size
;
365 for (uint32_t i
= 0; i
< count
; ++i
) {
366 union esirisc_memory value
;
370 case sizeof(value
.word
):
371 value_p
= &value
.word
;
372 retval
= esirisc_jtag_read_word(jtag_info
, address
, value_p
);
375 case sizeof(value
.hword
):
376 value_p
= &value
.hword
;
377 retval
= esirisc_jtag_read_hword(jtag_info
, address
, value_p
);
380 case sizeof(value
.byte
):
381 value_p
= &value
.byte
;
382 retval
= esirisc_jtag_read_byte(jtag_info
, address
, value_p
);
386 LOG_ERROR("%s: unsupported size: %" PRIu32
, target_name(target
), size
);
390 if (retval
!= ERROR_OK
) {
391 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR
, target_name(target
),
396 buf_cpy(value_p
, buffer
, num_bits
);
404 static int esirisc_write_memory(struct target
*target
, target_addr_t address
,
405 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
407 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
408 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
413 int num_bits
= 8 * size
;
414 for (uint32_t i
= 0; i
< count
; ++i
) {
415 union esirisc_memory value
;
418 case sizeof(value
.word
):
419 value
.word
= buf_get_u32(buffer
, 0, num_bits
);
420 retval
= esirisc_jtag_write_word(jtag_info
, address
, value
.word
);
423 case sizeof(value
.hword
):
424 value
.hword
= buf_get_u32(buffer
, 0, num_bits
);
425 retval
= esirisc_jtag_write_hword(jtag_info
, address
, value
.hword
);
428 case sizeof(value
.byte
):
429 value
.byte
= buf_get_u32(buffer
, 0, num_bits
);
430 retval
= esirisc_jtag_write_byte(jtag_info
, address
, value
.byte
);
434 LOG_ERROR("%s: unsupported size: %" PRIu32
, target_name(target
), size
);
438 if (retval
!= ERROR_OK
) {
439 LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR
, target_name(target
),
451 static int esirisc_checksum_memory(struct target
*target
, target_addr_t address
,
452 uint32_t count
, uint32_t *checksum
)
454 return ERROR_FAIL
; /* not supported */
457 static int esirisc_next_breakpoint(struct target
*target
)
459 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
460 struct breakpoint
**breakpoints_p
= esirisc
->breakpoints_p
;
461 struct breakpoint
**breakpoints_e
= breakpoints_p
+ esirisc
->num_breakpoints
;
465 for (int bp_index
= 0; breakpoints_p
< breakpoints_e
; ++breakpoints_p
, ++bp_index
)
472 static int esirisc_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
474 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
475 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
483 * The default linker scripts provided by the eSi-RISC toolchain do
484 * not specify attributes on memory regions, which results in
485 * incorrect application of software breakpoints by GDB. Targets
486 * must be configured with `gdb breakpoint_override hard` as
487 * software breakpoints are not supported.
489 if (breakpoint
->type
!= BKPT_HARD
)
490 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
492 bp_index
= esirisc_next_breakpoint(target
);
494 LOG_ERROR("%s: out of hardware breakpoints", target_name(target
));
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
498 breakpoint_hw_set(breakpoint
, bp_index
);
499 esirisc
->breakpoints_p
[bp_index
] = breakpoint
;
501 /* specify instruction breakpoint address */
502 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBA_N
+ bp_index
,
503 breakpoint
->address
);
504 if (retval
!= ERROR_OK
) {
505 LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target
));
509 /* enable instruction breakpoint */
510 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, &ibc
);
511 if (retval
!= ERROR_OK
) {
512 LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target
));
516 ibc
|= (1 << bp_index
); /* IBC.In */
518 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, ibc
);
519 if (retval
!= ERROR_OK
) {
520 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target
));
527 static int esirisc_add_breakpoints(struct target
*target
)
529 struct breakpoint
*breakpoint
= target
->breakpoints
;
534 if (!breakpoint
->is_set
)
535 esirisc_add_breakpoint(target
, breakpoint
);
537 breakpoint
= breakpoint
->next
;
543 static int esirisc_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
545 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
546 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
547 unsigned int bp_index
= breakpoint
->number
;
553 /* disable instruction breakpoint */
554 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, &ibc
);
555 if (retval
!= ERROR_OK
) {
556 LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target
));
560 ibc
&= ~(1 << bp_index
); /* IBC.In */
562 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, ibc
);
563 if (retval
!= ERROR_OK
) {
564 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target
));
568 esirisc
->breakpoints_p
[bp_index
] = NULL
;
569 breakpoint
->is_set
= false;
574 static int esirisc_remove_breakpoints(struct target
*target
)
576 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
577 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
581 /* clear instruction breakpoints */
582 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, 0);
583 if (retval
!= ERROR_OK
) {
584 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target
));
588 memset(esirisc
->breakpoints_p
, 0, sizeof(esirisc
->breakpoints_p
));
593 static int esirisc_next_watchpoint(struct target
*target
)
595 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
596 struct watchpoint
**watchpoints_p
= esirisc
->watchpoints_p
;
597 struct watchpoint
**watchpoints_e
= watchpoints_p
+ esirisc
->num_watchpoints
;
601 for (int wp_index
= 0; watchpoints_p
< watchpoints_e
; ++watchpoints_p
, ++wp_index
)
608 static int esirisc_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
610 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
611 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
618 wp_index
= esirisc_next_watchpoint(target
);
620 LOG_ERROR("%s: out of hardware watchpoints", target_name(target
));
624 watchpoint_set(watchpoint
, wp_index
);
625 esirisc
->watchpoints_p
[wp_index
] = watchpoint
;
627 /* specify data breakpoint address */
628 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBA_N
+ wp_index
,
629 watchpoint
->address
);
630 if (retval
!= ERROR_OK
) {
631 LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target
));
635 /* specify data breakpoint size */
636 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBS
, &dbs
);
637 if (retval
!= ERROR_OK
) {
638 LOG_ERROR("%s: failed to read Debug CSR: DBS", target_name(target
));
643 switch (watchpoint
->length
) {
644 case sizeof(uint64_t):
647 case sizeof(uint32_t):
651 case sizeof(uint16_t):
655 case sizeof(uint8_t):
660 LOG_ERROR("%s: unsupported length: %" PRIu32
, target_name(target
),
665 dbs
|= (sn
<< (2 * wp_index
)); /* DBS.Sn */
667 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBS
, dbs
);
668 if (retval
!= ERROR_OK
) {
669 LOG_ERROR("%s: failed to write Debug CSR: DBS", target_name(target
));
673 /* enable data breakpoint */
674 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, &dbc
);
675 if (retval
!= ERROR_OK
) {
676 LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target
));
681 switch (watchpoint
->rw
) {
695 LOG_ERROR("%s: unsupported rw: %" PRId32
, target_name(target
),
700 dbc
|= (dn
<< (2 * wp_index
)); /* DBC.Dn */
702 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, dbc
);
703 if (retval
!= ERROR_OK
) {
704 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target
));
711 static int esirisc_add_watchpoints(struct target
*target
)
713 struct watchpoint
*watchpoint
= target
->watchpoints
;
718 if (!watchpoint
->is_set
)
719 esirisc_add_watchpoint(target
, watchpoint
);
721 watchpoint
= watchpoint
->next
;
727 static int esirisc_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
729 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
730 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
731 unsigned int wp_index
= watchpoint
->number
;
737 /* disable data breakpoint */
738 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, &dbc
);
739 if (retval
!= ERROR_OK
) {
740 LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target
));
744 dbc
&= ~(0x3 << (2 * wp_index
)); /* DBC.Dn */
746 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, dbc
);
747 if (retval
!= ERROR_OK
) {
748 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target
));
752 esirisc
->watchpoints_p
[wp_index
] = NULL
;
753 watchpoint
->is_set
= false;
758 static int esirisc_remove_watchpoints(struct target
*target
)
760 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
761 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
765 /* clear data breakpoints */
766 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, 0);
767 if (retval
!= ERROR_OK
) {
768 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target
));
772 memset(esirisc
->watchpoints_p
, 0, sizeof(esirisc
->watchpoints_p
));
777 static int esirisc_halt(struct target
*target
)
779 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
780 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
784 if (target
->state
== TARGET_HALTED
)
787 int retval
= esirisc_jtag_break(jtag_info
);
788 if (retval
!= ERROR_OK
) {
789 LOG_ERROR("%s: failed to halt target", target_name(target
));
793 target
->debug_reason
= DBG_REASON_DBGRQ
;
798 static int esirisc_disable_step(struct target
*target
)
800 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
801 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
807 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, &dc
);
808 if (retval
!= ERROR_OK
) {
809 LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target
));
813 dc
&= ~(1<<0); /* DC.S */
815 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, dc
);
816 if (retval
!= ERROR_OK
) {
817 LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target
));
824 static int esirisc_enable_step(struct target
*target
)
826 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
827 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
833 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, &dc
);
834 if (retval
!= ERROR_OK
) {
835 LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target
));
839 dc
|= (1<<0); /* DC.S */
841 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, dc
);
842 if (retval
!= ERROR_OK
) {
843 LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target
));
850 static int esirisc_resume_or_step(struct target
*target
, int current
, target_addr_t address
,
851 int handle_breakpoints
, int debug_execution
, bool step
)
853 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
854 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
855 struct breakpoint
*breakpoint
= NULL
;
860 if (target
->state
!= TARGET_HALTED
) {
861 LOG_TARGET_ERROR(target
, "not halted");
862 return ERROR_TARGET_NOT_HALTED
;
865 if (!debug_execution
) {
866 target_free_all_working_areas(target
);
867 esirisc_add_breakpoints(target
);
868 esirisc_add_watchpoints(target
);
872 address
= buf_get_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
);
874 buf_set_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
, address
);
875 esirisc
->epc
->dirty
= true;
876 esirisc
->epc
->valid
= true;
879 esirisc_restore_context(target
);
881 if (esirisc_has_cache(esirisc
))
882 esirisc_flush_caches(target
);
884 if (handle_breakpoints
) {
885 breakpoint
= breakpoint_find(target
, address
);
887 esirisc_remove_breakpoint(target
, breakpoint
);
891 esirisc_disable_interrupts(target
);
892 esirisc_enable_step(target
);
893 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
895 esirisc_disable_step(target
);
896 esirisc_restore_interrupts(target
);
897 target
->debug_reason
= DBG_REASON_NOTHALTED
;
900 esirisc_restore_hwdc(target
);
902 retval
= esirisc_jtag_continue(jtag_info
);
903 if (retval
!= ERROR_OK
) {
904 LOG_ERROR("%s: failed to resume target", target_name(target
));
908 register_cache_invalidate(esirisc
->reg_cache
);
910 if (!debug_execution
) {
911 target
->state
= TARGET_RUNNING
;
912 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
914 target
->state
= TARGET_DEBUG_RUNNING
;
915 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
921 static int esirisc_resume(struct target
*target
, int current
, target_addr_t address
,
922 int handle_breakpoints
, int debug_execution
)
926 return esirisc_resume_or_step(target
, current
, address
,
927 handle_breakpoints
, debug_execution
, false);
930 static int esirisc_step(struct target
*target
, int current
, target_addr_t address
,
931 int handle_breakpoints
)
935 return esirisc_resume_or_step(target
, current
, address
,
936 handle_breakpoints
, 0, true);
939 static int esirisc_debug_step(struct target
*target
)
941 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
942 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
947 esirisc_disable_interrupts(target
);
948 esirisc_enable_step(target
);
950 retval
= esirisc_jtag_continue(jtag_info
);
951 if (retval
!= ERROR_OK
) {
952 LOG_ERROR("%s: failed to resume target", target_name(target
));
956 retval
= esirisc_wait_debug_active(esirisc
, STEP_TIMEOUT
);
957 if (retval
!= ERROR_OK
) {
958 LOG_ERROR("%s: step timed out", target_name(target
));
962 esirisc_disable_step(target
);
963 esirisc_restore_interrupts(target
);
968 static int esirisc_debug_reset(struct target
*target
)
970 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
971 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
976 retval
= esirisc_jtag_assert_reset(jtag_info
);
977 if (retval
!= ERROR_OK
) {
978 LOG_ERROR("%s: failed to assert reset", target_name(target
));
982 retval
= esirisc_jtag_deassert_reset(jtag_info
);
983 if (retval
!= ERROR_OK
) {
984 LOG_ERROR("%s: failed to deassert reset", target_name(target
));
988 retval
= esirisc_wait_debug_active(esirisc
, RESET_TIMEOUT
);
989 if (retval
!= ERROR_OK
) {
990 LOG_ERROR("%s: reset timed out", target_name(target
));
997 static int esirisc_debug_enable(struct target
*target
)
999 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1000 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1005 retval
= esirisc_jtag_enable_debug(jtag_info
);
1006 if (retval
!= ERROR_OK
) {
1007 LOG_ERROR("%s: failed to enable debug mode", target_name(target
));
1012 * The debug clock is inactive until the first command is sent.
1013 * If the target is stopped, we must first issue a reset before
1014 * attempting further communication. This also handles unpowered
1015 * targets, which will respond with all ones and appear active.
1017 if (esirisc_jtag_is_stopped(jtag_info
)) {
1018 LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target
));
1019 retval
= esirisc_debug_reset(target
);
1020 if (retval
!= ERROR_OK
)
1023 if (esirisc_jtag_is_stopped(jtag_info
)) {
1024 LOG_ERROR("%s: target unresponsive; giving up", target_name(target
));
1032 static int esirisc_debug_entry(struct target
*target
)
1034 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1035 struct breakpoint
*breakpoint
;
1039 esirisc_save_context(target
);
1041 if (esirisc_has_cache(esirisc
))
1042 esirisc_flush_caches(target
);
1044 if (target
->debug_reason
!= DBG_REASON_SINGLESTEP
) {
1045 esirisc_save_interrupts(target
);
1047 uint32_t eid
= buf_get_u32(esirisc
->eid
->value
, 0, esirisc
->eid
->size
);
1050 * InstBreakpoint exceptions are also raised when a core is
1051 * halted for debugging. The following is required to
1052 * determine if a breakpoint was encountered.
1054 case EID_INST_BREAKPOINT
:
1055 breakpoint
= breakpoint_find(target
,
1056 buf_get_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
));
1057 target
->debug_reason
= (breakpoint
) ?
1058 DBG_REASON_BREAKPOINT
: DBG_REASON_DBGRQ
;
1062 * eSi-RISC treats watchpoints similarly to breakpoints,
1063 * however GDB will not request to step over the current
1064 * instruction when a watchpoint fires. The following is
1065 * required to resume the target.
1067 case EID_DATA_BREAKPOINT
:
1068 esirisc_remove_watchpoints(target
);
1069 esirisc_debug_step(target
);
1070 esirisc_add_watchpoints(target
);
1071 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1075 target
->debug_reason
= DBG_REASON_DBGRQ
;
1082 static int esirisc_poll(struct target
*target
)
1084 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1085 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1088 retval
= esirisc_jtag_enable_debug(jtag_info
);
1089 if (retval
!= ERROR_OK
) {
1090 LOG_ERROR("%s: failed to poll target", target_name(target
));
1094 if (esirisc_jtag_is_stopped(jtag_info
)) {
1095 LOG_ERROR("%s: target has stopped; reset required", target_name(target
));
1096 target
->state
= TARGET_UNKNOWN
;
1097 return ERROR_TARGET_FAILURE
;
1100 if (esirisc_jtag_is_debug_active(jtag_info
)) {
1101 if (target
->state
== TARGET_RUNNING
|| target
->state
== TARGET_RESET
) {
1102 target
->state
= TARGET_HALTED
;
1104 retval
= esirisc_debug_entry(target
);
1105 if (retval
!= ERROR_OK
)
1108 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1111 } else if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_RESET
) {
1112 target
->state
= TARGET_RUNNING
;
1113 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1119 static int esirisc_assert_reset(struct target
*target
)
1121 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1122 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1127 if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1128 jtag_add_reset(1, 1);
1129 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) == 0)
1130 jtag_add_reset(0, 1);
1132 esirisc_remove_breakpoints(target
);
1133 esirisc_remove_watchpoints(target
);
1135 retval
= esirisc_jtag_assert_reset(jtag_info
);
1136 if (retval
!= ERROR_OK
) {
1137 LOG_ERROR("%s: failed to assert reset", target_name(target
));
1142 target
->state
= TARGET_RESET
;
1144 register_cache_invalidate(esirisc
->reg_cache
);
1149 static int esirisc_reset_entry(struct target
*target
)
1151 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1152 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1158 /* read exception table address */
1159 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETA
, &eta
);
1160 if (retval
!= ERROR_OK
) {
1161 LOG_ERROR("%s: failed to read Thread CSR: ETA", target_name(target
));
1165 /* read reset entry point */
1166 retval
= esirisc_jtag_read_word(jtag_info
, eta
+ ENTRY_RESET
, &epc
);
1167 if (retval
!= ERROR_OK
) {
1168 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR
, target_name(target
),
1169 (target_addr_t
)epc
);
1173 /* write reset entry point */
1174 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_EPC
, epc
);
1175 if (retval
!= ERROR_OK
) {
1176 LOG_ERROR("%s: failed to write Thread CSR: EPC", target_name(target
));
1183 static int esirisc_deassert_reset(struct target
*target
)
1185 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1186 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1191 if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1192 jtag_add_reset(0, 0);
1194 retval
= esirisc_debug_enable(target
);
1195 if (retval
!= ERROR_OK
)
1198 retval
= esirisc_debug_reset(target
);
1199 if (retval
!= ERROR_OK
)
1203 retval
= esirisc_jtag_deassert_reset(jtag_info
);
1204 if (retval
!= ERROR_OK
) {
1205 LOG_ERROR("%s: failed to deassert reset", target_name(target
));
1210 retval
= esirisc_wait_debug_active(esirisc
, RESET_TIMEOUT
);
1211 if (retval
!= ERROR_OK
) {
1212 LOG_ERROR("%s: reset timed out", target_name(target
));
1216 retval
= esirisc_reset_entry(target
);
1217 if (retval
!= ERROR_OK
)
1220 esirisc_add_breakpoints(target
);
1221 esirisc_add_watchpoints(target
);
1223 esirisc_restore_hwdc(target
);
1225 if (!target
->reset_halt
) {
1226 retval
= esirisc_jtag_continue(jtag_info
);
1227 if (retval
!= ERROR_OK
) {
1228 LOG_ERROR("%s: failed to resume target", target_name(target
));
1236 static int esirisc_arch_state(struct target
*target
)
1238 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1239 uint32_t epc
= buf_get_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
);
1240 uint32_t ecas
= buf_get_u32(esirisc
->ecas
->value
, 0, esirisc
->ecas
->size
);
1241 uint32_t eid
= buf_get_u32(esirisc
->eid
->value
, 0, esirisc
->eid
->size
);
1242 uint32_t ed
= buf_get_u32(esirisc
->ed
->value
, 0, esirisc
->ed
->size
);
1244 LOG_USER("target halted due to %s, exception: %s\n"
1245 "EPC: 0x%" PRIx32
", ECAS: 0x%" PRIx32
", EID: 0x%" PRIx32
", ED: 0x%" PRIx32
,
1246 debug_reason_name(target
), esirisc_exception_strings
[eid
], epc
, ecas
, eid
, ed
);
1251 static const char *esirisc_get_gdb_arch(const struct target
*target
)
1253 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1258 * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a
1259 * Harvard architecture. This option is not exposed in a CSR, which
1260 * requires additional configuration to properly interact with these
1261 * targets in GDB (also see: `esirisc cache_arch`).
1263 if (!esirisc
->gdb_arch
&& target_was_examined(target
))
1264 esirisc
->gdb_arch
= alloc_printf("esirisc:%d_bit_%d_reg_%s",
1265 esirisc
->num_bits
, esirisc
->num_regs
, esirisc_cache_arch_name(esirisc
));
1267 return esirisc
->gdb_arch
;
1270 static int esirisc_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
1271 int *reg_list_size
, enum target_register_class reg_class
)
1273 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1277 *reg_list_size
= ESIRISC_NUM_REGS
;
1279 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
1283 if (reg_class
== REG_CLASS_ALL
)
1284 for (int i
= 0; i
< *reg_list_size
; ++i
)
1285 (*reg_list
)[i
] = esirisc
->reg_cache
->reg_list
+ i
;
1287 for (int i
= 0; i
< esirisc
->num_regs
; ++i
)
1288 (*reg_list
)[i
] = esirisc
->reg_cache
->reg_list
+ i
;
1290 (*reg_list
)[ESIRISC_PC
] = esirisc
->reg_cache
->reg_list
+ ESIRISC_PC
;
1291 (*reg_list
)[ESIRISC_CAS
] = esirisc
->reg_cache
->reg_list
+ ESIRISC_CAS
;
1297 static int esirisc_read_reg(struct reg
*reg
)
1299 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1300 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1301 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1302 struct target
*target
= esirisc
->target
;
1307 int retval
= esirisc_jtag_read_reg(jtag_info
, reg
->number
, &data
);
1308 if (retval
!= ERROR_OK
) {
1309 LOG_ERROR("%s: failed to read register: %s", target_name(target
), reg
->name
);
1313 buf_set_u32(reg
->value
, 0, reg
->size
, data
);
1320 static int esirisc_write_reg(struct reg
*reg
)
1322 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1323 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1324 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1325 struct target
*target
= esirisc
->target
;
1326 uint32_t data
= buf_get_u32(reg
->value
, 0, reg
->size
);
1330 int retval
= esirisc_jtag_write_reg(jtag_info
, reg
->number
, data
);
1331 if (retval
!= ERROR_OK
) {
1332 LOG_ERROR("%s: failed to write register: %s", target_name(target
), reg
->name
);
1342 static int esirisc_read_csr(struct reg
*reg
)
1344 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1345 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1346 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1347 struct target
*target
= esirisc
->target
;
1352 int retval
= esirisc_jtag_read_csr(jtag_info
, reg_info
->bank
, reg_info
->csr
, &data
);
1353 if (retval
!= ERROR_OK
) {
1354 LOG_ERROR("%s: failed to read CSR: %s", target_name(target
), reg
->name
);
1358 buf_set_u32(reg
->value
, 0, reg
->size
, data
);
1365 static int esirisc_write_csr(struct reg
*reg
)
1367 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1368 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1369 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1370 struct target
*target
= esirisc
->target
;
1371 uint32_t data
= buf_get_u32(reg
->value
, 0, reg
->size
);
1375 int retval
= esirisc_jtag_write_csr(jtag_info
, reg_info
->bank
, reg_info
->csr
, data
);
1376 if (retval
!= ERROR_OK
) {
1377 LOG_ERROR("%s: failed to write CSR: %s", target_name(target
), reg
->name
);
1387 static int esirisc_get_reg(struct reg
*reg
)
1389 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1390 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1391 struct target
*target
= esirisc
->target
;
1395 if (target
->state
!= TARGET_HALTED
)
1396 return ERROR_TARGET_NOT_HALTED
;
1398 return reg_info
->read(reg
);
1401 static int esirisc_set_reg(struct reg
*reg
, uint8_t *buf
)
1403 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1404 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1405 struct target
*target
= esirisc
->target
;
1406 uint32_t value
= buf_get_u32(buf
, 0, reg
->size
);
1410 if (target
->state
!= TARGET_HALTED
)
1411 return ERROR_TARGET_NOT_HALTED
;
1413 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
1420 static const struct reg_arch_type esirisc_reg_type
= {
1421 .get
= esirisc_get_reg
,
1422 .set
= esirisc_set_reg
,
1425 static struct reg_cache
*esirisc_build_reg_cache(struct target
*target
)
1427 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1428 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1429 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
1430 struct reg
*reg_list
= calloc(ESIRISC_NUM_REGS
, sizeof(struct reg
));
1434 cache
->name
= "eSi-RISC registers";
1436 cache
->reg_list
= reg_list
;
1437 cache
->num_regs
= ESIRISC_NUM_REGS
;
1440 esirisc
->reg_cache
= cache
;
1441 esirisc
->epc
= reg_list
+ ESIRISC_EPC
;
1442 esirisc
->ecas
= reg_list
+ ESIRISC_ECAS
;
1443 esirisc
->eid
= reg_list
+ ESIRISC_EID
;
1444 esirisc
->ed
= reg_list
+ ESIRISC_ED
;
1446 for (int i
= 0; i
< esirisc
->num_regs
; ++i
) {
1447 struct reg
*reg
= reg_list
+ esirisc_regs
[i
].number
;
1448 struct esirisc_reg
*reg_info
= calloc(1, sizeof(struct esirisc_reg
));
1450 reg
->name
= esirisc_regs
[i
].name
;
1451 reg
->number
= esirisc_regs
[i
].number
;
1452 reg
->value
= calloc(1, DIV_ROUND_UP(esirisc
->num_bits
, 8));
1453 reg
->size
= esirisc
->num_bits
;
1454 reg
->reg_data_type
= calloc(1, sizeof(struct reg_data_type
));
1455 reg
->reg_data_type
->type
= esirisc_regs
[i
].type
;
1456 reg
->group
= esirisc_regs
[i
].group
;
1457 reg_info
->esirisc
= esirisc
;
1458 reg_info
->read
= esirisc_read_reg
;
1459 reg_info
->write
= esirisc_write_reg
;
1460 reg
->arch_info
= reg_info
;
1461 reg
->type
= &esirisc_reg_type
;
1465 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_csrs
); ++i
) {
1466 struct reg
*reg
= reg_list
+ esirisc_csrs
[i
].number
;
1467 struct esirisc_reg
*reg_info
= calloc(1, sizeof(struct esirisc_reg
));
1469 reg
->name
= esirisc_csrs
[i
].name
;
1470 reg
->number
= esirisc_csrs
[i
].number
;
1471 reg
->value
= calloc(1, DIV_ROUND_UP(esirisc
->num_bits
, 8));
1472 reg
->size
= esirisc
->num_bits
;
1473 reg
->reg_data_type
= calloc(1, sizeof(struct reg_data_type
));
1474 reg
->reg_data_type
->type
= esirisc_csrs
[i
].type
;
1475 reg
->group
= esirisc_csrs
[i
].group
;
1476 reg_info
->esirisc
= esirisc
;
1477 reg_info
->bank
= esirisc_csrs
[i
].bank
;
1478 reg_info
->csr
= esirisc_csrs
[i
].csr
;
1479 reg_info
->read
= esirisc_read_csr
;
1480 reg_info
->write
= esirisc_write_csr
;
1481 reg
->arch_info
= reg_info
;
1482 reg
->type
= &esirisc_reg_type
;
1489 static void esirisc_free_reg_cache(struct target
*target
)
1491 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1492 struct reg_cache
*cache
= esirisc
->reg_cache
;
1493 struct reg
*reg_list
= cache
->reg_list
;
1495 for (int i
= 0; i
< esirisc
->num_regs
; ++i
) {
1496 struct reg
*reg
= reg_list
+ esirisc_regs
[i
].number
;
1498 free(reg
->arch_info
);
1500 free(reg
->reg_data_type
);
1503 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_csrs
); ++i
) {
1504 struct reg
*reg
= reg_list
+ esirisc_csrs
[i
].number
;
1506 free(reg
->arch_info
);
1508 free(reg
->reg_data_type
);
1515 static int esirisc_identify(struct target
*target
)
1517 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1518 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1524 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_ARCH0
, &csr
);
1525 if (retval
!= ERROR_OK
) {
1526 LOG_ERROR("%s: failed to read Configuration CSR: ARCH0", target_name(target
));
1530 esirisc
->num_bits
= (csr
>> 0) & 0x3f; /* ARCH0.B */
1531 esirisc
->num_regs
= (csr
>> 10) & 0x3f; /* ARCH0.R */
1533 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_MEM
, &csr
);
1534 if (retval
!= ERROR_OK
) {
1535 LOG_ERROR("%s: failed to read Configuration CSR: MEM", target_name(target
));
1539 target
->endianness
= (csr
& 1<<0) ? /* MEM.E */
1540 TARGET_BIG_ENDIAN
: TARGET_LITTLE_ENDIAN
;
1542 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_IC
, &csr
);
1543 if (retval
!= ERROR_OK
) {
1544 LOG_ERROR("%s: failed to read Configuration CSR: IC", target_name(target
));
1548 esirisc
->has_icache
= !!(csr
& 1<<0); /* IC.E */
1550 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_DC
, &csr
);
1551 if (retval
!= ERROR_OK
) {
1552 LOG_ERROR("%s: failed to read Configuration CSR: DC", target_name(target
));
1556 esirisc
->has_dcache
= !!(csr
& 1<<0); /* DC.E */
1558 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_DBG
, &csr
);
1559 if (retval
!= ERROR_OK
) {
1560 LOG_ERROR("%s: failed to read Configuration CSR: DBG", target_name(target
));
1564 esirisc
->num_breakpoints
= (csr
>> 7) & 0xf; /* DBG.BP */
1565 esirisc
->num_watchpoints
= (csr
>> 12) & 0xf; /* DBG.WP */
1567 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_TRACE
, &csr
);
1568 if (retval
!= ERROR_OK
) {
1569 LOG_ERROR("%s: failed to read Configuration CSR: TRACE", target_name(target
));
1573 esirisc
->has_trace
= !!(csr
& 1<<0); /* TRACE.T */
1578 static int esirisc_target_create(struct target
*target
, Jim_Interp
*interp
)
1580 struct jtag_tap
*tap
= target
->tap
;
1581 struct esirisc_common
*esirisc
;
1586 if (tap
->ir_length
!= INSTR_LENGTH
) {
1587 LOG_ERROR("%s: invalid IR length; expected %d", target_name(target
),
1592 esirisc
= calloc(1, sizeof(struct esirisc_common
));
1596 esirisc
->target
= target
;
1597 esirisc
->jtag_info
.tap
= tap
;
1598 target
->arch_info
= esirisc
;
1603 static int esirisc_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
1605 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1607 /* trap reset, error, and debug exceptions */
1608 esirisc
->hwdc_save
= HWDC_R
| HWDC_E
| HWDC_D
;
1613 static void esirisc_deinit_target(struct target
*target
)
1615 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1617 if (!target_was_examined(target
))
1620 esirisc_free_reg_cache(target
);
1622 free(esirisc
->gdb_arch
);
1626 static int esirisc_examine(struct target
*target
)
1628 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1629 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1634 if (!target_was_examined(target
)) {
1635 retval
= esirisc_debug_enable(target
);
1636 if (retval
!= ERROR_OK
)
1640 * In order to identify the target we must first halt the core.
1641 * We quietly resume once identification has completed for those
1642 * targets that were running when target_examine was called.
1644 if (esirisc_jtag_is_debug_active(jtag_info
)) {
1645 if (target
->state
== TARGET_UNKNOWN
)
1646 target
->debug_reason
= DBG_REASON_DBGRQ
;
1648 target
->state
= TARGET_HALTED
;
1650 retval
= esirisc_jtag_break(jtag_info
);
1651 if (retval
!= ERROR_OK
) {
1652 LOG_ERROR("%s: failed to halt target", target_name(target
));
1656 target
->state
= TARGET_RUNNING
;
1659 retval
= esirisc_identify(target
);
1660 if (retval
!= ERROR_OK
) {
1661 LOG_ERROR("%s: failed to identify target", target_name(target
));
1665 esirisc_build_reg_cache(target
);
1667 esirisc_remove_breakpoints(target
);
1668 esirisc_remove_watchpoints(target
);
1670 esirisc_disable_step(target
);
1671 esirisc_restore_hwdc(target
);
1673 if (target
->state
== TARGET_HALTED
)
1674 esirisc_save_interrupts(target
);
1676 retval
= esirisc_jtag_continue(jtag_info
);
1677 if (retval
!= ERROR_OK
) {
1678 LOG_ERROR("%s: failed to resume target", target_name(target
));
1683 target_set_examined(target
);
1685 LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target
),
1686 esirisc
->num_bits
, esirisc
->num_regs
,
1687 target_endianness(target
),
1688 esirisc
->has_icache
? ", icache" : "",
1689 esirisc
->has_dcache
? ", dcache" : "");
1691 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints%s", target_name(target
),
1692 esirisc
->num_breakpoints
, esirisc
->num_watchpoints
,
1693 esirisc
->has_trace
? ", trace" : "");
1699 COMMAND_HANDLER(handle_esirisc_cache_arch_command
)
1701 struct target
*target
= get_current_target(CMD_CTX
);
1702 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1705 if (strcmp(*CMD_ARGV
, "harvard") == 0)
1706 esirisc
->cache_arch
= ESIRISC_CACHE_HARVARD
;
1707 else if (strcmp(*CMD_ARGV
, "von_neumann") == 0)
1708 esirisc
->cache_arch
= ESIRISC_CACHE_VON_NEUMANN
;
1710 LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV
);
1711 return ERROR_COMMAND_SYNTAX_ERROR
;
1715 command_print(CMD
, "esirisc cache_arch %s", esirisc_cache_arch_name(esirisc
));
1720 COMMAND_HANDLER(handle_esirisc_flush_caches_command
)
1722 struct target
*target
= get_current_target(CMD_CTX
);
1723 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1726 if (!esirisc_has_cache(esirisc
)) {
1727 LOG_ERROR("target does not support caching");
1731 retval
= esirisc_flush_caches(target
);
1733 command_print(CMD
, "cache flush %s",
1734 (retval
== ERROR_OK
) ? "successful" : "failed");
1739 static const struct {
1742 } esirisc_hwdc_masks
[] = {
1743 { "reset", HWDC_R
},
1744 { "interrupt", HWDC_I
},
1745 { "syscall", HWDC_S
},
1746 { "error", HWDC_E
},
1747 { "debug", HWDC_D
},
1750 static int esirisc_find_hwdc_mask(const char *name
)
1752 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_hwdc_masks
); ++i
)
1753 if (strcmp(esirisc_hwdc_masks
[i
].name
, name
) == 0)
1754 return esirisc_hwdc_masks
[i
].mask
;
1759 COMMAND_HANDLER(handle_esirisc_hwdc_command
)
1761 struct target
*target
= get_current_target(CMD_CTX
);
1762 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1765 if (strcmp(CMD_ARGV
[0], "all") == 0)
1766 esirisc
->hwdc_save
= HWDC_R
| HWDC_I
| HWDC_S
| HWDC_E
| HWDC_D
;
1768 esirisc
->hwdc_save
= 0;
1769 if (strcmp(CMD_ARGV
[0], "none") != 0) {
1770 while (CMD_ARGC
-- > 0) {
1771 int mask
= esirisc_find_hwdc_mask(CMD_ARGV
[CMD_ARGC
]);
1773 LOG_ERROR("invalid mask: %s", CMD_ARGV
[CMD_ARGC
]);
1774 return ERROR_COMMAND_SYNTAX_ERROR
;
1776 esirisc
->hwdc_save
|= mask
;
1782 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_hwdc_masks
); ++i
)
1783 command_print(CMD
, "%9s: %s", esirisc_hwdc_masks
[i
].name
,
1784 (esirisc
->hwdc_save
& esirisc_hwdc_masks
[i
].mask
) ? "enabled" : "disabled");
1789 static const struct command_registration esirisc_exec_command_handlers
[] = {
1791 .name
= "flush_caches",
1792 .handler
= handle_esirisc_flush_caches_command
,
1793 .mode
= COMMAND_EXEC
,
1794 .help
= "flush instruction and data caches",
1797 COMMAND_REGISTRATION_DONE
1800 static const struct command_registration esirisc_any_command_handlers
[] = {
1802 .name
= "cache_arch",
1803 .handler
= handle_esirisc_cache_arch_command
,
1804 .mode
= COMMAND_ANY
,
1805 .help
= "configure cache architecture",
1806 .usage
= "['harvard'|'von_neumann']",
1810 .handler
= handle_esirisc_hwdc_command
,
1811 .mode
= COMMAND_ANY
,
1812 .help
= "configure hardware debug control",
1813 .usage
= "['all'|'none'|mask ...]",
1816 .chain
= esirisc_exec_command_handlers
1819 .chain
= esirisc_trace_command_handlers
1821 COMMAND_REGISTRATION_DONE
1824 static const struct command_registration esirisc_command_handlers
[] = {
1827 .mode
= COMMAND_ANY
,
1828 .help
= "eSi-RISC command group",
1830 .chain
= esirisc_any_command_handlers
,
1832 COMMAND_REGISTRATION_DONE
1835 struct target_type esirisc_target
= {
1838 .poll
= esirisc_poll
,
1839 .arch_state
= esirisc_arch_state
,
1841 .halt
= esirisc_halt
,
1842 .resume
= esirisc_resume
,
1843 .step
= esirisc_step
,
1845 .assert_reset
= esirisc_assert_reset
,
1846 .deassert_reset
= esirisc_deassert_reset
,
1848 .get_gdb_arch
= esirisc_get_gdb_arch
,
1849 .get_gdb_reg_list
= esirisc_get_gdb_reg_list
,
1851 .read_memory
= esirisc_read_memory
,
1852 .write_memory
= esirisc_write_memory
,
1853 .checksum_memory
= esirisc_checksum_memory
,
1855 .add_breakpoint
= esirisc_add_breakpoint
,
1856 .remove_breakpoint
= esirisc_remove_breakpoint
,
1857 .add_watchpoint
= esirisc_add_watchpoint
,
1858 .remove_watchpoint
= esirisc_remove_watchpoint
,
1860 .commands
= esirisc_command_handlers
,
1862 .target_create
= esirisc_target_create
,
1863 .init_target
= esirisc_init_target
,
1864 .deinit_target
= esirisc_deinit_target
,
1865 .examine
= esirisc_examine
,