flash/stm32l4x: support STM32U53/U54x devices
[openocd.git] / src / target / arm7_9_common.h
blob92d0fd51a23a173fd84c2cf45eacd0b90a7fce82
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 * *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 * *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
12 * *
13 * Copyright (C) 2008 by Hongtao Zheng *
14 * hontor@126.com *
15 ***************************************************************************/
17 #ifndef OPENOCD_TARGET_ARM7_9_COMMON_H
18 #define OPENOCD_TARGET_ARM7_9_COMMON_H
20 #include "arm.h"
21 #include "arm_jtag.h"
23 #define ARM7_9_COMMON_MAGIC 0x0a790a79U /**< */
25 /**
26 * Structure for items that are common between both ARM7 and ARM9 targets.
28 struct arm7_9_common {
29 unsigned int common_magic;
31 struct arm arm;
33 struct arm_jtag jtag_info; /**< JTAG information for target */
34 struct reg_cache *eice_cache; /**< Embedded ICE register cache */
36 uint32_t arm_bkpt; /**< ARM breakpoint instruction */
37 uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
39 int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
40 int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
41 int breakpoint_count; /**< Current number of set breakpoints */
42 int wp_available; /**< Current number of available watchpoint units */
43 int wp_available_max; /**< Maximum number of available watchpoint units */
44 int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
45 int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
46 int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
47 int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
48 bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
49 bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
51 bool has_single_step;
52 bool has_monitor_mode;
53 bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
55 bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
57 bool fast_memory_access;
58 bool dcc_downloads;
60 struct working_area *dcc_working_area;
62 int (*examine_debug_reason)(struct target *target);
63 /**< Function for determining why debug state was entered */
65 void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
66 /**< Function for changing from Thumb to ARM mode */
68 void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
69 /**< Function for reading the core registers */
71 void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
72 void *buffer, int size);
73 void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
74 /**< Function for reading CPSR or SPSR */
76 void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
77 /**< Function for writing to CPSR or SPSR */
79 void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
80 /**< Function for writing an immediate value to CPSR or SPSR */
82 void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
84 void (*load_word_regs)(struct target *target, uint32_t mask);
85 void (*load_hword_reg)(struct target *target, int num);
86 void (*load_byte_reg)(struct target *target, int num);
88 void (*store_word_regs)(struct target *target, uint32_t mask);
89 void (*store_hword_reg)(struct target *target, int num);
90 void (*store_byte_reg)(struct target *target, int num);
92 void (*write_pc)(struct target *target, uint32_t pc);
93 /**< Function for writing to the program counter */
95 void (*branch_resume)(struct target *target);
96 void (*branch_resume_thumb)(struct target *target);
98 void (*enable_single_step)(struct target *target, uint32_t next_pc);
99 void (*disable_single_step)(struct target *target);
101 void (*set_special_dbgrq)(struct target *target);
102 /**< Function for setting DBGRQ if the normal way won't work */
104 int (*post_debug_entry)(struct target *target);
105 /**< Callback function called after entering debug mode */
107 void (*pre_restore_context)(struct target *target);
108 /**< Callback function called before restoring the processor context */
111 * Variant specific memory write function that does not dispatch to bulk_write_memory.
112 * Used as a fallback when bulk writes are unavailable, or for writing data needed to
113 * do the bulk writes.
115 int (*write_memory)(struct target *target, target_addr_t address,
116 uint32_t size, uint32_t count, const uint8_t *buffer);
118 * Write target memory in multiples of 4 bytes, optimized for
119 * writing large quantities of data.
121 int (*bulk_write_memory)(struct target *target, target_addr_t address,
122 uint32_t count, const uint8_t *buffer);
125 static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
127 return container_of(target->arch_info, struct arm7_9_common, arm);
130 static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
132 return arm7_9->common_magic == ARM7_9_COMMON_MAGIC;
135 extern const struct command_registration arm7_9_command_handlers[];
137 int arm7_9_poll(struct target *target);
139 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
141 int arm7_9_assert_reset(struct target *target);
142 int arm7_9_deassert_reset(struct target *target);
143 int arm7_9_reset_request_halt(struct target *target);
144 int arm7_9_early_halt(struct target *target);
145 int arm7_9_soft_reset_halt(struct target *target);
147 int arm7_9_halt(struct target *target);
148 int arm7_9_resume(struct target *target, int current, target_addr_t address,
149 int handle_breakpoints, int debug_execution);
150 int arm7_9_step(struct target *target, int current, target_addr_t address,
151 int handle_breakpoints);
152 int arm7_9_read_memory(struct target *target, target_addr_t address,
153 uint32_t size, uint32_t count, uint8_t *buffer);
154 int arm7_9_write_memory(struct target *target, target_addr_t address,
155 uint32_t size, uint32_t count, const uint8_t *buffer);
156 int arm7_9_write_memory_opt(struct target *target, target_addr_t address,
157 uint32_t size, uint32_t count, const uint8_t *buffer);
158 int arm7_9_write_memory_no_opt(struct target *target, uint32_t address,
159 uint32_t size, uint32_t count, const uint8_t *buffer);
160 int arm7_9_bulk_write_memory(struct target *target, target_addr_t address,
161 uint32_t count, const uint8_t *buffer);
163 int arm7_9_run_algorithm(struct target *target, int num_mem_params,
164 struct mem_param *mem_params, int num_reg_prams,
165 struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
167 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
168 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
169 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
170 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
172 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
173 void arm7_9_disable_eice_step(struct target *target);
175 int arm7_9_execute_sys_speed(struct target *target);
177 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
178 int arm7_9_examine(struct target *target);
179 void arm7_9_deinit(struct target *target);
180 int arm7_9_check_reset(struct target *target);
182 int arm7_9_endianness_callback(jtag_callback_data_t pu8_in,
183 jtag_callback_data_t i_size, jtag_callback_data_t i_be,
184 jtag_callback_data_t i_flip);
186 #endif /* OPENOCD_TARGET_ARM7_9_COMMON_H */