1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include "target/armv7m.h"
9 #include "rtos_standard_stackings.h"
10 #include "rtos_ecos_stackings.h"
12 /* For Cortex-M eCos applications the actual thread context register layout can
13 * be different between active threads of an application depending on whether
14 * the FPU is in use, configured for lazy FPU context saving, etc. */
16 /* Default fixed thread register context description used for older eCos
17 * application builds without the necessary symbolic information describing the
18 * actual configuration-dependent offsets. */
19 static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets
[ARMV7M_NUM_CORE_REGS
] = {
20 { ARMV7M_R0
, 0x0c, 32 }, /* r0 */
21 { ARMV7M_R1
, 0x10, 32 }, /* r1 */
22 { ARMV7M_R2
, 0x14, 32 }, /* r2 */
23 { ARMV7M_R3
, 0x18, 32 }, /* r3 */
24 { ARMV7M_R4
, 0x1c, 32 }, /* r4 */
25 { ARMV7M_R5
, 0x20, 32 }, /* r5 */
26 { ARMV7M_R6
, 0x24, 32 }, /* r6 */
27 { ARMV7M_R7
, 0x28, 32 }, /* r7 */
28 { ARMV7M_R8
, 0x2c, 32 }, /* r8 */
29 { ARMV7M_R9
, 0x30, 32 }, /* r9 */
30 { ARMV7M_R10
, 0x34, 32 }, /* r10 */
31 { ARMV7M_R11
, 0x38, 32 }, /* r11 */
32 { ARMV7M_R12
, 0x3c, 32 }, /* r12 */
33 { ARMV7M_R13
, -2, 32 }, /* sp */
34 { ARMV7M_R14
, -1, 32 }, /* lr */
35 { ARMV7M_PC
, 0x40, 32 }, /* pc */
36 { ARMV7M_XPSR
, -1, 32 }, /* xPSR */
39 const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking
= {
40 .stack_registers_size
= 0x44,
41 .stack_growth_direction
= -1,
42 .num_output_registers
= ARMV7M_NUM_CORE_REGS
,
43 .calculate_process_stack
= rtos_generic_stack_align8
,
44 .register_offsets
= rtos_ecos_cortex_m3_stack_offsets