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flash/nor/nrf5: handle ERROR_WAIT during nRF91 flash erase
[openocd.git] / src / flash / nor / tms470.c
blobe01d2df0a50122fc4b42fe26b6b884e087e29135
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2007,2008 by Christopher Kilgour *
5 * techie |_at_| whiterocker |_dot_| com *
6 ***************************************************************************/
7
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11
12 #include "imp.h"
13
14 /* ----------------------------------------------------------------------
15 * Internal Support, Helpers
16 * ---------------------------------------------------------------------- */
17
18 struct tms470_flash_bank {
19 unsigned ordinal;
20
21 /* device identification register */
22 uint32_t device_ident_reg;
23 uint32_t silicon_version;
24 uint32_t technology_family;
25 uint32_t rom_flash;
26 uint32_t part_number;
27 const char *part_name;
28
29 };
30
31 static const struct flash_sector tms470r1a256_sectors[] = {
32 {0x00000000, 0x00002000, -1, -1},
33 {0x00002000, 0x00002000, -1, -1},
34 {0x00004000, 0x00002000, -1, -1},
35 {0x00006000, 0x00002000, -1, -1},
36 {0x00008000, 0x00008000, -1, -1},
37 {0x00010000, 0x00008000, -1, -1},
38 {0x00018000, 0x00008000, -1, -1},
39 {0x00020000, 0x00008000, -1, -1},
40 {0x00028000, 0x00008000, -1, -1},
41 {0x00030000, 0x00008000, -1, -1},
42 {0x00038000, 0x00002000, -1, -1},
43 {0x0003A000, 0x00002000, -1, -1},
44 {0x0003C000, 0x00002000, -1, -1},
45 {0x0003E000, 0x00002000, -1, -1},
46 };
47
48 #define TMS470R1A256_NUM_SECTORS \
49 ARRAY_SIZE(tms470r1a256_sectors)
50
51 static const struct flash_sector tms470r1a288_bank0_sectors[] = {
52 {0x00000000, 0x00002000, -1, -1},
53 {0x00002000, 0x00002000, -1, -1},
54 {0x00004000, 0x00002000, -1, -1},
55 {0x00006000, 0x00002000, -1, -1},
56 };
57
58 #define TMS470R1A288_BANK0_NUM_SECTORS \
59 ARRAY_SIZE(tms470r1a288_bank0_sectors)
60
61 static const struct flash_sector tms470r1a288_bank1_sectors[] = {
62 {0x00040000, 0x00010000, -1, -1},
63 {0x00050000, 0x00010000, -1, -1},
64 {0x00060000, 0x00010000, -1, -1},
65 {0x00070000, 0x00010000, -1, -1},
66 };
67
68 #define TMS470R1A288_BANK1_NUM_SECTORS \
69 ARRAY_SIZE(tms470r1a288_bank1_sectors)
70
71 static const struct flash_sector tms470r1a384_bank0_sectors[] = {
72 {0x00000000, 0x00002000, -1, -1},
73 {0x00002000, 0x00002000, -1, -1},
74 {0x00004000, 0x00004000, -1, -1},
75 {0x00008000, 0x00004000, -1, -1},
76 {0x0000C000, 0x00004000, -1, -1},
77 {0x00010000, 0x00004000, -1, -1},
78 {0x00014000, 0x00004000, -1, -1},
79 {0x00018000, 0x00002000, -1, -1},
80 {0x0001C000, 0x00002000, -1, -1},
81 {0x0001E000, 0x00002000, -1, -1},
82 };
83
84 #define TMS470R1A384_BANK0_NUM_SECTORS \
85 ARRAY_SIZE(tms470r1a384_bank0_sectors)
86
87 static const struct flash_sector tms470r1a384_bank1_sectors[] = {
88 {0x00020000, 0x00008000, -1, -1},
89 {0x00028000, 0x00008000, -1, -1},
90 {0x00030000, 0x00008000, -1, -1},
91 {0x00038000, 0x00008000, -1, -1},
92 };
93
94 #define TMS470R1A384_BANK1_NUM_SECTORS \
95 ARRAY_SIZE(tms470r1a384_bank1_sectors)
96
97 static const struct flash_sector tms470r1a384_bank2_sectors[] = {
98 {0x00040000, 0x00008000, -1, -1},
99 {0x00048000, 0x00008000, -1, -1},
100 {0x00050000, 0x00008000, -1, -1},
101 {0x00058000, 0x00008000, -1, -1},
102 };
103
104 #define TMS470R1A384_BANK2_NUM_SECTORS \
105 ARRAY_SIZE(tms470r1a384_bank2_sectors)
106
107 /* ---------------------------------------------------------------------- */
108
109 static int tms470_read_part_info(struct flash_bank *bank)
110 {
111 struct tms470_flash_bank *tms470_info = bank->driver_priv;
112 struct target *target = bank->target;
113 uint32_t device_ident_reg;
114 uint32_t silicon_version;
115 uint32_t technology_family;
116 uint32_t rom_flash;
117 uint32_t part_number;
118 const char *part_name;
119
120 /* we shall not rely on the caller in this test, this function allocates memory,
121 thus and executing the code more than once may cause memory leak */
122 if (tms470_info->device_ident_reg)
123 return ERROR_OK;
124
125 /* read and parse the device identification register */
126 target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
127
128 LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
129
130 if ((device_ident_reg & 7) == 0) {
131 LOG_WARNING("Cannot identify target as a TMS470 family.");
132 return ERROR_FLASH_OPERATION_FAILED;
133 }
134
135 silicon_version = (device_ident_reg >> 12) & 0xF;
136 technology_family = (device_ident_reg >> 11) & 1;
137 rom_flash = (device_ident_reg >> 10) & 1;
138 part_number = (device_ident_reg >> 3) & 0x7f;
139
140 free(bank->sectors);
141 bank->sectors = NULL;
142 bank->num_sectors = 0;
143
144 /*
145 * If the part number is known, determine if the flash bank is valid
146 * based on the base address being within the known flash bank
147 * ranges. Then fixup/complete the remaining fields of the flash
148 * bank structure.
149 */
150 switch (part_number) {
151 case 0x0a:
152 part_name = "TMS470R1A256";
153
154 if (bank->base >= 0x00040000) {
155 LOG_ERROR("No %s flash bank contains base address "
156 TARGET_ADDR_FMT ".",
157 part_name,
158 bank->base);
159 return ERROR_FLASH_OPERATION_FAILED;
160 }
161 tms470_info->ordinal = 0;
162 bank->base = 0x00000000;
163 bank->size = 256 * 1024;
164 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
165 bank->sectors = malloc(sizeof(tms470r1a256_sectors));
166 if (!bank->sectors)
167 return ERROR_FLASH_OPERATION_FAILED;
168 (void)memcpy(bank->sectors, tms470r1a256_sectors, sizeof(tms470r1a256_sectors));
169 break;
170
171 case 0x2b:
172 part_name = "TMS470R1A288";
173
174 if (bank->base < 0x00008000) {
175 tms470_info->ordinal = 0;
176 bank->base = 0x00000000;
177 bank->size = 32 * 1024;
178 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
179 bank->sectors = malloc(sizeof(tms470r1a288_bank0_sectors));
180 if (!bank->sectors)
181 return ERROR_FLASH_OPERATION_FAILED;
182 (void)memcpy(bank->sectors, tms470r1a288_bank0_sectors,
183 sizeof(tms470r1a288_bank0_sectors));
184 } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) {
185 tms470_info->ordinal = 1;
186 bank->base = 0x00040000;
187 bank->size = 256 * 1024;
188 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
189 bank->sectors = malloc(sizeof(tms470r1a288_bank1_sectors));
190 if (!bank->sectors)
191 return ERROR_FLASH_OPERATION_FAILED;
192 (void)memcpy(bank->sectors, tms470r1a288_bank1_sectors,
193 sizeof(tms470r1a288_bank1_sectors));
194 } else {
195 LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
196 part_name, bank->base);
197 return ERROR_FLASH_OPERATION_FAILED;
198 }
199 break;
200
201 case 0x2d:
202 part_name = "TMS470R1A384";
203
204 if (bank->base < 0x00020000) {
205 tms470_info->ordinal = 0;
206 bank->base = 0x00000000;
207 bank->size = 128 * 1024;
208 bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS;
209 bank->sectors = malloc(sizeof(tms470r1a384_bank0_sectors));
210 if (!bank->sectors)
211 return ERROR_FLASH_OPERATION_FAILED;
212 (void)memcpy(bank->sectors, tms470r1a384_bank0_sectors,
213 sizeof(tms470r1a384_bank0_sectors));
214 } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) {
215 tms470_info->ordinal = 1;
216 bank->base = 0x00020000;
217 bank->size = 128 * 1024;
218 bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS;
219 bank->sectors = malloc(sizeof(tms470r1a384_bank1_sectors));
220 if (!bank->sectors)
221 return ERROR_FLASH_OPERATION_FAILED;
222 (void)memcpy(bank->sectors, tms470r1a384_bank1_sectors,
223 sizeof(tms470r1a384_bank1_sectors));
224 } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) {
225 tms470_info->ordinal = 2;
226 bank->base = 0x00040000;
227 bank->size = 128 * 1024;
228 bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS;
229 bank->sectors = malloc(sizeof(tms470r1a384_bank2_sectors));
230 if (!bank->sectors)
231 return ERROR_FLASH_OPERATION_FAILED;
232 (void)memcpy(bank->sectors, tms470r1a384_bank2_sectors,
233 sizeof(tms470r1a384_bank2_sectors));
234 } else {
235 LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
236 part_name, bank->base);
237 return ERROR_FLASH_OPERATION_FAILED;
238 }
239 break;
240
241 default:
242 LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.",
243 (unsigned)part_number);
244 return ERROR_FLASH_OPERATION_FAILED;
245 }
246
247 /* turn off memory selects */
248 target_write_u32(target, 0xFFFFFFE4, 0x00000000);
249 target_write_u32(target, 0xFFFFFFE0, 0x00000000);
250
251 LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
252 part_name,
253 (int)(silicon_version),
254 (technology_family ? "1.8v" : "3.3v"),
255 (rom_flash ? "rom" : "flash"));
256
257 tms470_info->device_ident_reg = device_ident_reg;
258 tms470_info->silicon_version = silicon_version;
259 tms470_info->technology_family = technology_family;
260 tms470_info->rom_flash = rom_flash;
261 tms470_info->part_number = part_number;
262 tms470_info->part_name = part_name;
263
264 /*
265 * Disable reset on address access violation.
266 */
267 target_write_u32(target, 0xFFFFFFE0, 0x00004007);
268
269 return ERROR_OK;
270 }
271
272 /* ---------------------------------------------------------------------- */
273
274 static uint32_t keys_set;
275 static uint32_t flash_keys[4];
276
277 COMMAND_HANDLER(tms470_handle_flash_keyset_command)
278 {
279 if (CMD_ARGC > 4)
280 return ERROR_COMMAND_SYNTAX_ERROR;
281 else if (CMD_ARGC == 4) {
282 int i;
283
284 for (i = 0; i < 4; i++) {
285 int start = (strncmp(CMD_ARGV[i], "0x", 2) == 0) ? 2 : 0;
286
287 if (sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i]) != 1) {
288 command_print(CMD, "could not process flash key %s",
289 CMD_ARGV[i]);
290 LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
291 return ERROR_COMMAND_SYNTAX_ERROR;
292 }
293 }
294
295 keys_set = 1;
296 } else if (CMD_ARGC != 0) {
297 command_print(CMD, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
298 return ERROR_COMMAND_SYNTAX_ERROR;
299 }
300
301 if (keys_set) {
302 command_print(CMD,
303 "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
304 flash_keys[0],
305 flash_keys[1],
306 flash_keys[2],
307 flash_keys[3]);
308 } else
309 command_print(CMD, "flash keys not set");
310
311 return ERROR_OK;
312 }
313
314 static const uint32_t flash_keys_all_ones[] = { 0xFFFFFFFF, 0xFFFFFFFF,
315 0xFFFFFFFF, 0xFFFFFFFF,};
316
317 static const uint32_t flash_keys_all_zeros[] = { 0x00000000, 0x00000000,
318 0x00000000, 0x00000000,};
319
320 static const uint32_t flash_keys_mix1[] = { 0xf0fff0ff, 0xf0fff0ff,
321 0xf0fff0ff, 0xf0fff0ff};
322
323 static const uint32_t flash_keys_mix2[] = { 0x0000ffff, 0x0000ffff,
324 0x0000ffff, 0x0000ffff};
325
326 /* ---------------------------------------------------------------------- */
327
328 static int osc_mhz = 12;
329
330 COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
331 {
332 if (CMD_ARGC > 1)
333 return ERROR_COMMAND_SYNTAX_ERROR;
334 else if (CMD_ARGC == 1)
335 sscanf(CMD_ARGV[0], "%d", &osc_mhz);
336
337 if (osc_mhz <= 0) {
338 LOG_ERROR("osc_megahertz must be positive and non-zero!");
339 command_print(CMD, "osc_megahertz must be positive and non-zero!");
340 osc_mhz = 12;
341 return ERROR_COMMAND_SYNTAX_ERROR;
342 }
343
344 command_print(CMD, "osc_megahertz=%d", osc_mhz);
345
346 return ERROR_OK;
347 }
348
349 /* ---------------------------------------------------------------------- */
350
351 static int plldis;
352
353 COMMAND_HANDLER(tms470_handle_plldis_command)
354 {
355 if (CMD_ARGC > 1)
356 return ERROR_COMMAND_SYNTAX_ERROR;
357 else if (CMD_ARGC == 1) {
358 sscanf(CMD_ARGV[0], "%d", &plldis);
359 plldis = plldis ? 1 : 0;
360 }
361
362 command_print(CMD, "plldis=%d", plldis);
363
364 return ERROR_OK;
365 }
366
367 /* ---------------------------------------------------------------------- */
368
369 static int tms470_check_flash_unlocked(struct target *target)
370 {
371 uint32_t fmbbusy;
372
373 target_read_u32(target, 0xFFE89C08, &fmbbusy);
374 LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32 " -> %s",
375 fmbbusy,
376 fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
377 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
378 }
379
380 /* ---------------------------------------------------------------------- */
381
382 static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
383 {
384 uint32_t glbctrl, fmmstat;
385 int retval = ERROR_FLASH_OPERATION_FAILED;
386
387 /* set GLBCTRL.4 */
388 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
389 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
390
391 /* only perform the key match when 3VSTAT is clear */
392 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
393 if (!(fmmstat & 0x08)) {
394 unsigned i;
395 uint32_t fmbptr, fmbac2, orig_fmregopt;
396
397 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
398
399 /* wait for pump ready */
400 do {
401 target_read_u32(target, 0xFFE8A814, &fmbptr);
402 alive_sleep(1);
403 } while (!(fmbptr & 0x0200));
404
405 /* force max wait states */
406 target_read_u32(target, 0xFFE88004, &fmbac2);
407 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
408
409 /* save current access mode, force normal read mode */
410 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
411 target_write_u32(target, 0xFFE89C00, 0x00);
412
413 for (i = 0; i < 4; i++) {
414 uint32_t tmp;
415
416 /* There is no point displaying the value of tmp, it is
417 * filtered by the chip. The purpose of this read is to
418 * prime the unlocking logic rather than read out the value.
419 */
420 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
421
422 LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
423 target_write_u32(target, 0xFFE89C0C, key_set[i]);
424 }
425
426 if (tms470_check_flash_unlocked(target) == ERROR_OK) {
427 /*
428 * There seems to be a side-effect of reading the FMPKEY
429 * register in that it re-enables the protection. So we
430 * re-enable it.
431 */
432 for (i = 0; i < 4; i++) {
433 uint32_t tmp;
434
435 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
436 target_write_u32(target, 0xFFE89C0C, key_set[i]);
437 }
438 retval = ERROR_OK;
439 }
440
441 /* restore settings */
442 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
443 target_write_u32(target, 0xFFE88004, fmbac2);
444 }
445
446 /* clear config bit */
447 target_write_u32(target, 0xFFFFFFDC, glbctrl);
448
449 return retval;
450 }
451
452 /* ---------------------------------------------------------------------- */
453
454 static int tms470_unlock_flash(struct flash_bank *bank)
455 {
456 struct target *target = bank->target;
457 const uint32_t *p_key_sets[5];
458 unsigned i, key_set_count;
459
460 if (keys_set) {
461 key_set_count = 5;
462 p_key_sets[0] = flash_keys;
463 p_key_sets[1] = flash_keys_all_ones;
464 p_key_sets[2] = flash_keys_all_zeros;
465 p_key_sets[3] = flash_keys_mix1;
466 p_key_sets[4] = flash_keys_mix2;
467 } else {
468 key_set_count = 4;
469 p_key_sets[0] = flash_keys_all_ones;
470 p_key_sets[1] = flash_keys_all_zeros;
471 p_key_sets[2] = flash_keys_mix1;
472 p_key_sets[3] = flash_keys_mix2;
473 }
474
475 for (i = 0; i < key_set_count; i++) {
476 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK) {
477 LOG_INFO("tms470 flash is unlocked");
478 return ERROR_OK;
479 }
480 }
481
482 LOG_WARNING("tms470 could not unlock flash memory protection level 2");
483 return ERROR_FLASH_OPERATION_FAILED;
484 }
485
486 /* ---------------------------------------------------------------------- */
487
488 static int tms470_flash_initialize_internal_state_machine(struct flash_bank *bank)
489 {
490 uint32_t fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
491 struct target *target = bank->target;
492 struct tms470_flash_bank *tms470_info = bank->driver_priv;
493 int result = ERROR_OK;
494
495 /*
496 * Select the desired bank to be programmed by writing BANK[2:0] of
497 * FMMAC2.
498 */
499 target_read_u32(target, 0xFFE8BC04, &fmmac2);
500 fmmac2 &= ~0x0007;
501 fmmac2 |= (tms470_info->ordinal & 7);
502 target_write_u32(target, 0xFFE8BC04, fmmac2);
503 LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
504
505 /*
506 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
507 */
508 target_read_u32(target, 0xFFE8BC00, &fmmac1);
509 fmmac1 |= 0x8000;
510 target_write_u32(target, 0xFFE8BC00, fmmac1);
511 LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
512
513 /*
514 * FMTCREG = 0x2fc0;
515 */
516 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
517 LOG_DEBUG("set fmtcreg = 0x2fc0");
518
519 /*
520 * MAXPP = 50
521 */
522 target_write_u32(target, 0xFFE8A07C, 50);
523 LOG_DEBUG("set fmmaxpp = 50");
524
525 /*
526 * MAXCP = 0xf000 + 2000
527 */
528 target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
529 LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
530
531 /*
532 * configure VHV
533 */
534 target_read_u32(target, 0xFFE8A080, &fmmaxep);
535 if (fmmaxep == 0xf000) {
536 fmmaxep = 0xf000 + 4095;
537 target_write_u32(target, 0xFFE8A80C, 0x9964);
538 LOG_DEBUG("set fmptr3 = 0x9964");
539 } else {
540 fmmaxep = 0xa000 + 4095;
541 target_write_u32(target, 0xFFE8A80C, 0x9b64);
542 LOG_DEBUG("set fmptr3 = 0x9b64");
543 }
544 target_write_u32(target, 0xFFE8A080, fmmaxep);
545 LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
546
547 /*
548 * FMPTR4 = 0xa000
549 */
550 target_write_u32(target, 0xFFE8A810, 0xa000);
551 LOG_DEBUG("set fmptr4 = 0xa000");
552
553 /*
554 * FMPESETUP, delay parameter selected based on clock frequency.
555 *
556 * According to the TI App Note SPNU257 and flashing code, delay is
557 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
558 * clock is usually derived from the ZPLL module, and selected by
559 * the plldis global.
560 */
561 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
562 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7));
563 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
564 target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
565 LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
566
567 /*
568 * FMPVEVACCESS, based on delay.
569 */
570 k = delay | (delay << 8);
571 target_write_u32(target, 0xFFE8A05C, k);
572 LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
573
574 /*
575 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
576 */
577 k <<= 1;
578 target_write_u32(target, 0xFFE8A034, k);
579 LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
580 target_write_u32(target, 0xFFE8A040, k);
581 LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
582 target_write_u32(target, 0xFFE8A024, k);
583 LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
584
585 /*
586 * FMCVACCESS, based on delay.
587 */
588 k = delay * 16;
589 target_write_u32(target, 0xFFE8A060, k);
590 LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
591
592 /*
593 * FMCSETUP, based on delay.
594 */
595 k = 0x3000 | delay * 20;
596 target_write_u32(target, 0xFFE8A020, k);
597 LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
598
599 /*
600 * FMEHOLD, based on delay.
601 */
602 k = (delay * 20) << 2;
603 target_write_u32(target, 0xFFE8A038, k);
604 LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
605
606 /*
607 * PWIDTH, CWIDTH, EWIDTH, based on delay.
608 */
609 target_write_u32(target, 0xFFE8A050, delay * 8);
610 LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
611 target_write_u32(target, 0xFFE8A058, delay * 1000);
612 LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
613 target_write_u32(target, 0xFFE8A054, delay * 5400);
614 LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
615
616 return result;
617 }
618
619 /* ---------------------------------------------------------------------- */
620
621 static int tms470_flash_status(struct flash_bank *bank)
622 {
623 struct target *target = bank->target;
624 int result = ERROR_OK;
625 uint32_t fmmstat;
626
627 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
628 LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
629
630 if (fmmstat & 0x0080) {
631 LOG_WARNING("tms470 flash command: erase still active after busy clear.");
632 result = ERROR_FLASH_OPERATION_FAILED;
633 }
634
635 if (fmmstat & 0x0040) {
636 LOG_WARNING("tms470 flash command: program still active after busy clear.");
637 result = ERROR_FLASH_OPERATION_FAILED;
638 }
639
640 if (fmmstat & 0x0020) {
641 LOG_WARNING("tms470 flash command: invalid data command.");
642 result = ERROR_FLASH_OPERATION_FAILED;
643 }
644
645 if (fmmstat & 0x0010) {
646 LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
647 result = ERROR_FLASH_OPERATION_FAILED;
648 }
649
650 if (fmmstat & 0x0008) {
651 LOG_WARNING("tms470 flash command: voltage instability detected.");
652 result = ERROR_FLASH_OPERATION_FAILED;
653 }
654
655 if (fmmstat & 0x0006) {
656 LOG_WARNING("tms470 flash command: command suspend detected.");
657 result = ERROR_FLASH_OPERATION_FAILED;
658 }
659
660 if (fmmstat & 0x0001) {
661 LOG_WARNING("tms470 flash command: sector was locked.");
662 result = ERROR_FLASH_OPERATION_FAILED;
663 }
664
665 return result;
666 }
667
668 /* ---------------------------------------------------------------------- */
669
670 static int tms470_erase_sector(struct flash_bank *bank, int sector)
671 {
672 uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
673 struct target *target = bank->target;
674 uint32_t flash_addr = bank->base + bank->sectors[sector].offset;
675 int result = ERROR_OK;
676
677 /*
678 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
679 * module) to enable writing to the flash registers }.
680 */
681 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
682 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
683 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
684
685 /* Force normal read mode. */
686 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
687 target_write_u32(target, 0xFFE89C00, 0);
688 LOG_DEBUG("set fmregopt = 0x%08x", 0);
689
690 (void)tms470_flash_initialize_internal_state_machine(bank);
691
692 /*
693 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
694 * protection for the particular sector to be erased/written.
695 */
696 assert(sector >= 0);
697 if (sector < 16) {
698 target_read_u32(target, 0xFFE88008, &fmbsea);
699 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
700 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
701 } else {
702 target_read_u32(target, 0xFFE8800C, &fmbseb);
703 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
704 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
705 }
706 bank->sectors[sector].is_protected = 0;
707
708 /*
709 * clear status register, sent erase command, kickoff erase
710 */
711 target_write_u16(target, flash_addr, 0x0040);
712 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flash_addr);
713 target_write_u16(target, flash_addr, 0x0020);
714 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flash_addr);
715 target_write_u16(target, flash_addr, 0xffff);
716 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flash_addr);
717
718 /*
719 * Monitor FMMSTAT, busy until clear, then check and other flags for
720 * ultimate result of the operation.
721 */
722 do {
723 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
724 if (fmmstat & 0x0100)
725 alive_sleep(1);
726 } while (fmmstat & 0x0100);
727
728 result = tms470_flash_status(bank);
729
730 if (sector < 16) {
731 target_write_u32(target, 0xFFE88008, fmbsea);
732 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
733 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
734 } else {
735 target_write_u32(target, 0xFFE8800C, fmbseb);
736 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
737 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
738 }
739 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
740 LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
741 target_write_u32(target, 0xFFFFFFDC, glbctrl);
742 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
743
744 return result;
745 }
746
747 /*----------------------------------------------------------------------
748 * Implementation of Flash Driver Interfaces
749 *---------------------------------------------------------------------- */
750
751 static const struct command_registration tms470_any_command_handlers[] = {
752 {
753 .name = "flash_keyset",
754 .usage = "<key0> <key1> <key2> <key3>",
755 .handler = tms470_handle_flash_keyset_command,
756 .mode = COMMAND_ANY,
757 .help = "tms470 flash_keyset <key0> <key1> <key2> <key3>",
758 },
759 {
760 .name = "osc_megahertz",
761 .usage = "<MHz>",
762 .handler = tms470_handle_osc_megahertz_command,
763 .mode = COMMAND_ANY,
764 .help = "tms470 osc_megahertz <MHz>",
765 },
766 {
767 .name = "plldis",
768 .usage = "<0 | 1>",
769 .handler = tms470_handle_plldis_command,
770 .mode = COMMAND_ANY,
771 .help = "tms470 plldis <0/1>",
772 },
773 COMMAND_REGISTRATION_DONE
774 };
775 static const struct command_registration tms470_command_handlers[] = {
776 {
777 .name = "tms470",
778 .mode = COMMAND_ANY,
779 .help = "TI tms470 flash command group",
780 .usage = "",
781 .chain = tms470_any_command_handlers,
782 },
783 COMMAND_REGISTRATION_DONE
784 };
785
786 /* ---------------------------------------------------------------------- */
787
788 static int tms470_erase(struct flash_bank *bank, unsigned int first,
789 unsigned int last)
790 {
791 struct tms470_flash_bank *tms470_info = bank->driver_priv;
792 int result = ERROR_OK;
793
794 if (bank->target->state != TARGET_HALTED) {
795 LOG_ERROR("Target not halted");
796 return ERROR_TARGET_NOT_HALTED;
797 }
798
799 tms470_read_part_info(bank);
800
801 if ((first >= bank->num_sectors) || (last >= bank->num_sectors) ||
802 (first > last)) {
803 LOG_ERROR("Sector range %u to %u invalid.", first, last);
804 return ERROR_FLASH_SECTOR_INVALID;
805 }
806
807 result = tms470_unlock_flash(bank);
808 if (result != ERROR_OK)
809 return result;
810
811 for (unsigned int sector = first; sector <= last; sector++) {
812 LOG_INFO("Erasing tms470 bank %u sector %u...", tms470_info->ordinal, sector);
813
814 result = tms470_erase_sector(bank, sector);
815
816 if (result != ERROR_OK) {
817 LOG_ERROR("tms470 could not erase flash sector.");
818 break;
819 } else
820 LOG_INFO("sector erased successfully.");
821 }
822
823 return result;
824 }
825
826 /* ---------------------------------------------------------------------- */
827
828 static int tms470_protect(struct flash_bank *bank, int set, unsigned int first,
829 unsigned int last)
830 {
831 struct tms470_flash_bank *tms470_info = bank->driver_priv;
832 struct target *target = bank->target;
833 uint32_t fmmac2, fmbsea, fmbseb;
834
835 if (target->state != TARGET_HALTED) {
836 LOG_ERROR("Target not halted");
837 return ERROR_TARGET_NOT_HALTED;
838 }
839
840 tms470_read_part_info(bank);
841
842 if ((first >= bank->num_sectors) || (last >= bank->num_sectors) ||
843 (first > last)) {
844 LOG_ERROR("Sector range %u to %u invalid.", first, last);
845 return ERROR_FLASH_SECTOR_INVALID;
846 }
847
848 /* enable the appropriate bank */
849 target_read_u32(target, 0xFFE8BC04, &fmmac2);
850 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
851
852 /* get the original sector protection flags for this bank */
853 target_read_u32(target, 0xFFE88008, &fmbsea);
854 target_read_u32(target, 0xFFE8800C, &fmbseb);
855
856 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
857 if (sector < 16) {
858 fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
859 bank->sectors[sector].is_protected = set ? 1 : 0;
860 } else {
861 fmbseb = set ? fmbseb &
862 ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
863 bank->sectors[sector].is_protected = set ? 1 : 0;
864 }
865 }
866
867 /* update the protection bits */
868 target_write_u32(target, 0xFFE88008, fmbsea);
869 target_write_u32(target, 0xFFE8800C, fmbseb);
870
871 return ERROR_OK;
872 }
873
874 /* ---------------------------------------------------------------------- */
875
876 static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
877 {
878 struct target *target = bank->target;
879 uint32_t glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
880 int result = ERROR_OK;
881 uint32_t i;
882
883 if (target->state != TARGET_HALTED) {
884 LOG_ERROR("Target not halted");
885 return ERROR_TARGET_NOT_HALTED;
886 }
887
888 tms470_read_part_info(bank);
889
890 LOG_INFO("Writing %" PRIu32 " bytes starting at " TARGET_ADDR_FMT,
891 count, bank->base + offset);
892
893 /* set GLBCTRL.4 */
894 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
895 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
896
897 (void)tms470_flash_initialize_internal_state_machine(bank);
898
899 /* force max wait states */
900 target_read_u32(target, 0xFFE88004, &fmbac2);
901 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
902
903 /* save current access mode, force normal read mode */
904 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
905 target_write_u32(target, 0xFFE89C00, 0x00);
906
907 /*
908 * Disable Level 1 protection for all sectors to be erased/written.
909 */
910 target_read_u32(target, 0xFFE88008, &fmbsea);
911 target_write_u32(target, 0xFFE88008, 0xffff);
912 target_read_u32(target, 0xFFE8800C, &fmbseb);
913 target_write_u32(target, 0xFFE8800C, 0xffff);
914
915 /* read MAXPP */
916 target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
917
918 for (i = 0; i < count; i += 2) {
919 uint32_t addr = bank->base + offset + i;
920 uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
921
922 if (word != 0xffff) {
923 LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
924
925 /* clear status register */
926 target_write_u16(target, addr, 0x0040);
927 /* program flash command */
928 target_write_u16(target, addr, 0x0010);
929 /* burn the 16-bit word (big-endian) */
930 target_write_u16(target, addr, word);
931
932 /*
933 * Monitor FMMSTAT, busy until clear, then check and other flags
934 * for ultimate result of the operation.
935 */
936 do {
937 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
938 if (fmmstat & 0x0100)
939 alive_sleep(1);
940 } while (fmmstat & 0x0100);
941
942 if (fmmstat & 0x3ff) {
943 LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
944 LOG_ERROR(
945 "Could not program word 0x%04x at address 0x%08" PRIx32 ".",
946 word,
947 addr);
948 result = ERROR_FLASH_OPERATION_FAILED;
949 break;
950 }
951 } else
952 LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
953 }
954
955 /* restore */
956 target_write_u32(target, 0xFFE88008, fmbsea);
957 target_write_u32(target, 0xFFE8800C, fmbseb);
958 target_write_u32(target, 0xFFE88004, fmbac2);
959 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
960 target_write_u32(target, 0xFFFFFFDC, glbctrl);
961
962 return result;
963 }
964
965 /* ---------------------------------------------------------------------- */
966
967 static int tms470_probe(struct flash_bank *bank)
968 {
969 if (bank->target->state != TARGET_HALTED) {
970 LOG_WARNING("Cannot communicate... target not halted.");
971 return ERROR_TARGET_NOT_HALTED;
972 }
973
974 return tms470_read_part_info(bank);
975 }
976
977 static int tms470_auto_probe(struct flash_bank *bank)
978 {
979 struct tms470_flash_bank *tms470_info = bank->driver_priv;
980
981 if (tms470_info->device_ident_reg)
982 return ERROR_OK;
983 return tms470_probe(bank);
984 }
985
986 /* ---------------------------------------------------------------------- */
987
988 static int tms470_erase_check(struct flash_bank *bank)
989 {
990 struct target *target = bank->target;
991 struct tms470_flash_bank *tms470_info = bank->driver_priv;
992 int result = ERROR_OK;
993 uint32_t fmmac2, fmbac2, glbctrl, orig_fmregopt;
994 static uint8_t buffer[64 * 1024];
995
996 if (target->state != TARGET_HALTED) {
997 LOG_ERROR("Target not halted");
998 return ERROR_TARGET_NOT_HALTED;
999 }
1000
1001 if (!tms470_info->device_ident_reg)
1002 tms470_read_part_info(bank);
1003
1004 /* set GLBCTRL.4 */
1005 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1006 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1007
1008 /* save current access mode, force normal read mode */
1009 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1010 target_write_u32(target, 0xFFE89C00, 0x00);
1011
1012 /* enable the appropriate bank */
1013 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1014 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1015
1016 /* TCR = 0 */
1017 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1018
1019 /* clear TEZ in fmbrdy */
1020 target_write_u32(target, 0xFFE88010, 0x0b);
1021
1022 /* save current wait states, force max */
1023 target_read_u32(target, 0xFFE88004, &fmbac2);
1024 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1025
1026 /*
1027 * The TI primitives inspect the flash memory by reading one 32-bit
1028 * word at a time. Here we read an entire sector and inspect it in
1029 * an attempt to reduce the JTAG overhead.
1030 */
1031 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1032 uint32_t i, addr = bank->base + bank->sectors[sector].offset;
1033
1034 LOG_INFO("checking flash bank %u sector %u", tms470_info->ordinal, sector);
1035
1036 target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1037
1038 bank->sectors[sector].is_erased = 1;
1039 for (i = 0; i < bank->sectors[sector].size; i++) {
1040 if (buffer[i] != 0xff) {
1041 bank->sectors[sector].is_erased = 0;
1042 break;
1043 }
1044 }
1045 if (bank->sectors[sector].is_erased != 1) {
1046 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1047 break;
1048 } else
1049 LOG_INFO("sector erased");
1050 }
1051
1052 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1053 target_write_u32(target, 0xFFE88010, 0x0f);
1054 target_write_u32(target, 0xFFE88004, fmbac2);
1055 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1056 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1057
1058 return result;
1059 }
1060
1061 /* ---------------------------------------------------------------------- */
1062
1063 static int tms470_protect_check(struct flash_bank *bank)
1064 {
1065 struct target *target = bank->target;
1066 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1067 int result = ERROR_OK;
1068 uint32_t fmmac2, fmbsea, fmbseb;
1069
1070 if (target->state != TARGET_HALTED) {
1071 LOG_ERROR("Target not halted");
1072 return ERROR_TARGET_NOT_HALTED;
1073 }
1074
1075 if (!tms470_info->device_ident_reg)
1076 tms470_read_part_info(bank);
1077
1078 /* enable the appropriate bank */
1079 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1080 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1081
1082 target_read_u32(target, 0xFFE88008, &fmbsea);
1083 target_read_u32(target, 0xFFE8800C, &fmbseb);
1084
1085 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1086 int protected;
1087
1088 if (sector < 16) {
1089 protected = fmbsea & (1 << sector) ? 0 : 1;
1090 bank->sectors[sector].is_protected = protected;
1091 } else {
1092 protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1093 bank->sectors[sector].is_protected = protected;
1094 }
1095
1096 LOG_DEBUG("bank %u sector %u is %s",
1097 tms470_info->ordinal,
1098 sector,
1099 protected ? "protected" : "not protected");
1100 }
1101
1102 return result;
1103 }
1104
1105 /* ---------------------------------------------------------------------- */
1106
1107 static int get_tms470_info(struct flash_bank *bank, struct command_invocation *cmd)
1108 {
1109 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1110
1111 if (!tms470_info->device_ident_reg)
1112 tms470_read_part_info(bank);
1113
1114 if (!tms470_info->device_ident_reg) {
1115 command_print_sameline(cmd, "Cannot identify target as a TMS470\n");
1116 return ERROR_FLASH_OPERATION_FAILED;
1117 }
1118
1119 command_print_sameline(cmd, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
1120 command_print_sameline(cmd, "Flash protection level 2 is %s\n",
1121 tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1122
1123 return ERROR_OK;
1124 }
1125
1126 /* ---------------------------------------------------------------------- */
1127
1128 /*
1129 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1130 * [options...]
1131 */
1132
1133 FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
1134 {
1135 bank->driver_priv = malloc(sizeof(struct tms470_flash_bank));
1136
1137 if (!bank->driver_priv)
1138 return ERROR_FLASH_OPERATION_FAILED;
1139
1140 (void)memset(bank->driver_priv, 0, sizeof(struct tms470_flash_bank));
1141
1142 return ERROR_OK;
1143 }
1144
1145 const struct flash_driver tms470_flash = {
1146 .name = "tms470",
1147 .commands = tms470_command_handlers,
1148 .flash_bank_command = tms470_flash_bank_command,
1149 .erase = tms470_erase,
1150 .protect = tms470_protect,
1151 .write = tms470_write,
1152 .read = default_flash_read,
1153 .probe = tms470_probe,
1154 .auto_probe = tms470_auto_probe,
1155 .erase_check = tms470_erase_check,
1156 .protect_check = tms470_protect_check,
1157 .info = get_tms470_info,
1158 .free_driver_priv = default_flash_free_driver_priv,
1159 };
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