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target: Do not use LOG_USER() for error messages
[openocd.git] / src / flash / nor / stm32f1x.c
blob5a3c2da663fcf0f1136b0385ebcdaf7ce1c02c44
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 * *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
9 * *
10 * Copyright (C) 2011 by Andreas Fritiofson *
11 * andreas.fritiofson@gmail.com *
12 ***************************************************************************/
13
14 #ifdef HAVE_CONFIG_H
15 #include "config.h"
16 #endif
17
18 #include <string.h>
19
20 #include "imp.h"
21 #include <helper/binarybuffer.h>
22 #include <target/algorithm.h>
23 #include <target/cortex_m.h>
24
25 /* stm32x register locations */
26
27 #define FLASH_REG_BASE_B0 0x40022000
28 #define FLASH_REG_BASE_B1 0x40022040
29
30 #define STM32_FLASH_ACR 0x00
31 #define STM32_FLASH_KEYR 0x04
32 #define STM32_FLASH_OPTKEYR 0x08
33 #define STM32_FLASH_SR 0x0C
34 #define STM32_FLASH_CR 0x10
35 #define STM32_FLASH_AR 0x14
36 #define STM32_FLASH_OBR 0x1C
37 #define STM32_FLASH_WRPR 0x20
38
39 /* TODO: Check if code using these really should be hard coded to bank 0.
40 * There are valid cases, on dual flash devices the protection of the
41 * second bank is done on the bank0 reg's. */
42 #define STM32_FLASH_ACR_B0 0x40022000
43 #define STM32_FLASH_KEYR_B0 0x40022004
44 #define STM32_FLASH_OPTKEYR_B0 0x40022008
45 #define STM32_FLASH_SR_B0 0x4002200C
46 #define STM32_FLASH_CR_B0 0x40022010
47 #define STM32_FLASH_AR_B0 0x40022014
48 #define STM32_FLASH_OBR_B0 0x4002201C
49 #define STM32_FLASH_WRPR_B0 0x40022020
50
51 /* option byte location */
52
53 #define STM32_OB_RDP 0x1FFFF800
54 #define STM32_OB_USER 0x1FFFF802
55 #define STM32_OB_DATA0 0x1FFFF804
56 #define STM32_OB_DATA1 0x1FFFF806
57 #define STM32_OB_WRP0 0x1FFFF808
58 #define STM32_OB_WRP1 0x1FFFF80A
59 #define STM32_OB_WRP2 0x1FFFF80C
60 #define STM32_OB_WRP3 0x1FFFF80E
61
62 /* FLASH_CR register bits */
63
64 #define FLASH_PG (1 << 0)
65 #define FLASH_PER (1 << 1)
66 #define FLASH_MER (1 << 2)
67 #define FLASH_OPTPG (1 << 4)
68 #define FLASH_OPTER (1 << 5)
69 #define FLASH_STRT (1 << 6)
70 #define FLASH_LOCK (1 << 7)
71 #define FLASH_OPTWRE (1 << 9)
72 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
73
74 /* FLASH_SR register bits */
75
76 #define FLASH_BSY (1 << 0)
77 #define FLASH_PGERR (1 << 2)
78 #define FLASH_WRPRTERR (1 << 4)
79 #define FLASH_EOP (1 << 5)
80
81 /* STM32_FLASH_OBR bit definitions (reading) */
82
83 #define OPT_ERROR 0
84 #define OPT_READOUT 1
85 #define OPT_RDWDGSW 2
86 #define OPT_RDRSTSTOP 3
87 #define OPT_RDRSTSTDBY 4
88 #define OPT_BFB2 5 /* dual flash bank only */
89
90 /* register unlock keys */
91
92 #define KEY1 0x45670123
93 #define KEY2 0xCDEF89AB
94
95 /* timeout values */
96
97 #define FLASH_WRITE_TIMEOUT 10
98 #define FLASH_ERASE_TIMEOUT 100
99
100 struct stm32x_options {
101 uint8_t rdp;
102 uint8_t user;
103 uint16_t data;
104 uint32_t protection;
105 };
106
107 struct stm32x_flash_bank {
108 struct stm32x_options option_bytes;
109 int ppage_size;
110 bool probed;
111
112 bool has_dual_banks;
113 /* used to access dual flash bank stm32xl */
114 bool can_load_options;
115 uint32_t register_base;
116 uint8_t default_rdp;
117 int user_data_offset;
118 int option_offset;
119 uint32_t user_bank_size;
120 };
121
122 static int stm32x_mass_erase(struct flash_bank *bank);
123 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
124 uint32_t address, uint32_t hwords_count);
125
126 /* flash bank stm32x <base> <size> 0 0 <target#>
127 */
128 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
129 {
130 struct stm32x_flash_bank *stm32x_info;
131
132 if (CMD_ARGC < 6)
133 return ERROR_COMMAND_SYNTAX_ERROR;
134
135 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
136
137 bank->driver_priv = stm32x_info;
138 stm32x_info->probed = false;
139 stm32x_info->has_dual_banks = false;
140 stm32x_info->can_load_options = false;
141 stm32x_info->register_base = FLASH_REG_BASE_B0;
142 stm32x_info->user_bank_size = bank->size;
143
144 /* The flash write must be aligned to a halfword boundary */
145 bank->write_start_alignment = bank->write_end_alignment = 2;
146
147 return ERROR_OK;
148 }
149
150 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
151 {
152 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
153 return reg + stm32x_info->register_base;
154 }
155
156 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
157 {
158 struct target *target = bank->target;
159 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
160 }
161
162 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
163 {
164 struct target *target = bank->target;
165 uint32_t status;
166 int retval = ERROR_OK;
167
168 /* wait for busy to clear */
169 for (;;) {
170 retval = stm32x_get_flash_status(bank, &status);
171 if (retval != ERROR_OK)
172 return retval;
173 LOG_DEBUG("status: 0x%" PRIx32 "", status);
174 if ((status & FLASH_BSY) == 0)
175 break;
176 if (timeout-- <= 0) {
177 LOG_ERROR("timed out waiting for flash");
178 return ERROR_FLASH_BUSY;
179 }
180 alive_sleep(1);
181 }
182
183 if (status & FLASH_WRPRTERR) {
184 LOG_ERROR("stm32x device protected");
185 retval = ERROR_FLASH_PROTECTED;
186 }
187
188 if (status & FLASH_PGERR) {
189 LOG_ERROR("stm32x device programming failed / flash not erased");
190 retval = ERROR_FLASH_OPERATION_FAILED;
191 }
192
193 /* Clear but report errors */
194 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
195 /* If this operation fails, we ignore it and report the original
196 * retval
197 */
198 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
199 FLASH_WRPRTERR | FLASH_PGERR);
200 }
201 return retval;
202 }
203
204 static int stm32x_check_operation_supported(struct flash_bank *bank)
205 {
206 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
207
208 /* if we have a dual flash bank device then
209 * we need to perform option byte stuff on bank0 only */
210 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
211 LOG_ERROR("Option byte operations must use bank 0");
212 return ERROR_FLASH_OPERATION_FAILED;
213 }
214
215 return ERROR_OK;
216 }
217
218 static int stm32x_read_options(struct flash_bank *bank)
219 {
220 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
221 struct target *target = bank->target;
222 uint32_t option_bytes;
223 int retval;
224
225 /* read user and read protection option bytes, user data option bytes */
226 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
227 if (retval != ERROR_OK)
228 return retval;
229
230 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
231 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
232 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
233
234 /* read write protection option bytes */
235 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
236 if (retval != ERROR_OK)
237 return retval;
238
239 return ERROR_OK;
240 }
241
242 static int stm32x_erase_options(struct flash_bank *bank)
243 {
244 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
245 struct target *target = bank->target;
246
247 /* read current options */
248 stm32x_read_options(bank);
249
250 /* unlock flash registers */
251 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
252 if (retval != ERROR_OK)
253 return retval;
254 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
255 if (retval != ERROR_OK)
256 goto flash_lock;
257
258 /* unlock option flash registers */
259 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
260 if (retval != ERROR_OK)
261 goto flash_lock;
262 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 goto flash_lock;
265
266 /* erase option bytes */
267 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
268 if (retval != ERROR_OK)
269 goto flash_lock;
270 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
271 if (retval != ERROR_OK)
272 goto flash_lock;
273
274 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
275 if (retval != ERROR_OK)
276 goto flash_lock;
277
278 /* clear read protection option byte
279 * this will also force a device unlock if set */
280 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
281
282 return ERROR_OK;
283
284 flash_lock:
285 target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
286 return retval;
287 }
288
289 static int stm32x_write_options(struct flash_bank *bank)
290 {
291 struct stm32x_flash_bank *stm32x_info = NULL;
292 struct target *target = bank->target;
293
294 stm32x_info = bank->driver_priv;
295
296 /* unlock flash registers */
297 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
298 if (retval != ERROR_OK)
299 return retval;
300 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
301 if (retval != ERROR_OK)
302 goto flash_lock;
303
304 /* unlock option flash registers */
305 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
306 if (retval != ERROR_OK)
307 goto flash_lock;
308 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
309 if (retval != ERROR_OK)
310 goto flash_lock;
311
312 /* program option bytes */
313 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
314 if (retval != ERROR_OK)
315 goto flash_lock;
316
317 uint8_t opt_bytes[16];
318
319 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
320 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
321 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
322 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
323 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
324 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
325 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
327
328 /* Block write is preferred in favour of operation with ancient ST-Link
329 * firmwares without 16-bit memory access. See
330 * 480: flash: stm32f1x: write option bytes using the loader
331 * https://review.openocd.org/c/openocd/+/480
332 */
333 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
334
335 flash_lock:
336 {
337 int retval2 = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
338 if (retval == ERROR_OK)
339 retval = retval2;
340 }
341 return retval;
342 }
343
344 static int stm32x_protect_check(struct flash_bank *bank)
345 {
346 struct target *target = bank->target;
347 uint32_t protection;
348
349 int retval = stm32x_check_operation_supported(bank);
350 if (retval != ERROR_OK)
351 return retval;
352
353 /* medium density - each bit refers to a 4 sector protection block
354 * high density - each bit refers to a 2 sector protection block
355 * bit 31 refers to all remaining sectors in a bank */
356 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
357 if (retval != ERROR_OK)
358 return retval;
359
360 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
361 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
362
363 return ERROR_OK;
364 }
365
366 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
367 unsigned int last)
368 {
369 struct target *target = bank->target;
370
371 if (bank->target->state != TARGET_HALTED) {
372 LOG_ERROR("Target not halted");
373 return ERROR_TARGET_NOT_HALTED;
374 }
375
376 if ((first == 0) && (last == (bank->num_sectors - 1)))
377 return stm32x_mass_erase(bank);
378
379 /* unlock flash registers */
380 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
381 if (retval != ERROR_OK)
382 return retval;
383 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
384 if (retval != ERROR_OK)
385 goto flash_lock;
386
387 for (unsigned int i = first; i <= last; i++) {
388 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
389 if (retval != ERROR_OK)
390 goto flash_lock;
391 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
392 bank->base + bank->sectors[i].offset);
393 if (retval != ERROR_OK)
394 goto flash_lock;
395 retval = target_write_u32(target,
396 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
397 if (retval != ERROR_OK)
398 goto flash_lock;
399
400 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
401 if (retval != ERROR_OK)
402 goto flash_lock;
403 }
404
405 flash_lock:
406 {
407 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
408 if (retval == ERROR_OK)
409 retval = retval2;
410 }
411 return retval;
412 }
413
414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
415 unsigned int last)
416 {
417 struct target *target = bank->target;
418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
419
420 if (target->state != TARGET_HALTED) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED;
423 }
424
425 int retval = stm32x_check_operation_supported(bank);
426 if (retval != ERROR_OK)
427 return retval;
428
429 retval = stm32x_erase_options(bank);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("stm32x failed to erase options");
432 return retval;
433 }
434
435 for (unsigned int i = first; i <= last; i++) {
436 if (set)
437 stm32x_info->option_bytes.protection &= ~(1 << i);
438 else
439 stm32x_info->option_bytes.protection |= (1 << i);
440 }
441
442 return stm32x_write_options(bank);
443 }
444
445 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
446 uint32_t address, uint32_t hwords_count)
447 {
448 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 struct armv7m_algorithm armv7m_info;
454 int retval;
455
456 static const uint8_t stm32x_flash_write_code[] = {
457 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
458 };
459
460 /* flash write code */
461 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
462 &write_algorithm) != ERROR_OK) {
463 LOG_WARNING("no working area available, can't do block memory writes");
464 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
465 }
466
467 retval = target_write_buffer(target, write_algorithm->address,
468 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
469 if (retval != ERROR_OK) {
470 target_free_working_area(target, write_algorithm);
471 return retval;
472 }
473
474 /* memory buffer */
475 buffer_size = target_get_working_area_avail(target);
476 buffer_size = MIN(hwords_count * 2 + 8, MAX(buffer_size, 256));
477 /* Normally we allocate all available working area.
478 * MIN shrinks buffer_size if the size of the written block is smaller.
479 * MAX prevents using async algo if the available working area is smaller
480 * than 256, the following allocation fails with
481 * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
482 */
483
484 retval = target_alloc_working_area(target, buffer_size, &source);
485 /* Allocated size is always 32-bit word aligned */
486 if (retval != ERROR_OK) {
487 target_free_working_area(target, write_algorithm);
488 LOG_WARNING("no large enough working area available, can't do block memory writes");
489 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
490 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
491 */
492 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
493 }
494
495 struct reg_param reg_params[5];
496
497 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
498 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
499 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
500 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
501 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
502
503 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
504 buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
505 buf_set_u32(reg_params[2].value, 0, 32, source->address);
506 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
507 buf_set_u32(reg_params[4].value, 0, 32, address);
508
509 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
510 armv7m_info.core_mode = ARM_MODE_THREAD;
511
512 retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
513 0, NULL,
514 ARRAY_SIZE(reg_params), reg_params,
515 source->address, source->size,
516 write_algorithm->address, 0,
517 &armv7m_info);
518
519 if (retval == ERROR_FLASH_OPERATION_FAILED) {
520 /* Actually we just need to check for programming errors
521 * stm32x_wait_status_busy also reports error and clears status bits.
522 *
523 * Target algo returns flash status in r0 only if properly finished.
524 * It is safer to re-read status register.
525 */
526 int retval2 = stm32x_wait_status_busy(bank, 5);
527 if (retval2 != ERROR_OK)
528 retval = retval2;
529
530 LOG_ERROR("flash write failed just before address 0x%"PRIx32,
531 buf_get_u32(reg_params[4].value, 0, 32));
532 }
533
534 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
535 destroy_reg_param(&reg_params[i]);
536
537 target_free_working_area(target, source);
538 target_free_working_area(target, write_algorithm);
539
540 return retval;
541 }
542
543 static int stm32x_write_block_riscv(struct flash_bank *bank, const uint8_t *buffer,
544 uint32_t address, uint32_t hwords_count)
545 {
546 struct target *target = bank->target;
547 uint32_t buffer_size;
548 struct working_area *write_algorithm;
549 struct working_area *source;
550 static const uint8_t gd32vf103_flash_write_code[] = {
551 #include "../../../contrib/loaders/flash/gd32vf103/gd32vf103.inc"
552 };
553
554 /* flash write code */
555 if (target_alloc_working_area(target, sizeof(gd32vf103_flash_write_code),
556 &write_algorithm) != ERROR_OK) {
557 LOG_WARNING("no working area available, can't do block memory writes");
558 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
559 }
560
561 int retval = target_write_buffer(target, write_algorithm->address,
562 sizeof(gd32vf103_flash_write_code), gd32vf103_flash_write_code);
563 if (retval != ERROR_OK) {
564 target_free_working_area(target, write_algorithm);
565 return retval;
566 }
567
568 /* memory buffer */
569 buffer_size = target_get_working_area_avail(target);
570 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
571
572 retval = target_alloc_working_area(target, buffer_size, &source);
573 /* Allocated size is always word aligned */
574 if (retval != ERROR_OK) {
575 target_free_working_area(target, write_algorithm);
576 LOG_WARNING("no large enough working area available, can't do block memory writes");
577 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
578 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
579 */
580 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
581 }
582
583 struct reg_param reg_params[4];
584
585 init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT); /* poiner to FLASH_SR */
586 init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT); /* count (halfword-16bit) */
587 init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT); /* buffer start */
588 init_reg_param(&reg_params[3], "a3", 32, PARAM_IN_OUT); /* target address */
589
590 while (hwords_count > 0) {
591 uint32_t thisrun_hwords = source->size / 2;
592
593 /* Limit to the amount of data we actually want to write */
594 if (thisrun_hwords > hwords_count)
595 thisrun_hwords = hwords_count;
596
597 /* Write data to buffer */
598 retval = target_write_buffer(target, source->address,
599 thisrun_hwords * 2, buffer);
600 if (retval != ERROR_OK)
601 break;
602
603 buf_set_u32(reg_params[0].value, 0, 32, stm32x_get_flash_reg(bank, STM32_FLASH_SR));
604 buf_set_u32(reg_params[1].value, 0, 32, thisrun_hwords);
605 buf_set_u32(reg_params[2].value, 0, 32, source->address);
606 buf_set_u32(reg_params[3].value, 0, 32, address);
607
608 retval = target_run_algorithm(target,
609 0, NULL,
610 ARRAY_SIZE(reg_params), reg_params,
611 write_algorithm->address,
612 write_algorithm->address + sizeof(gd32vf103_flash_write_code) - 4,
613 10000, NULL);
614
615 if (retval != ERROR_OK) {
616 LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
617 write_algorithm->address, retval);
618 break;
619 }
620
621 /* Actually we just need to check for programming errors
622 * stm32x_wait_status_busy also reports error and clears status bits
623 */
624 retval = stm32x_wait_status_busy(bank, 5);
625 if (retval != ERROR_OK) {
626 LOG_ERROR("flash write failed at address 0x%"PRIx32,
627 buf_get_u32(reg_params[3].value, 0, 32));
628 break;
629 }
630
631 /* Update counters */
632 buffer += thisrun_hwords * 2;
633 address += thisrun_hwords * 2;
634 hwords_count -= thisrun_hwords;
635 }
636
637 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
638 destroy_reg_param(&reg_params[i]);
639
640 target_free_working_area(target, source);
641 target_free_working_area(target, write_algorithm);
642
643 return retval;
644 }
645
646 /** Writes a block to flash either using target algorithm
647 * or use fallback, host controlled halfword-by-halfword access.
648 * Flash controller must be unlocked before this call.
649 */
650 static int stm32x_write_block(struct flash_bank *bank,
651 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
652 {
653 struct target *target = bank->target;
654
655 /* The flash write must be aligned to a halfword boundary.
656 * The flash infrastructure ensures it, do just a security check
657 */
658 assert(address % 2 == 0);
659
660 int retval;
661 struct arm *arm = target_to_arm(target);
662 if (is_arm(arm)) {
663 /* try using a block write - on ARM architecture or... */
664 retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
665 } else {
666 /* ... RISC-V architecture */
667 retval = stm32x_write_block_riscv(bank, buffer, address, hwords_count);
668 }
669
670 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
671 /* if block write failed (no sufficient working area),
672 * we use normal (slow) single halfword accesses */
673 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
674
675 while (hwords_count > 0) {
676 retval = target_write_memory(target, address, 2, 1, buffer);
677 if (retval != ERROR_OK)
678 return retval;
679
680 retval = stm32x_wait_status_busy(bank, 5);
681 if (retval != ERROR_OK)
682 return retval;
683
684 hwords_count--;
685 buffer += 2;
686 address += 2;
687 }
688 }
689 return retval;
690 }
691
692 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
693 uint32_t offset, uint32_t count)
694 {
695 struct target *target = bank->target;
696
697 if (bank->target->state != TARGET_HALTED) {
698 LOG_ERROR("Target not halted");
699 return ERROR_TARGET_NOT_HALTED;
700 }
701
702 /* The flash write must be aligned to a halfword boundary.
703 * The flash infrastructure ensures it, do just a security check
704 */
705 assert(offset % 2 == 0);
706 assert(count % 2 == 0);
707
708 int retval, retval2;
709
710 /* unlock flash registers */
711 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
712 if (retval != ERROR_OK)
713 return retval;
714 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
715 if (retval != ERROR_OK)
716 goto reset_pg_and_lock;
717
718 /* enable flash programming */
719 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
720 if (retval != ERROR_OK)
721 goto reset_pg_and_lock;
722
723 /* write to flash */
724 retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
725
726 reset_pg_and_lock:
727 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
728 if (retval == ERROR_OK)
729 retval = retval2;
730
731 return retval;
732 }
733
734 struct stm32x_property_addr {
735 uint32_t device_id;
736 uint32_t flash_size;
737 };
738
739 static int stm32x_get_property_addr(struct target *target, struct stm32x_property_addr *addr)
740 {
741 if (!target_was_examined(target)) {
742 LOG_ERROR("Target not examined yet");
743 return ERROR_TARGET_NOT_EXAMINED;
744 }
745
746 switch (cortex_m_get_impl_part(target)) {
747 case CORTEX_M0_PARTNO: /* STM32F0x devices */
748 case CORTEX_M0P_PARTNO: /* APM32F0x devices */
749 addr->device_id = 0x40015800;
750 addr->flash_size = 0x1FFFF7CC;
751 return ERROR_OK;
752 case CORTEX_M3_PARTNO: /* STM32F1x devices */
753 addr->device_id = 0xE0042000;
754 addr->flash_size = 0x1FFFF7E0;
755 return ERROR_OK;
756 case CORTEX_M4_PARTNO: /* STM32F3x devices */
757 addr->device_id = 0xE0042000;
758 addr->flash_size = 0x1FFFF7CC;
759 return ERROR_OK;
760 case CORTEX_M23_PARTNO: /* GD32E23x devices */
761 addr->device_id = 0x40015800;
762 addr->flash_size = 0x1FFFF7E0;
763 return ERROR_OK;
764 case CORTEX_M_PARTNO_INVALID:
765 /* Check for GD32VF103 with RISC-V CPU */
766 if (strcmp(target_type_name(target), "riscv") == 0
767 && target_address_bits(target) == 32) {
768 /* There is nothing like arm common_magic in riscv_info_t
769 * check text name of target and if target is 32-bit
770 */
771 addr->device_id = 0xE0042000;
772 addr->flash_size = 0x1FFFF7E0;
773 return ERROR_OK;
774 }
775 /* fallthrough */
776 default:
777 LOG_ERROR("Cannot identify target as a stm32x");
778 return ERROR_FAIL;
779 }
780 }
781
782 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
783 {
784 struct target *target = bank->target;
785 struct stm32x_property_addr addr;
786
787 int retval = stm32x_get_property_addr(target, &addr);
788 if (retval != ERROR_OK)
789 return retval;
790
791 return target_read_u32(target, addr.device_id, device_id);
792 }
793
794 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
795 {
796 struct target *target = bank->target;
797 struct stm32x_property_addr addr;
798
799 int retval = stm32x_get_property_addr(target, &addr);
800 if (retval != ERROR_OK)
801 return retval;
802
803 return target_read_u16(target, addr.flash_size, flash_size_in_kb);
804 }
805
806 static int stm32x_probe(struct flash_bank *bank)
807 {
808 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
809 uint16_t flash_size_in_kb;
810 uint16_t max_flash_size_in_kb;
811 uint32_t dbgmcu_idcode;
812 int page_size;
813 uint32_t base_address = 0x08000000;
814
815 stm32x_info->probed = false;
816 stm32x_info->register_base = FLASH_REG_BASE_B0;
817 stm32x_info->user_data_offset = 10;
818 stm32x_info->option_offset = 0;
819
820 /* default factory read protection level 0 */
821 stm32x_info->default_rdp = 0xA5;
822
823 /* read stm32 device id register */
824 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
825 if (retval != ERROR_OK)
826 return retval;
827
828 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
829
830 uint16_t device_id = dbgmcu_idcode & 0xfff;
831 uint16_t rev_id = dbgmcu_idcode >> 16;
832
833 /* set page size, protection granularity and max flash size depending on family */
834 switch (device_id) {
835 case 0x440: /* stm32f05x */
836 page_size = 1024;
837 stm32x_info->ppage_size = 4;
838 max_flash_size_in_kb = 64;
839 stm32x_info->user_data_offset = 16;
840 stm32x_info->option_offset = 6;
841 stm32x_info->default_rdp = 0xAA;
842 stm32x_info->can_load_options = true;
843 break;
844 case 0x444: /* stm32f03x */
845 case 0x445: /* stm32f04x */
846 page_size = 1024;
847 stm32x_info->ppage_size = 4;
848 max_flash_size_in_kb = 32;
849 stm32x_info->user_data_offset = 16;
850 stm32x_info->option_offset = 6;
851 stm32x_info->default_rdp = 0xAA;
852 stm32x_info->can_load_options = true;
853 break;
854 case 0x448: /* stm32f07x */
855 page_size = 2048;
856 stm32x_info->ppage_size = 4;
857 max_flash_size_in_kb = 128;
858 stm32x_info->user_data_offset = 16;
859 stm32x_info->option_offset = 6;
860 stm32x_info->default_rdp = 0xAA;
861 stm32x_info->can_load_options = true;
862 break;
863 case 0x442: /* stm32f09x */
864 page_size = 2048;
865 stm32x_info->ppage_size = 4;
866 max_flash_size_in_kb = 256;
867 stm32x_info->user_data_offset = 16;
868 stm32x_info->option_offset = 6;
869 stm32x_info->default_rdp = 0xAA;
870 stm32x_info->can_load_options = true;
871 break;
872 case 0x410: /* stm32f1x medium-density */
873 page_size = 1024;
874 stm32x_info->ppage_size = 4;
875 max_flash_size_in_kb = 128;
876 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
877 share DEV_ID with STM32F101/2/3 medium-density line,
878 however they use a REV_ID different from any STM32 device.
879 The main difference is another offset of user option bits
880 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
881 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
882 This caused problems e.g. during flash block programming
883 because of unexpected active hardware watchog. */
884 switch (rev_id) {
885 case 0x1303: /* gd32f1x0 */
886 stm32x_info->user_data_offset = 16;
887 stm32x_info->option_offset = 6;
888 max_flash_size_in_kb = 64;
889 stm32x_info->can_load_options = true;
890 break;
891 case 0x1704: /* gd32f3x0 */
892 stm32x_info->user_data_offset = 16;
893 stm32x_info->option_offset = 6;
894 stm32x_info->can_load_options = true;
895 break;
896 case 0x1906: /* gd32vf103 */
897 break;
898 case 0x1909: /* gd32e23x */
899 stm32x_info->user_data_offset = 16;
900 stm32x_info->option_offset = 6;
901 max_flash_size_in_kb = 64;
902 stm32x_info->can_load_options = true;
903 break;
904 }
905 break;
906 case 0x412: /* stm32f1x low-density */
907 page_size = 1024;
908 stm32x_info->ppage_size = 4;
909 max_flash_size_in_kb = 32;
910 break;
911 case 0x414: /* stm32f1x high-density */
912 page_size = 2048;
913 stm32x_info->ppage_size = 2;
914 max_flash_size_in_kb = 512;
915 break;
916 case 0x418: /* stm32f1x connectivity */
917 page_size = 2048;
918 stm32x_info->ppage_size = 2;
919 max_flash_size_in_kb = 256;
920 break;
921 case 0x430: /* stm32f1 XL-density (dual flash banks) */
922 page_size = 2048;
923 stm32x_info->ppage_size = 2;
924 max_flash_size_in_kb = 1024;
925 stm32x_info->has_dual_banks = true;
926 break;
927 case 0x420: /* stm32f100xx low- and medium-density value line */
928 page_size = 1024;
929 stm32x_info->ppage_size = 4;
930 max_flash_size_in_kb = 128;
931 break;
932 case 0x428: /* stm32f100xx high-density value line */
933 page_size = 2048;
934 stm32x_info->ppage_size = 4;
935 max_flash_size_in_kb = 512;
936 break;
937 case 0x422: /* stm32f302/3xb/c */
938 page_size = 2048;
939 stm32x_info->ppage_size = 2;
940 max_flash_size_in_kb = 256;
941 stm32x_info->user_data_offset = 16;
942 stm32x_info->option_offset = 6;
943 stm32x_info->default_rdp = 0xAA;
944 stm32x_info->can_load_options = true;
945 break;
946 case 0x446: /* stm32f303xD/E */
947 page_size = 2048;
948 stm32x_info->ppage_size = 2;
949 max_flash_size_in_kb = 512;
950 stm32x_info->user_data_offset = 16;
951 stm32x_info->option_offset = 6;
952 stm32x_info->default_rdp = 0xAA;
953 stm32x_info->can_load_options = true;
954 break;
955 case 0x432: /* stm32f37x */
956 page_size = 2048;
957 stm32x_info->ppage_size = 2;
958 max_flash_size_in_kb = 256;
959 stm32x_info->user_data_offset = 16;
960 stm32x_info->option_offset = 6;
961 stm32x_info->default_rdp = 0xAA;
962 stm32x_info->can_load_options = true;
963 break;
964 case 0x438: /* stm32f33x */
965 case 0x439: /* stm32f302x6/8 */
966 page_size = 2048;
967 stm32x_info->ppage_size = 2;
968 max_flash_size_in_kb = 64;
969 stm32x_info->user_data_offset = 16;
970 stm32x_info->option_offset = 6;
971 stm32x_info->default_rdp = 0xAA;
972 stm32x_info->can_load_options = true;
973 break;
974 default:
975 LOG_WARNING("Cannot identify target as a STM32 family.");
976 return ERROR_FAIL;
977 }
978
979 /* get flash size from target. */
980 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
981
982 /* failed reading flash size or flash size invalid (early silicon),
983 * default to max target family */
984 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
985 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
986 max_flash_size_in_kb);
987 flash_size_in_kb = max_flash_size_in_kb;
988 }
989
990 if (stm32x_info->has_dual_banks) {
991 /* split reported size into matching bank */
992 if (bank->base != 0x08080000) {
993 /* bank 0 will be fixed 512k */
994 flash_size_in_kb = 512;
995 } else {
996 flash_size_in_kb -= 512;
997 /* bank1 also uses a register offset */
998 stm32x_info->register_base = FLASH_REG_BASE_B1;
999 base_address = 0x08080000;
1000 }
1001 }
1002
1003 /* if the user sets the size manually then ignore the probed value
1004 * this allows us to work around devices that have a invalid flash size register value */
1005 if (stm32x_info->user_bank_size) {
1006 LOG_INFO("ignoring flash probed value, using configured bank size");
1007 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
1008 }
1009
1010 LOG_INFO("flash size = %d KiB", flash_size_in_kb);
1011
1012 /* did we assign flash size? */
1013 assert(flash_size_in_kb != 0xffff);
1014
1015 /* calculate numbers of pages */
1016 int num_pages = flash_size_in_kb * 1024 / page_size;
1017
1018 /* check that calculation result makes sense */
1019 assert(num_pages > 0);
1020
1021 free(bank->sectors);
1022 bank->sectors = NULL;
1023
1024 free(bank->prot_blocks);
1025 bank->prot_blocks = NULL;
1026
1027 bank->base = base_address;
1028 bank->size = (num_pages * page_size);
1029
1030 bank->num_sectors = num_pages;
1031 bank->sectors = alloc_block_array(0, page_size, num_pages);
1032 if (!bank->sectors)
1033 return ERROR_FAIL;
1034
1035 /* calculate number of write protection blocks */
1036 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
1037 if (num_prot_blocks > 32)
1038 num_prot_blocks = 32;
1039
1040 bank->num_prot_blocks = num_prot_blocks;
1041 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
1042 if (!bank->prot_blocks)
1043 return ERROR_FAIL;
1044
1045 if (num_prot_blocks == 32)
1046 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
1047
1048 stm32x_info->probed = true;
1049
1050 return ERROR_OK;
1051 }
1052
1053 static int stm32x_auto_probe(struct flash_bank *bank)
1054 {
1055 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1056 if (stm32x_info->probed)
1057 return ERROR_OK;
1058 return stm32x_probe(bank);
1059 }
1060
1061 #if 0
1062 COMMAND_HANDLER(stm32x_handle_part_id_command)
1063 {
1064 return ERROR_OK;
1065 }
1066 #endif
1067
1068 static const char *get_stm32f0_revision(uint16_t rev_id)
1069 {
1070 const char *rev_str = NULL;
1071
1072 switch (rev_id) {
1073 case 0x1000:
1074 rev_str = "1.0";
1075 break;
1076 case 0x2000:
1077 rev_str = "2.0";
1078 break;
1079 }
1080 return rev_str;
1081 }
1082
1083 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1084 {
1085 uint32_t dbgmcu_idcode;
1086
1087 /* read stm32 device id register */
1088 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1089 if (retval != ERROR_OK)
1090 return retval;
1091
1092 uint16_t device_id = dbgmcu_idcode & 0xfff;
1093 uint16_t rev_id = dbgmcu_idcode >> 16;
1094 const char *device_str;
1095 const char *rev_str = NULL;
1096
1097 switch (device_id) {
1098 case 0x410:
1099 device_str = "STM32F10x (Medium Density)";
1100
1101 switch (rev_id) {
1102 case 0x0000:
1103 rev_str = "A";
1104 break;
1105
1106 case 0x1303: /* gd32f1x0 */
1107 device_str = "GD32F1x0";
1108 break;
1109
1110 case 0x1704: /* gd32f3x0 */
1111 device_str = "GD32F3x0";
1112 break;
1113
1114 case 0x1906:
1115 device_str = "GD32VF103";
1116 break;
1117
1118 case 0x1909: /* gd32e23x */
1119 device_str = "GD32E23x";
1120 break;
1121
1122 case 0x2000:
1123 rev_str = "B";
1124 break;
1125
1126 case 0x2001:
1127 rev_str = "Z";
1128 break;
1129
1130 case 0x2003:
1131 rev_str = "Y";
1132 break;
1133 }
1134 break;
1135
1136 case 0x412:
1137 device_str = "STM32F10x (Low Density)";
1138
1139 switch (rev_id) {
1140 case 0x1000:
1141 rev_str = "A";
1142 break;
1143 }
1144 break;
1145
1146 case 0x414:
1147 device_str = "STM32F10x (High Density)";
1148
1149 switch (rev_id) {
1150 case 0x1000:
1151 rev_str = "A";
1152 break;
1153
1154 case 0x1001:
1155 rev_str = "Z";
1156 break;
1157
1158 case 0x1003:
1159 rev_str = "Y";
1160 break;
1161 }
1162 break;
1163
1164 case 0x418:
1165 device_str = "STM32F10x (Connectivity)";
1166
1167 switch (rev_id) {
1168 case 0x1000:
1169 rev_str = "A";
1170 break;
1171
1172 case 0x1001:
1173 rev_str = "Z";
1174 break;
1175 }
1176 break;
1177
1178 case 0x420:
1179 device_str = "STM32F100 (Low/Medium Density)";
1180
1181 switch (rev_id) {
1182 case 0x1000:
1183 rev_str = "A";
1184 break;
1185
1186 case 0x1001:
1187 rev_str = "Z";
1188 break;
1189 }
1190 break;
1191
1192 case 0x422:
1193 device_str = "STM32F302xB/C";
1194
1195 switch (rev_id) {
1196 case 0x1000:
1197 rev_str = "A";
1198 break;
1199
1200 case 0x1001:
1201 rev_str = "Z";
1202 break;
1203
1204 case 0x1003:
1205 rev_str = "Y";
1206 break;
1207
1208 case 0x2000:
1209 rev_str = "B";
1210 break;
1211 }
1212 break;
1213
1214 case 0x428:
1215 device_str = "STM32F100 (High Density)";
1216
1217 switch (rev_id) {
1218 case 0x1000:
1219 rev_str = "A";
1220 break;
1221
1222 case 0x1001:
1223 rev_str = "Z";
1224 break;
1225 }
1226 break;
1227
1228 case 0x430:
1229 device_str = "STM32F10x (XL Density)";
1230
1231 switch (rev_id) {
1232 case 0x1000:
1233 rev_str = "A";
1234 break;
1235 }
1236 break;
1237
1238 case 0x432:
1239 device_str = "STM32F37x";
1240
1241 switch (rev_id) {
1242 case 0x1000:
1243 rev_str = "A";
1244 break;
1245
1246 case 0x2000:
1247 rev_str = "B";
1248 break;
1249 }
1250 break;
1251
1252 case 0x438:
1253 device_str = "STM32F33x";
1254
1255 switch (rev_id) {
1256 case 0x1000:
1257 rev_str = "A";
1258 break;
1259 }
1260 break;
1261
1262 case 0x439:
1263 device_str = "STM32F302x6/8";
1264
1265 switch (rev_id) {
1266 case 0x1000:
1267 rev_str = "A";
1268 break;
1269
1270 case 0x1001:
1271 rev_str = "Z";
1272 break;
1273 }
1274 break;
1275
1276 case 0x444:
1277 device_str = "STM32F03x";
1278 rev_str = get_stm32f0_revision(rev_id);
1279 break;
1280
1281 case 0x440:
1282 device_str = "STM32F05x";
1283 rev_str = get_stm32f0_revision(rev_id);
1284 break;
1285
1286 case 0x445:
1287 device_str = "STM32F04x";
1288 rev_str = get_stm32f0_revision(rev_id);
1289 break;
1290
1291 case 0x446:
1292 device_str = "STM32F303xD/E";
1293 switch (rev_id) {
1294 case 0x1000:
1295 rev_str = "A";
1296 break;
1297 }
1298 break;
1299
1300 case 0x448:
1301 device_str = "STM32F07x";
1302 rev_str = get_stm32f0_revision(rev_id);
1303 break;
1304
1305 case 0x442:
1306 device_str = "STM32F09x";
1307 rev_str = get_stm32f0_revision(rev_id);
1308 break;
1309
1310 default:
1311 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1312 return ERROR_FAIL;
1313 }
1314
1315 if (rev_str)
1316 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1317 else
1318 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1319
1320 return ERROR_OK;
1321 }
1322
1323 COMMAND_HANDLER(stm32x_handle_lock_command)
1324 {
1325 struct target *target = NULL;
1326 struct stm32x_flash_bank *stm32x_info = NULL;
1327
1328 if (CMD_ARGC < 1)
1329 return ERROR_COMMAND_SYNTAX_ERROR;
1330
1331 struct flash_bank *bank;
1332 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1333 if (retval != ERROR_OK)
1334 return retval;
1335
1336 stm32x_info = bank->driver_priv;
1337
1338 target = bank->target;
1339
1340 if (target->state != TARGET_HALTED) {
1341 LOG_ERROR("Target not halted");
1342 return ERROR_TARGET_NOT_HALTED;
1343 }
1344
1345 retval = stm32x_check_operation_supported(bank);
1346 if (retval != ERROR_OK)
1347 return retval;
1348
1349 if (stm32x_erase_options(bank) != ERROR_OK) {
1350 command_print(CMD, "stm32x failed to erase options");
1351 return ERROR_OK;
1352 }
1353
1354 /* set readout protection */
1355 stm32x_info->option_bytes.rdp = 0;
1356
1357 if (stm32x_write_options(bank) != ERROR_OK) {
1358 command_print(CMD, "stm32x failed to lock device");
1359 return ERROR_OK;
1360 }
1361
1362 command_print(CMD, "stm32x locked");
1363
1364 return ERROR_OK;
1365 }
1366
1367 COMMAND_HANDLER(stm32x_handle_unlock_command)
1368 {
1369 struct target *target = NULL;
1370
1371 if (CMD_ARGC < 1)
1372 return ERROR_COMMAND_SYNTAX_ERROR;
1373
1374 struct flash_bank *bank;
1375 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1376 if (retval != ERROR_OK)
1377 return retval;
1378
1379 target = bank->target;
1380
1381 if (target->state != TARGET_HALTED) {
1382 LOG_ERROR("Target not halted");
1383 return ERROR_TARGET_NOT_HALTED;
1384 }
1385
1386 retval = stm32x_check_operation_supported(bank);
1387 if (retval != ERROR_OK)
1388 return retval;
1389
1390 if (stm32x_erase_options(bank) != ERROR_OK) {
1391 command_print(CMD, "stm32x failed to erase options");
1392 return ERROR_OK;
1393 }
1394
1395 if (stm32x_write_options(bank) != ERROR_OK) {
1396 command_print(CMD, "stm32x failed to unlock device");
1397 return ERROR_OK;
1398 }
1399
1400 command_print(CMD, "stm32x unlocked.\n"
1401 "INFO: a reset or power cycle is required "
1402 "for the new settings to take effect.");
1403
1404 return ERROR_OK;
1405 }
1406
1407 COMMAND_HANDLER(stm32x_handle_options_read_command)
1408 {
1409 uint32_t optionbyte, protection;
1410 struct target *target = NULL;
1411 struct stm32x_flash_bank *stm32x_info = NULL;
1412
1413 if (CMD_ARGC < 1)
1414 return ERROR_COMMAND_SYNTAX_ERROR;
1415
1416 struct flash_bank *bank;
1417 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1418 if (retval != ERROR_OK)
1419 return retval;
1420
1421 stm32x_info = bank->driver_priv;
1422
1423 target = bank->target;
1424
1425 if (target->state != TARGET_HALTED) {
1426 LOG_ERROR("Target not halted");
1427 return ERROR_TARGET_NOT_HALTED;
1428 }
1429
1430 retval = stm32x_check_operation_supported(bank);
1431 if (retval != ERROR_OK)
1432 return retval;
1433
1434 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1435 if (retval != ERROR_OK)
1436 return retval;
1437
1438 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1439
1440 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1441 if (retval != ERROR_OK)
1442 return retval;
1443
1444 if (optionbyte & (1 << OPT_ERROR))
1445 command_print(CMD, "option byte complement error");
1446
1447 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1448 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1449
1450 command_print(CMD, "read protection: %s",
1451 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1452
1453 /* user option bytes are offset depending on variant */
1454 optionbyte >>= stm32x_info->option_offset;
1455
1456 command_print(CMD, "watchdog: %sware",
1457 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1458
1459 command_print(CMD, "stop mode: %sreset generated upon entry",
1460 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1461
1462 command_print(CMD, "standby mode: %sreset generated upon entry",
1463 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1464
1465 if (stm32x_info->has_dual_banks)
1466 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1467
1468 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1469
1470 return ERROR_OK;
1471 }
1472
1473 COMMAND_HANDLER(stm32x_handle_options_write_command)
1474 {
1475 struct target *target = NULL;
1476 struct stm32x_flash_bank *stm32x_info = NULL;
1477 uint8_t optionbyte;
1478 uint16_t useropt;
1479
1480 if (CMD_ARGC < 2)
1481 return ERROR_COMMAND_SYNTAX_ERROR;
1482
1483 struct flash_bank *bank;
1484 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1485 if (retval != ERROR_OK)
1486 return retval;
1487
1488 stm32x_info = bank->driver_priv;
1489
1490 target = bank->target;
1491
1492 if (target->state != TARGET_HALTED) {
1493 LOG_ERROR("Target not halted");
1494 return ERROR_TARGET_NOT_HALTED;
1495 }
1496
1497 retval = stm32x_check_operation_supported(bank);
1498 if (retval != ERROR_OK)
1499 return retval;
1500
1501 retval = stm32x_read_options(bank);
1502 if (retval != ERROR_OK)
1503 return retval;
1504
1505 /* start with current options */
1506 optionbyte = stm32x_info->option_bytes.user;
1507 useropt = stm32x_info->option_bytes.data;
1508
1509 /* skip over flash bank */
1510 CMD_ARGC--;
1511 CMD_ARGV++;
1512
1513 while (CMD_ARGC) {
1514 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1515 optionbyte |= (1 << 0);
1516 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1517 optionbyte &= ~(1 << 0);
1518 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1519 optionbyte |= (1 << 1);
1520 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1521 optionbyte &= ~(1 << 1);
1522 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1523 optionbyte |= (1 << 2);
1524 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1525 optionbyte &= ~(1 << 2);
1526 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1527 if (CMD_ARGC < 2)
1528 return ERROR_COMMAND_SYNTAX_ERROR;
1529 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1530 CMD_ARGC--;
1531 CMD_ARGV++;
1532 } else if (stm32x_info->has_dual_banks) {
1533 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1534 optionbyte |= (1 << 3);
1535 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1536 optionbyte &= ~(1 << 3);
1537 else
1538 return ERROR_COMMAND_SYNTAX_ERROR;
1539 } else
1540 return ERROR_COMMAND_SYNTAX_ERROR;
1541 CMD_ARGC--;
1542 CMD_ARGV++;
1543 }
1544
1545 if (stm32x_erase_options(bank) != ERROR_OK) {
1546 command_print(CMD, "stm32x failed to erase options");
1547 return ERROR_OK;
1548 }
1549
1550 stm32x_info->option_bytes.user = optionbyte;
1551 stm32x_info->option_bytes.data = useropt;
1552
1553 if (stm32x_write_options(bank) != ERROR_OK) {
1554 command_print(CMD, "stm32x failed to write options");
1555 return ERROR_OK;
1556 }
1557
1558 command_print(CMD, "stm32x write options complete.\n"
1559 "INFO: %spower cycle is required "
1560 "for the new settings to take effect.",
1561 stm32x_info->can_load_options
1562 ? "'stm32f1x options_load' command or " : "");
1563
1564 return ERROR_OK;
1565 }
1566
1567 COMMAND_HANDLER(stm32x_handle_options_load_command)
1568 {
1569 if (CMD_ARGC < 1)
1570 return ERROR_COMMAND_SYNTAX_ERROR;
1571
1572 struct flash_bank *bank;
1573 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1574 if (retval != ERROR_OK)
1575 return retval;
1576
1577 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1578
1579 if (!stm32x_info->can_load_options) {
1580 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1581 "required instead.");
1582 return ERROR_FAIL;
1583 }
1584
1585 struct target *target = bank->target;
1586
1587 if (target->state != TARGET_HALTED) {
1588 LOG_ERROR("Target not halted");
1589 return ERROR_TARGET_NOT_HALTED;
1590 }
1591
1592 retval = stm32x_check_operation_supported(bank);
1593 if (retval != ERROR_OK)
1594 return retval;
1595
1596 /* unlock option flash registers */
1597 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1598 if (retval != ERROR_OK)
1599 return retval;
1600 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1601 if (retval != ERROR_OK) {
1602 (void)target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1603 return retval;
1604 }
1605
1606 /* force re-load of option bytes - generates software reset */
1607 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1608 if (retval != ERROR_OK)
1609 return retval;
1610
1611 return ERROR_OK;
1612 }
1613
1614 static int stm32x_mass_erase(struct flash_bank *bank)
1615 {
1616 struct target *target = bank->target;
1617
1618 if (target->state != TARGET_HALTED) {
1619 LOG_ERROR("Target not halted");
1620 return ERROR_TARGET_NOT_HALTED;
1621 }
1622
1623 /* unlock option flash registers */
1624 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1625 if (retval != ERROR_OK)
1626 return retval;
1627 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1628 if (retval != ERROR_OK)
1629 goto flash_lock;
1630
1631 /* mass erase flash memory */
1632 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1633 if (retval != ERROR_OK)
1634 goto flash_lock;
1635 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1636 FLASH_MER | FLASH_STRT);
1637 if (retval != ERROR_OK)
1638 goto flash_lock;
1639
1640 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1641
1642 flash_lock:
1643 {
1644 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1645 if (retval == ERROR_OK)
1646 retval = retval2;
1647 }
1648 return retval;
1649 }
1650
1651 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1652 {
1653 if (CMD_ARGC < 1)
1654 return ERROR_COMMAND_SYNTAX_ERROR;
1655
1656 struct flash_bank *bank;
1657 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1658 if (retval != ERROR_OK)
1659 return retval;
1660
1661 retval = stm32x_mass_erase(bank);
1662 if (retval == ERROR_OK)
1663 command_print(CMD, "stm32x mass erase complete");
1664 else
1665 command_print(CMD, "stm32x mass erase failed");
1666
1667 return retval;
1668 }
1669
1670 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1671 {
1672 .name = "lock",
1673 .handler = stm32x_handle_lock_command,
1674 .mode = COMMAND_EXEC,
1675 .usage = "bank_id",
1676 .help = "Lock entire flash device.",
1677 },
1678 {
1679 .name = "unlock",
1680 .handler = stm32x_handle_unlock_command,
1681 .mode = COMMAND_EXEC,
1682 .usage = "bank_id",
1683 .help = "Unlock entire protected flash device.",
1684 },
1685 {
1686 .name = "mass_erase",
1687 .handler = stm32x_handle_mass_erase_command,
1688 .mode = COMMAND_EXEC,
1689 .usage = "bank_id",
1690 .help = "Erase entire flash device.",
1691 },
1692 {
1693 .name = "options_read",
1694 .handler = stm32x_handle_options_read_command,
1695 .mode = COMMAND_EXEC,
1696 .usage = "bank_id",
1697 .help = "Read and display device option bytes.",
1698 },
1699 {
1700 .name = "options_write",
1701 .handler = stm32x_handle_options_write_command,
1702 .mode = COMMAND_EXEC,
1703 .usage = "bank_id ('SWWDG'|'HWWDG') "
1704 "('RSTSTNDBY'|'NORSTSTNDBY') "
1705 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1706 .help = "Replace bits in device option bytes.",
1707 },
1708 {
1709 .name = "options_load",
1710 .handler = stm32x_handle_options_load_command,
1711 .mode = COMMAND_EXEC,
1712 .usage = "bank_id",
1713 .help = "Force re-load of device option bytes.",
1714 },
1715 COMMAND_REGISTRATION_DONE
1716 };
1717
1718 static const struct command_registration stm32f1x_command_handlers[] = {
1719 {
1720 .name = "stm32f1x",
1721 .mode = COMMAND_ANY,
1722 .help = "stm32f1x flash command group",
1723 .usage = "",
1724 .chain = stm32f1x_exec_command_handlers,
1725 },
1726 COMMAND_REGISTRATION_DONE
1727 };
1728
1729 const struct flash_driver stm32f1x_flash = {
1730 .name = "stm32f1x",
1731 .commands = stm32f1x_command_handlers,
1732 .flash_bank_command = stm32x_flash_bank_command,
1733 .erase = stm32x_erase,
1734 .protect = stm32x_protect,
1735 .write = stm32x_write,
1736 .read = default_flash_read,
1737 .probe = stm32x_probe,
1738 .auto_probe = stm32x_auto_probe,
1739 .erase_check = default_flash_blank_check,
1740 .protect_check = stm32x_protect_check,
1741 .info = get_stm32x_info,
1742 .free_driver_priv = default_flash_free_driver_priv,
1743 };
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