target/cortex_m: workaround Cortex-M7 erratum 3092511
[openocd.git] / src / flash / nand / mxc.h
blobae2c03a758a00dd39314b41e53e82eed6a7c26a9
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2009 by Alexei Babich *
5 * Rezonans plc., Chelyabinsk, Russia *
6 * impatt@mail.ru *
7 * *
8 * Copyright (C) 2011 by Erik Ahlen *
9 * Avalon Innovation, Sweden *
10 ***************************************************************************/
12 #ifndef OPENOCD_FLASH_NAND_MXC_H
13 #define OPENOCD_FLASH_NAND_MXC_H
16 * Freescale iMX OpenOCD NAND Flash controller support.
17 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
19 * Many thanks to Ben Dooks for writing s3c24xx driver.
22 #define MXC_NF_BUFSIZ (mxc_nf_info->mxc_regs_addr + 0x00)
23 #define MXC_NF_BUFADDR (mxc_nf_info->mxc_regs_addr + 0x04)
24 #define MXC_NF_FADDR (mxc_nf_info->mxc_regs_addr + 0x06)
25 #define MXC_NF_FCMD (mxc_nf_info->mxc_regs_addr + 0x08)
26 #define MXC_NF_BUFCFG (mxc_nf_info->mxc_regs_addr + 0x0a)
27 #define MXC_NF_ECCSTATUS (mxc_nf_info->mxc_regs_addr + 0x0c)
28 #define MXC_NF_ECCMAINPOS (mxc_nf_info->mxc_regs_addr + 0x0e)
29 #define MXC_NF_V1_ECCSPAREPOS (mxc_nf_info->mxc_regs_addr + 0x10)
30 #define MXC_NF_V2_SPAS (mxc_nf_info->mxc_regs_addr + 0x10)
31 #define MXC_NF_FWP (mxc_nf_info->mxc_regs_addr + 0x12)
32 #define MXC_NF_V1_UNLOCKSTART (mxc_nf_info->mxc_regs_addr + 0x14)
33 #define MXC_NF_V1_UNLOCKEND (mxc_nf_info->mxc_regs_addr + 0x16)
34 #define MXC_NF_V2_UNLOCKSTART0 (mxc_nf_info->mxc_regs_addr + 0x20)
35 #define MXC_NF_V2_UNLOCKSTART1 (mxc_nf_info->mxc_regs_addr + 0x24)
36 #define MXC_NF_V2_UNLOCKSTART2 (mxc_nf_info->mxc_regs_addr + 0x28)
37 #define MXC_NF_V2_UNLOCKSTART3 (mxc_nf_info->mxc_regs_addr + 0x2c)
38 #define MXC_NF_V2_UNLOCKEND0 (mxc_nf_info->mxc_regs_addr + 0x22)
39 #define MXC_NF_V2_UNLOCKEND1 (mxc_nf_info->mxc_regs_addr + 0x26)
40 #define MXC_NF_V2_UNLOCKEND2 (mxc_nf_info->mxc_regs_addr + 0x2a)
41 #define MXC_NF_V2_UNLOCKEND3 (mxc_nf_info->mxc_regs_addr + 0x2e)
42 #define MXC_NF_FWPSTATUS (mxc_nf_info->mxc_regs_addr + 0x18)
44 * all bits not marked as self-clearing bit
46 #define MXC_NF_CFG1 (mxc_nf_info->mxc_regs_addr + 0x1a)
47 #define MXC_NF_CFG2 (mxc_nf_info->mxc_regs_addr + 0x1c)
49 #define MXC_NF_MAIN_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0000)
50 #define MXC_NF_MAIN_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0200)
51 #define MXC_NF_MAIN_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0400)
52 #define MXC_NF_MAIN_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0600)
53 #define MXC_NF_V1_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0800)
54 #define MXC_NF_V1_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0810)
55 #define MXC_NF_V1_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0820)
56 #define MXC_NF_V1_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0830)
57 #define MXC_NF_V2_MAIN_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x0800)
58 #define MXC_NF_V2_MAIN_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x0a00)
59 #define MXC_NF_V2_MAIN_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x0c00)
60 #define MXC_NF_V2_MAIN_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x0e00)
61 #define MXC_NF_V2_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x1000)
62 #define MXC_NF_V2_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x1040)
63 #define MXC_NF_V2_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x1080)
64 #define MXC_NF_V2_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x10c0)
65 #define MXC_NF_V2_SPARE_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x1100)
66 #define MXC_NF_V2_SPARE_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x1140)
67 #define MXC_NF_V2_SPARE_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x1180)
68 #define MXC_NF_V2_SPARE_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x11c0)
69 #define MXC_NF_MAIN_BUFFER_LEN 512
70 #define MXC_NF_SPARE_BUFFER_LEN 16
71 #define MXC_NF_SPARE_BUFFER_MAX 64
72 #define MXC_NF_V1_LAST_BUFFADDR ((MXC_NF_V1_SPARE_BUFFER3) + \
73 MXC_NF_SPARE_BUFFER_LEN - 2)
74 #define MXC_NF_V2_LAST_BUFFADDR ((MXC_NF_V2_SPARE_BUFFER7) + \
75 MXC_NF_SPARE_BUFFER_LEN - 2)
77 /* bits in MXC_NF_CFG1 register */
78 #define MXC_NF_BIT_ECC_4BIT (1<<0)
79 #define MXC_NF_BIT_SPARE_ONLY_EN (1<<2)
80 #define MXC_NF_BIT_ECC_EN (1<<3)
81 #define MXC_NF_BIT_INT_DIS (1<<4)
82 #define MXC_NF_BIT_BE_EN (1<<5)
83 #define MXC_NF_BIT_RESET_EN (1<<6)
84 #define MXC_NF_BIT_FORCE_CE (1<<7)
85 #define MXC_NF_V2_CFG1_PPB(x) (((x) & 0x3) << 9)
87 /* bits in MXC_NF_CFG2 register */
89 /*Flash Command Input*/
90 #define MXC_NF_BIT_OP_FCI (1<<0)
92 * Flash Address Input
94 #define MXC_NF_BIT_OP_FAI (1<<1)
96 * Flash Data Input
98 #define MXC_NF_BIT_OP_FDI (1<<2)
100 /* see "enum mx_dataout_type" below */
101 #define MXC_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
102 #define MXC_NF_BIT_OP_DONE (1<<15)
104 #define MXC_CCM_CGR2 0x53f80028
105 #define MXC_GPR 0x43fac008
106 #define MX2_FMCR 0x10027814
107 #define MX2_FMCR_NF_16BIT_SEL (1<<4)
108 #define MX2_FMCR_NF_FMS (1<<5)
109 #define MX25_RCSR 0x53f80018
110 #define MX25_RCSR_NF_16BIT_SEL (1<<14)
111 #define MX25_RCSR_NF_FMS (1<<8)
112 #define MX25_RCSR_NF_4K (1<<9)
113 #define MX3_PCSR 0x53f8000c
114 #define MX3_PCSR_NF_16BIT_SEL (1<<31)
115 #define MX3_PCSR_NF_FMS (1<<30)
116 #define MX35_RCSR 0x53f80018
117 #define MX35_RCSR_NF_16BIT_SEL (1<<14)
118 #define MX35_RCSR_NF_FMS (1<<8)
119 #define MX35_RCSR_NF_4K (1<<9)
121 enum mxc_version {
122 MXC_VERSION_UKWN = 0,
123 MXC_VERSION_MX25 = 1,
124 MXC_VERSION_MX27 = 2,
125 MXC_VERSION_MX31 = 3,
126 MXC_VERSION_MX35 = 4
129 enum mxc_dataout_type {
130 MXC_NF_DATAOUT_PAGE = 1,
131 MXC_NF_DATAOUT_NANDID = 2,
132 MXC_NF_DATAOUT_NANDSTATUS = 4,
135 enum mxc_nf_finalize_action {
136 MXC_NF_FIN_NONE,
137 MXC_NF_FIN_DATAOUT,
140 struct mxc_nf_flags {
141 unsigned target_little_endian:1;
142 unsigned nand_readonly:1;
143 unsigned one_kb_sram:1;
144 unsigned hw_ecc_enabled:1;
145 unsigned biswap_enabled:1;
148 struct mxc_nf_controller {
149 enum mxc_version mxc_version;
150 uint32_t mxc_base_addr;
151 uint32_t mxc_regs_addr;
152 enum mxc_dataout_type optype;
153 enum mxc_nf_finalize_action fin;
154 struct mxc_nf_flags flags;
157 #endif /* OPENOCD_FLASH_NAND_MXC_H */