1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "target_type.h"
32 #include "arm7_9_common.h"
33 #include "arm_simulator.h"
34 #include "arm_disassembler.h"
35 #include "time_support.h"
40 * Important XScale documents available as of October 2009 include:
42 * Intel XScale® Core Developer’s Manual, January 2004
43 * Order Number: 273473-002
44 * This has a chapter detailing debug facilities, and punts some
45 * details to chip-specific microarchitecture documentats.
47 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
48 * Document Number: 273539-005
49 * Less detailed than the developer's manual, but summarizes those
50 * missing details (for most XScales) and gives LOTS of notes about
51 * debugger/handler interaction issues. Presents a simpler reset
52 * and load-handler sequence than the arch doc. (Note, OpenOCD
53 * doesn't currently support "Hot-Debug" as defined there.)
55 * Chip-specific microarchitecture documents may also be useful.
59 /* forward declarations */
60 static int xscale_resume(struct target_s
*, int current
,
61 uint32_t address
, int handle_breakpoints
, int debug_execution
);
62 static int xscale_debug_entry(target_t
*);
63 static int xscale_restore_context(target_t
*);
64 static int xscale_get_reg(reg_t
*reg
);
65 static int xscale_set_reg(reg_t
*reg
, uint8_t *buf
);
66 static int xscale_set_breakpoint(struct target_s
*, breakpoint_t
*);
67 static int xscale_set_watchpoint(struct target_s
*, watchpoint_t
*);
68 static int xscale_unset_breakpoint(struct target_s
*, breakpoint_t
*);
69 static int xscale_read_trace(target_t
*);
72 static char *const xscale_reg_list
[] =
74 "XSCALE_MAINID", /* 0 */
84 "XSCALE_IBCR0", /* 10 */
98 static const xscale_reg_t xscale_reg_arch_info
[] =
100 {XSCALE_MAINID
, NULL
},
101 {XSCALE_CACHETYPE
, NULL
},
103 {XSCALE_AUXCTRL
, NULL
},
109 {XSCALE_CPACCESS
, NULL
},
110 {XSCALE_IBCR0
, NULL
},
111 {XSCALE_IBCR1
, NULL
},
114 {XSCALE_DBCON
, NULL
},
115 {XSCALE_TBREG
, NULL
},
116 {XSCALE_CHKPT0
, NULL
},
117 {XSCALE_CHKPT1
, NULL
},
118 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
119 {-1, NULL
}, /* TX accessed via JTAG */
120 {-1, NULL
}, /* RX accessed via JTAG */
121 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
124 static int xscale_reg_arch_type
= -1;
126 /* convenience wrapper to access XScale specific registers */
127 static int xscale_set_reg_u32(reg_t
*reg
, uint32_t value
)
131 buf_set_u32(buf
, 0, 32, value
);
133 return xscale_set_reg(reg
, buf
);
137 static int xscale_get_arch_pointers(target_t
*target
,
138 armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
140 armv4_5_common_t
*armv4_5
= target
->arch_info
;
141 xscale_common_t
*xscale
= armv4_5
->arch_info
;
143 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
145 LOG_ERROR("target isn't an XScale target");
149 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
151 LOG_ERROR("target isn't an XScale target");
155 *armv4_5_p
= armv4_5
;
161 static int xscale_jtag_set_instr(jtag_tap_t
*tap
, uint32_t new_instr
)
166 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
171 field
.num_bits
= tap
->ir_length
;
172 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
173 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
176 field
.in_value
= tmp
;
178 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
180 /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
181 jtag_check_value_mask(&field
, tap
->expected
, tap
->expected_mask
);
183 free(field
.out_value
);
189 static int xscale_read_dcsr(target_t
*target
)
191 armv4_5_common_t
*armv4_5
= target
->arch_info
;
192 xscale_common_t
*xscale
= armv4_5
->arch_info
;
196 scan_field_t fields
[3];
197 uint8_t field0
= 0x0;
198 uint8_t field0_check_value
= 0x2;
199 uint8_t field0_check_mask
= 0x7;
200 uint8_t field2
= 0x0;
201 uint8_t field2_check_value
= 0x0;
202 uint8_t field2_check_mask
= 0x1;
204 jtag_set_end_state(TAP_DRPAUSE
);
205 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
207 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
208 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
210 fields
[0].tap
= target
->tap
;
211 fields
[0].num_bits
= 3;
212 fields
[0].out_value
= &field0
;
214 fields
[0].in_value
= &tmp
;
216 fields
[1].tap
= target
->tap
;
217 fields
[1].num_bits
= 32;
218 fields
[1].out_value
= NULL
;
219 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
221 fields
[2].tap
= target
->tap
;
222 fields
[2].num_bits
= 1;
223 fields
[2].out_value
= &field2
;
225 fields
[2].in_value
= &tmp2
;
227 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
229 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
230 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
232 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
234 LOG_ERROR("JTAG error while reading DCSR");
238 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
239 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
241 /* write the register with the value we just read
242 * on this second pass, only the first bit of field0 is guaranteed to be 0)
244 field0_check_mask
= 0x1;
245 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
246 fields
[1].in_value
= NULL
;
248 jtag_set_end_state(TAP_IDLE
);
250 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
252 /* DANGER!!! this must be here. It will make sure that the arguments
253 * to jtag_set_check_value() does not go out of scope! */
254 return jtag_execute_queue();
258 static void xscale_getbuf(jtag_callback_data_t arg
)
260 uint8_t *in
= (uint8_t *)arg
;
261 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
264 static int xscale_receive(target_t
*target
, uint32_t *buffer
, int num_words
)
267 return ERROR_INVALID_ARGUMENTS
;
269 int retval
= ERROR_OK
;
271 scan_field_t fields
[3];
272 uint8_t *field0
= malloc(num_words
* 1);
273 uint8_t field0_check_value
= 0x2;
274 uint8_t field0_check_mask
= 0x6;
275 uint32_t *field1
= malloc(num_words
* 4);
276 uint8_t field2_check_value
= 0x0;
277 uint8_t field2_check_mask
= 0x1;
279 int words_scheduled
= 0;
283 path
[0] = TAP_DRSELECT
;
284 path
[1] = TAP_DRCAPTURE
;
285 path
[2] = TAP_DRSHIFT
;
287 fields
[0].tap
= target
->tap
;
288 fields
[0].num_bits
= 3;
289 fields
[0].out_value
= NULL
;
290 fields
[0].in_value
= NULL
;
291 fields
[0].check_value
= &field0_check_value
;
292 fields
[0].check_mask
= &field0_check_mask
;
294 fields
[1].tap
= target
->tap
;
295 fields
[1].num_bits
= 32;
296 fields
[1].out_value
= NULL
;
297 fields
[1].check_value
= NULL
;
298 fields
[1].check_mask
= NULL
;
300 fields
[2].tap
= target
->tap
;
301 fields
[2].num_bits
= 1;
302 fields
[2].out_value
= NULL
;
303 fields
[2].in_value
= NULL
;
304 fields
[2].check_value
= &field2_check_value
;
305 fields
[2].check_mask
= &field2_check_mask
;
307 jtag_set_end_state(TAP_IDLE
);
308 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGTX
);
309 jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
311 /* repeat until all words have been collected */
313 while (words_done
< num_words
)
317 for (i
= words_done
; i
< num_words
; i
++)
319 fields
[0].in_value
= &field0
[i
];
321 jtag_add_pathmove(3, path
);
323 fields
[1].in_value
= (uint8_t *)(field1
+ i
);
325 jtag_add_dr_scan_check(3, fields
, jtag_set_end_state(TAP_IDLE
));
327 jtag_add_callback(xscale_getbuf
, (jtag_callback_data_t
)(field1
+ i
));
332 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
334 LOG_ERROR("JTAG error while receiving data from debug handler");
338 /* examine results */
339 for (i
= words_done
; i
< num_words
; i
++)
341 if (!(field0
[0] & 1))
343 /* move backwards if necessary */
345 for (j
= i
; j
< num_words
- 1; j
++)
347 field0
[j
] = field0
[j
+ 1];
348 field1
[j
] = field1
[j
+ 1];
353 if (words_scheduled
== 0)
355 if (attempts
++==1000)
357 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
358 retval
= ERROR_TARGET_TIMEOUT
;
363 words_done
+= words_scheduled
;
366 for (i
= 0; i
< num_words
; i
++)
367 *(buffer
++) = buf_get_u32((uint8_t*)&field1
[i
], 0, 32);
374 static int xscale_read_tx(target_t
*target
, int consume
)
376 armv4_5_common_t
*armv4_5
= target
->arch_info
;
377 xscale_common_t
*xscale
= armv4_5
->arch_info
;
379 tap_state_t noconsume_path
[6];
382 struct timeval timeout
, now
;
384 scan_field_t fields
[3];
385 uint8_t field0_in
= 0x0;
386 uint8_t field0_check_value
= 0x2;
387 uint8_t field0_check_mask
= 0x6;
388 uint8_t field2_check_value
= 0x0;
389 uint8_t field2_check_mask
= 0x1;
391 jtag_set_end_state(TAP_IDLE
);
393 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGTX
);
395 path
[0] = TAP_DRSELECT
;
396 path
[1] = TAP_DRCAPTURE
;
397 path
[2] = TAP_DRSHIFT
;
399 noconsume_path
[0] = TAP_DRSELECT
;
400 noconsume_path
[1] = TAP_DRCAPTURE
;
401 noconsume_path
[2] = TAP_DREXIT1
;
402 noconsume_path
[3] = TAP_DRPAUSE
;
403 noconsume_path
[4] = TAP_DREXIT2
;
404 noconsume_path
[5] = TAP_DRSHIFT
;
406 fields
[0].tap
= target
->tap
;
407 fields
[0].num_bits
= 3;
408 fields
[0].out_value
= NULL
;
409 fields
[0].in_value
= &field0_in
;
411 fields
[1].tap
= target
->tap
;
412 fields
[1].num_bits
= 32;
413 fields
[1].out_value
= NULL
;
414 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
416 fields
[2].tap
= target
->tap
;
417 fields
[2].num_bits
= 1;
418 fields
[2].out_value
= NULL
;
420 fields
[2].in_value
= &tmp
;
422 gettimeofday(&timeout
, NULL
);
423 timeval_add_time(&timeout
, 1, 0);
427 /* if we want to consume the register content (i.e. clear TX_READY),
428 * we have to go straight from Capture-DR to Shift-DR
429 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
432 jtag_add_pathmove(3, path
);
435 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
438 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
440 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
441 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
443 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
445 LOG_ERROR("JTAG error while reading TX");
446 return ERROR_TARGET_TIMEOUT
;
449 gettimeofday(&now
, NULL
);
450 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
452 LOG_ERROR("time out reading TX register");
453 return ERROR_TARGET_TIMEOUT
;
455 if (!((!(field0_in
& 1)) && consume
))
459 if (debug_level
>= 3)
461 LOG_DEBUG("waiting 100ms");
462 alive_sleep(100); /* avoid flooding the logs */
470 if (!(field0_in
& 1))
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
476 static int xscale_write_rx(target_t
*target
)
478 armv4_5_common_t
*armv4_5
= target
->arch_info
;
479 xscale_common_t
*xscale
= armv4_5
->arch_info
;
482 struct timeval timeout
, now
;
484 scan_field_t fields
[3];
485 uint8_t field0_out
= 0x0;
486 uint8_t field0_in
= 0x0;
487 uint8_t field0_check_value
= 0x2;
488 uint8_t field0_check_mask
= 0x6;
489 uint8_t field2
= 0x0;
490 uint8_t field2_check_value
= 0x0;
491 uint8_t field2_check_mask
= 0x1;
493 jtag_set_end_state(TAP_IDLE
);
495 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGRX
);
497 fields
[0].tap
= target
->tap
;
498 fields
[0].num_bits
= 3;
499 fields
[0].out_value
= &field0_out
;
500 fields
[0].in_value
= &field0_in
;
502 fields
[1].tap
= target
->tap
;
503 fields
[1].num_bits
= 32;
504 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
505 fields
[1].in_value
= NULL
;
507 fields
[2].tap
= target
->tap
;
508 fields
[2].num_bits
= 1;
509 fields
[2].out_value
= &field2
;
511 fields
[2].in_value
= &tmp
;
513 gettimeofday(&timeout
, NULL
);
514 timeval_add_time(&timeout
, 1, 0);
516 /* poll until rx_read is low */
517 LOG_DEBUG("polling RX");
520 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
522 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
523 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
525 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
527 LOG_ERROR("JTAG error while writing RX");
531 gettimeofday(&now
, NULL
);
532 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
534 LOG_ERROR("time out writing RX register");
535 return ERROR_TARGET_TIMEOUT
;
537 if (!(field0_in
& 1))
539 if (debug_level
>= 3)
541 LOG_DEBUG("waiting 100ms");
542 alive_sleep(100); /* avoid flooding the logs */
552 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
554 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
556 LOG_ERROR("JTAG error while writing RX");
563 /* send count elements of size byte to the debug handler */
564 static int xscale_send(target_t
*target
, uint8_t *buffer
, int count
, int size
)
571 jtag_set_end_state(TAP_IDLE
);
573 xscale_jtag_set_instr(target
->tap
, XSCALE_DBGRX
);
580 int endianness
= target
->endianness
;
581 while (done_count
++ < count
)
586 if (endianness
== TARGET_LITTLE_ENDIAN
)
588 t
[1]=le_to_h_u32(buffer
);
591 t
[1]=be_to_h_u32(buffer
);
595 if (endianness
== TARGET_LITTLE_ENDIAN
)
597 t
[1]=le_to_h_u16(buffer
);
600 t
[1]=be_to_h_u16(buffer
);
607 LOG_ERROR("BUG: size neither 4, 2 nor 1");
610 jtag_add_dr_out(target
->tap
,
614 jtag_set_end_state(TAP_IDLE
));
618 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
620 LOG_ERROR("JTAG error while sending data to debug handler");
627 static int xscale_send_u32(target_t
*target
, uint32_t value
)
629 armv4_5_common_t
*armv4_5
= target
->arch_info
;
630 xscale_common_t
*xscale
= armv4_5
->arch_info
;
632 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
633 return xscale_write_rx(target
);
636 static int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
638 armv4_5_common_t
*armv4_5
= target
->arch_info
;
639 xscale_common_t
*xscale
= armv4_5
->arch_info
;
643 scan_field_t fields
[3];
644 uint8_t field0
= 0x0;
645 uint8_t field0_check_value
= 0x2;
646 uint8_t field0_check_mask
= 0x7;
647 uint8_t field2
= 0x0;
648 uint8_t field2_check_value
= 0x0;
649 uint8_t field2_check_mask
= 0x1;
652 xscale
->hold_rst
= hold_rst
;
654 if (ext_dbg_brk
!= -1)
655 xscale
->external_debug_break
= ext_dbg_brk
;
657 jtag_set_end_state(TAP_IDLE
);
658 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
660 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
661 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
663 fields
[0].tap
= target
->tap
;
664 fields
[0].num_bits
= 3;
665 fields
[0].out_value
= &field0
;
667 fields
[0].in_value
= &tmp
;
669 fields
[1].tap
= target
->tap
;
670 fields
[1].num_bits
= 32;
671 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
672 fields
[1].in_value
= NULL
;
674 fields
[2].tap
= target
->tap
;
675 fields
[2].num_bits
= 1;
676 fields
[2].out_value
= &field2
;
678 fields
[2].in_value
= &tmp2
;
680 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
682 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
683 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
685 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
687 LOG_ERROR("JTAG error while writing DCSR");
691 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
692 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
697 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
698 static unsigned int parity (unsigned int v
)
700 // unsigned int ov = v;
705 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
706 return (0x6996 >> v
) & 1;
709 static int xscale_load_ic(target_t
*target
, uint32_t va
, uint32_t buffer
[8])
714 scan_field_t fields
[2];
716 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32
"", va
);
719 jtag_set_end_state(TAP_IDLE
);
720 xscale_jtag_set_instr(target
->tap
, XSCALE_LDIC
);
722 /* CMD is b011 to load a cacheline into the Mini ICache.
723 * Loading into the main ICache is deprecated, and unused.
724 * It's followed by three zero bits, and 27 address bits.
726 buf_set_u32(&cmd
, 0, 6, 0x3);
728 /* virtual address of desired cache line */
729 buf_set_u32(packet
, 0, 27, va
>> 5);
731 fields
[0].tap
= target
->tap
;
732 fields
[0].num_bits
= 6;
733 fields
[0].out_value
= &cmd
;
734 fields
[0].in_value
= NULL
;
736 fields
[1].tap
= target
->tap
;
737 fields
[1].num_bits
= 27;
738 fields
[1].out_value
= packet
;
739 fields
[1].in_value
= NULL
;
741 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
743 /* rest of packet is a cacheline: 8 instructions, with parity */
744 fields
[0].num_bits
= 32;
745 fields
[0].out_value
= packet
;
747 fields
[1].num_bits
= 1;
748 fields
[1].out_value
= &cmd
;
750 for (word
= 0; word
< 8; word
++)
752 buf_set_u32(packet
, 0, 32, buffer
[word
]);
755 memcpy(&value
, packet
, sizeof(uint32_t));
758 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
761 return jtag_execute_queue();
764 static int xscale_invalidate_ic_line(target_t
*target
, uint32_t va
)
768 scan_field_t fields
[2];
770 jtag_set_end_state(TAP_IDLE
);
771 xscale_jtag_set_instr(target
->tap
, XSCALE_LDIC
);
773 /* CMD for invalidate IC line b000, bits [6:4] b000 */
774 buf_set_u32(&cmd
, 0, 6, 0x0);
776 /* virtual address of desired cache line */
777 buf_set_u32(packet
, 0, 27, va
>> 5);
779 fields
[0].tap
= target
->tap
;
780 fields
[0].num_bits
= 6;
781 fields
[0].out_value
= &cmd
;
782 fields
[0].in_value
= NULL
;
784 fields
[1].tap
= target
->tap
;
785 fields
[1].num_bits
= 27;
786 fields
[1].out_value
= packet
;
787 fields
[1].in_value
= NULL
;
789 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
794 static int xscale_update_vectors(target_t
*target
)
796 armv4_5_common_t
*armv4_5
= target
->arch_info
;
797 xscale_common_t
*xscale
= armv4_5
->arch_info
;
801 uint32_t low_reset_branch
, high_reset_branch
;
803 for (i
= 1; i
< 8; i
++)
805 /* if there's a static vector specified for this exception, override */
806 if (xscale
->static_high_vectors_set
& (1 << i
))
808 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
812 retval
= target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
813 if (retval
== ERROR_TARGET_TIMEOUT
)
815 if (retval
!= ERROR_OK
)
817 /* Some of these reads will fail as part of normal execution */
818 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
823 for (i
= 1; i
< 8; i
++)
825 if (xscale
->static_low_vectors_set
& (1 << i
))
827 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
831 retval
= target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
832 if (retval
== ERROR_TARGET_TIMEOUT
)
834 if (retval
!= ERROR_OK
)
836 /* Some of these reads will fail as part of normal execution */
837 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
842 /* calculate branches to debug handler */
843 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
844 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
846 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
847 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
849 /* invalidate and load exception vectors in mini i-cache */
850 xscale_invalidate_ic_line(target
, 0x0);
851 xscale_invalidate_ic_line(target
, 0xffff0000);
853 xscale_load_ic(target
, 0x0, xscale
->low_vectors
);
854 xscale_load_ic(target
, 0xffff0000, xscale
->high_vectors
);
859 static int xscale_arch_state(struct target_s
*target
)
861 armv4_5_common_t
*armv4_5
= target
->arch_info
;
862 xscale_common_t
*xscale
= armv4_5
->arch_info
;
864 static const char *state
[] =
866 "disabled", "enabled"
869 static const char *arch_dbg_reason
[] =
871 "", "\n(processor reset)", "\n(trace buffer full)"
874 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
876 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
880 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
881 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
882 "MMU: %s, D-Cache: %s, I-Cache: %s"
884 armv4_5_state_strings
[armv4_5
->core_state
],
885 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
886 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
887 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
888 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
889 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
890 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
891 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
892 arch_dbg_reason
[xscale
->arch_debug_reason
]);
897 static int xscale_poll(target_t
*target
)
899 int retval
= ERROR_OK
;
900 armv4_5_common_t
*armv4_5
= target
->arch_info
;
901 xscale_common_t
*xscale
= armv4_5
->arch_info
;
903 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
905 enum target_state previous_state
= target
->state
;
906 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
909 /* there's data to read from the tx register, we entered debug state */
910 xscale
->handler_running
= 1;
912 target
->state
= TARGET_HALTED
;
914 /* process debug entry, fetching current mode regs */
915 retval
= xscale_debug_entry(target
);
917 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
919 LOG_USER("error while polling TX register, reset CPU");
920 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
921 target
->state
= TARGET_HALTED
;
924 /* debug_entry could have overwritten target state (i.e. immediate resume)
925 * don't signal event handlers in that case
927 if (target
->state
!= TARGET_HALTED
)
930 /* if target was running, signal that we halted
931 * otherwise we reentered from debug execution */
932 if (previous_state
== TARGET_RUNNING
)
933 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
935 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
941 static int xscale_debug_entry(target_t
*target
)
943 armv4_5_common_t
*armv4_5
= target
->arch_info
;
944 xscale_common_t
*xscale
= armv4_5
->arch_info
;
952 /* clear external dbg break (will be written on next DCSR read) */
953 xscale
->external_debug_break
= 0;
954 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
957 /* get r0, pc, r1 to r7 and cpsr */
958 if ((retval
= xscale_receive(target
, buffer
, 10)) != ERROR_OK
)
961 /* move r0 from buffer to register cache */
962 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
963 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
964 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
965 LOG_DEBUG("r0: 0x%8.8" PRIx32
"", buffer
[0]);
967 /* move pc from buffer to register cache */
968 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
969 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
970 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
971 LOG_DEBUG("pc: 0x%8.8" PRIx32
"", buffer
[1]);
973 /* move data from buffer to register cache */
974 for (i
= 1; i
<= 7; i
++)
976 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
977 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
978 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
979 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, buffer
[i
+ 1]);
982 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
983 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
984 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
985 LOG_DEBUG("cpsr: 0x%8.8" PRIx32
"", buffer
[9]);
987 armv4_5
->core_mode
= buffer
[9] & 0x1f;
988 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
990 target
->state
= TARGET_UNKNOWN
;
991 LOG_ERROR("cpsr contains invalid mode value - communication failure");
992 return ERROR_TARGET_FAILURE
;
994 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
996 if (buffer
[9] & 0x20)
997 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
999 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1002 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1005 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1006 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1008 xscale_receive(target
, buffer
, 8);
1009 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1010 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1011 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1015 /* r8 to r14, but no spsr */
1016 xscale_receive(target
, buffer
, 7);
1019 /* move data from buffer to register cache */
1020 for (i
= 8; i
<= 14; i
++)
1022 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1023 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1024 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1027 /* examine debug reason */
1028 xscale_read_dcsr(target
);
1029 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1031 /* stored PC (for calculating fixup) */
1032 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1036 case 0x0: /* Processor reset */
1037 target
->debug_reason
= DBG_REASON_DBGRQ
;
1038 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1041 case 0x1: /* Instruction breakpoint hit */
1042 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1043 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1046 case 0x2: /* Data breakpoint hit */
1047 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1048 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1051 case 0x3: /* BKPT instruction executed */
1052 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1053 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1056 case 0x4: /* Ext. debug event */
1057 target
->debug_reason
= DBG_REASON_DBGRQ
;
1058 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1061 case 0x5: /* Vector trap occured */
1062 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1063 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1066 case 0x6: /* Trace buffer full break */
1067 target
->debug_reason
= DBG_REASON_DBGRQ
;
1068 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1071 case 0x7: /* Reserved (may flag Hot-Debug support) */
1073 LOG_ERROR("Method of Entry is 'Reserved'");
1078 /* apply PC fixup */
1079 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1081 /* on the first debug entry, identify cache type */
1082 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1084 uint32_t cache_type_reg
;
1086 /* read cp15 cache type register */
1087 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1088 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1090 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1093 /* examine MMU and Cache settings */
1094 /* read cp15 control register */
1095 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1096 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1097 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1098 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1099 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1101 /* tracing enabled, read collected trace data */
1102 if (xscale
->trace
.buffer_enabled
)
1104 xscale_read_trace(target
);
1105 xscale
->trace
.buffer_fill
--;
1107 /* resume if we're still collecting trace data */
1108 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1109 && (xscale
->trace
.buffer_fill
> 0))
1111 xscale_resume(target
, 1, 0x0, 1, 0);
1115 xscale
->trace
.buffer_enabled
= 0;
1122 static int xscale_halt(target_t
*target
)
1124 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1125 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1127 LOG_DEBUG("target->state: %s",
1128 target_state_name(target
));
1130 if (target
->state
== TARGET_HALTED
)
1132 LOG_DEBUG("target was already halted");
1135 else if (target
->state
== TARGET_UNKNOWN
)
1137 /* this must not happen for a xscale target */
1138 LOG_ERROR("target was in unknown state when halt was requested");
1139 return ERROR_TARGET_INVALID
;
1141 else if (target
->state
== TARGET_RESET
)
1143 LOG_DEBUG("target->state == TARGET_RESET");
1147 /* assert external dbg break */
1148 xscale
->external_debug_break
= 1;
1149 xscale_read_dcsr(target
);
1151 target
->debug_reason
= DBG_REASON_DBGRQ
;
1157 static int xscale_enable_single_step(struct target_s
*target
, uint32_t next_pc
)
1159 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1160 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1161 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1164 if (xscale
->ibcr0_used
)
1166 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1170 xscale_unset_breakpoint(target
, ibcr0_bp
);
1174 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1179 if ((retval
= xscale_set_reg_u32(ibcr0
, next_pc
| 0x1)) != ERROR_OK
)
1185 static int xscale_disable_single_step(struct target_s
*target
)
1187 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1188 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1189 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1192 if ((retval
= xscale_set_reg_u32(ibcr0
, 0x0)) != ERROR_OK
)
1198 static void xscale_enable_watchpoints(struct target_s
*target
)
1200 watchpoint_t
*watchpoint
= target
->watchpoints
;
1204 if (watchpoint
->set
== 0)
1205 xscale_set_watchpoint(target
, watchpoint
);
1206 watchpoint
= watchpoint
->next
;
1210 static void xscale_enable_breakpoints(struct target_s
*target
)
1212 breakpoint_t
*breakpoint
= target
->breakpoints
;
1214 /* set any pending breakpoints */
1217 if (breakpoint
->set
== 0)
1218 xscale_set_breakpoint(target
, breakpoint
);
1219 breakpoint
= breakpoint
->next
;
1223 static int xscale_resume(struct target_s
*target
, int current
,
1224 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1226 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1227 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1228 breakpoint_t
*breakpoint
= target
->breakpoints
;
1230 uint32_t current_pc
;
1237 if (target
->state
!= TARGET_HALTED
)
1239 LOG_WARNING("target not halted");
1240 return ERROR_TARGET_NOT_HALTED
;
1243 if (!debug_execution
)
1245 target_free_all_working_areas(target
);
1248 /* update vector tables */
1249 if ((retval
= xscale_update_vectors(target
)) != ERROR_OK
)
1252 /* current = 1: continue on current pc, otherwise continue at <address> */
1254 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1256 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1258 /* if we're at the reset vector, we have to simulate the branch */
1259 if (current_pc
== 0x0)
1261 arm_simulate_step(target
, NULL
);
1262 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1265 /* the front-end may request us not to handle breakpoints */
1266 if (handle_breakpoints
)
1268 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1272 /* there's a breakpoint at the current PC, we have to step over it */
1273 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1274 xscale_unset_breakpoint(target
, breakpoint
);
1276 /* calculate PC of next instruction */
1277 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1279 uint32_t current_opcode
;
1280 target_read_u32(target
, current_pc
, ¤t_opcode
);
1281 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1284 LOG_DEBUG("enable single-step");
1285 xscale_enable_single_step(target
, next_pc
);
1287 /* restore banked registers */
1288 xscale_restore_context(target
);
1290 /* send resume request (command 0x30 or 0x31)
1291 * clean the trace buffer if it is to be enabled (0x62) */
1292 if (xscale
->trace
.buffer_enabled
)
1294 xscale_send_u32(target
, 0x62);
1295 xscale_send_u32(target
, 0x31);
1298 xscale_send_u32(target
, 0x30);
1301 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1302 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1304 for (i
= 7; i
>= 0; i
--)
1307 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1308 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1312 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1313 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1315 /* wait for and process debug entry */
1316 xscale_debug_entry(target
);
1318 LOG_DEBUG("disable single-step");
1319 xscale_disable_single_step(target
);
1321 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1322 xscale_set_breakpoint(target
, breakpoint
);
1326 /* enable any pending breakpoints and watchpoints */
1327 xscale_enable_breakpoints(target
);
1328 xscale_enable_watchpoints(target
);
1330 /* restore banked registers */
1331 xscale_restore_context(target
);
1333 /* send resume request (command 0x30 or 0x31)
1334 * clean the trace buffer if it is to be enabled (0x62) */
1335 if (xscale
->trace
.buffer_enabled
)
1337 xscale_send_u32(target
, 0x62);
1338 xscale_send_u32(target
, 0x31);
1341 xscale_send_u32(target
, 0x30);
1344 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1345 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1347 for (i
= 7; i
>= 0; i
--)
1350 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1351 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1355 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1356 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1358 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1360 if (!debug_execution
)
1362 /* registers are now invalid */
1363 armv4_5_invalidate_core_regs(target
);
1364 target
->state
= TARGET_RUNNING
;
1365 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1369 target
->state
= TARGET_DEBUG_RUNNING
;
1370 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1373 LOG_DEBUG("target resumed");
1375 xscale
->handler_running
= 1;
1380 static int xscale_step_inner(struct target_s
*target
, int current
,
1381 uint32_t address
, int handle_breakpoints
)
1383 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1384 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1390 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1392 /* calculate PC of next instruction */
1393 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1395 uint32_t current_opcode
, current_pc
;
1396 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1398 target_read_u32(target
, current_pc
, ¤t_opcode
);
1399 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1403 LOG_DEBUG("enable single-step");
1404 if ((retval
= xscale_enable_single_step(target
, next_pc
)) != ERROR_OK
)
1407 /* restore banked registers */
1408 if ((retval
= xscale_restore_context(target
)) != ERROR_OK
)
1411 /* send resume request (command 0x30 or 0x31)
1412 * clean the trace buffer if it is to be enabled (0x62) */
1413 if (xscale
->trace
.buffer_enabled
)
1415 if ((retval
= xscale_send_u32(target
, 0x62)) != ERROR_OK
)
1417 if ((retval
= xscale_send_u32(target
, 0x31)) != ERROR_OK
)
1421 if ((retval
= xscale_send_u32(target
, 0x30)) != ERROR_OK
)
1425 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32))) != ERROR_OK
)
1427 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1429 for (i
= 7; i
>= 0; i
--)
1432 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32))) != ERROR_OK
)
1434 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1438 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))) != ERROR_OK
)
1440 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1442 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1444 /* registers are now invalid */
1445 if ((retval
= armv4_5_invalidate_core_regs(target
)) != ERROR_OK
)
1448 /* wait for and process debug entry */
1449 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
1452 LOG_DEBUG("disable single-step");
1453 if ((retval
= xscale_disable_single_step(target
)) != ERROR_OK
)
1456 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1461 static int xscale_step(struct target_s
*target
, int current
,
1462 uint32_t address
, int handle_breakpoints
)
1464 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1465 breakpoint_t
*breakpoint
= target
->breakpoints
;
1467 uint32_t current_pc
;
1470 if (target
->state
!= TARGET_HALTED
)
1472 LOG_WARNING("target not halted");
1473 return ERROR_TARGET_NOT_HALTED
;
1476 /* current = 1: continue on current pc, otherwise continue at <address> */
1478 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1480 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1482 /* if we're at the reset vector, we have to simulate the step */
1483 if (current_pc
== 0x0)
1485 if ((retval
= arm_simulate_step(target
, NULL
)) != ERROR_OK
)
1487 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1489 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1490 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1495 /* the front-end may request us not to handle breakpoints */
1496 if (handle_breakpoints
)
1497 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1499 if ((retval
= xscale_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1503 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1507 xscale_set_breakpoint(target
, breakpoint
);
1510 LOG_DEBUG("target stepped");
1516 static int xscale_assert_reset(target_t
*target
)
1518 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1519 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1521 LOG_DEBUG("target->state: %s",
1522 target_state_name(target
));
1524 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1525 * end up in T-L-R, which would reset JTAG
1527 jtag_set_end_state(TAP_IDLE
);
1528 xscale_jtag_set_instr(target
->tap
, XSCALE_SELDCSR
);
1530 /* set Hold reset, Halt mode and Trap Reset */
1531 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1532 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1533 xscale_write_dcsr(target
, 1, 0);
1535 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1536 xscale_jtag_set_instr(target
->tap
, 0x7f);
1537 jtag_execute_queue();
1540 jtag_add_reset(0, 1);
1542 /* sleep 1ms, to be sure we fulfill any requirements */
1543 jtag_add_sleep(1000);
1544 jtag_execute_queue();
1546 target
->state
= TARGET_RESET
;
1548 if (target
->reset_halt
)
1551 if ((retval
= target_halt(target
)) != ERROR_OK
)
1558 static int xscale_deassert_reset(target_t
*target
)
1560 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1561 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1563 fileio_t debug_handler
;
1565 uint32_t binary_size
;
1571 breakpoint_t
*breakpoint
= target
->breakpoints
;
1575 xscale
->ibcr_available
= 2;
1576 xscale
->ibcr0_used
= 0;
1577 xscale
->ibcr1_used
= 0;
1579 xscale
->dbr_available
= 2;
1580 xscale
->dbr0_used
= 0;
1581 xscale
->dbr1_used
= 0;
1583 /* mark all hardware breakpoints as unset */
1586 if (breakpoint
->type
== BKPT_HARD
)
1588 breakpoint
->set
= 0;
1590 breakpoint
= breakpoint
->next
;
1593 if (!xscale
->handler_installed
)
1596 jtag_add_reset(0, 0);
1598 /* wait 300ms; 150 and 100ms were not enough */
1599 jtag_add_sleep(300*1000);
1601 jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE
));
1602 jtag_execute_queue();
1604 /* set Hold reset, Halt mode and Trap Reset */
1605 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1606 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1607 xscale_write_dcsr(target
, 1, 0);
1609 /* Load debug handler */
1610 if (fileio_open(&debug_handler
, "xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1615 if ((binary_size
= debug_handler
.size
) % 4)
1617 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1621 if (binary_size
> 0x800)
1623 LOG_ERROR("debug_handler.bin: larger than 2kb");
1627 binary_size
= CEIL(binary_size
, 32) * 32;
1629 address
= xscale
->handler_address
;
1630 while (binary_size
> 0)
1632 uint32_t cache_line
[8];
1635 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1640 for (i
= 0; i
< buf_cnt
; i
+= 4)
1642 /* convert LE buffer to host-endian uint32_t */
1643 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1646 for (; i
< 32; i
+= 4)
1648 cache_line
[i
/ 4] = 0xe1a08008;
1651 /* only load addresses other than the reset vectors */
1652 if ((address
% 0x400) != 0x0)
1654 xscale_load_ic(target
, address
, cache_line
);
1658 binary_size
-= buf_cnt
;
1661 xscale_load_ic(target
, 0x0, xscale
->low_vectors
);
1662 xscale_load_ic(target
, 0xffff0000, xscale
->high_vectors
);
1664 jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE
));
1666 jtag_add_sleep(100000);
1668 /* set Hold reset, Halt mode and Trap Reset */
1669 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1670 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1671 xscale_write_dcsr(target
, 1, 0);
1673 /* clear Hold reset to let the target run (should enter debug handler) */
1674 xscale_write_dcsr(target
, 0, 1);
1675 target
->state
= TARGET_RUNNING
;
1677 if (!target
->reset_halt
)
1679 jtag_add_sleep(10000);
1681 /* we should have entered debug now */
1682 xscale_debug_entry(target
);
1683 target
->state
= TARGET_HALTED
;
1685 /* resume the target */
1686 xscale_resume(target
, 1, 0x0, 1, 0);
1689 fileio_close(&debug_handler
);
1693 jtag_add_reset(0, 0);
1699 static int xscale_read_core_reg(struct target_s
*target
, int num
,
1700 enum armv4_5_mode mode
)
1702 LOG_ERROR("not implemented");
1706 static int xscale_write_core_reg(struct target_s
*target
, int num
,
1707 enum armv4_5_mode mode
, uint32_t value
)
1709 LOG_ERROR("not implemented");
1713 static int xscale_full_context(target_t
*target
)
1715 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1723 if (target
->state
!= TARGET_HALTED
)
1725 LOG_WARNING("target not halted");
1726 return ERROR_TARGET_NOT_HALTED
;
1729 buffer
= malloc(4 * 8);
1731 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1732 * we can't enter User mode on an XScale (unpredictable),
1733 * but User shares registers with SYS
1735 for (i
= 1; i
< 7; i
++)
1739 /* check if there are invalid registers in the current mode
1741 for (j
= 0; j
<= 16; j
++)
1743 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1751 /* request banked registers */
1752 xscale_send_u32(target
, 0x0);
1755 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1756 tmp_cpsr
|= 0xc0; /* I/F bits */
1758 /* send CPSR for desired mode */
1759 xscale_send_u32(target
, tmp_cpsr
);
1761 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1762 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1764 xscale_receive(target
, buffer
, 8);
1765 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1766 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1767 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1771 xscale_receive(target
, buffer
, 7);
1774 /* move data from buffer to register cache */
1775 for (j
= 8; j
<= 14; j
++)
1777 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1778 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1779 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1789 static int xscale_restore_context(target_t
*target
)
1791 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1795 if (target
->state
!= TARGET_HALTED
)
1797 LOG_WARNING("target not halted");
1798 return ERROR_TARGET_NOT_HALTED
;
1801 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1802 * we can't enter User mode on an XScale (unpredictable),
1803 * but User shares registers with SYS
1805 for (i
= 1; i
< 7; i
++)
1809 /* check if there are invalid registers in the current mode
1811 for (j
= 8; j
<= 14; j
++)
1813 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1817 /* if not USR/SYS, check if the SPSR needs to be written */
1818 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1820 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1828 /* send banked registers */
1829 xscale_send_u32(target
, 0x1);
1832 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1833 tmp_cpsr
|= 0xc0; /* I/F bits */
1835 /* send CPSR for desired mode */
1836 xscale_send_u32(target
, tmp_cpsr
);
1838 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1839 for (j
= 8; j
<= 14; j
++)
1841 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1842 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1845 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1847 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1848 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1856 static int xscale_read_memory(struct target_s
*target
, uint32_t address
,
1857 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1859 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1860 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1865 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1867 if (target
->state
!= TARGET_HALTED
)
1869 LOG_WARNING("target not halted");
1870 return ERROR_TARGET_NOT_HALTED
;
1873 /* sanitize arguments */
1874 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1875 return ERROR_INVALID_ARGUMENTS
;
1877 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1878 return ERROR_TARGET_UNALIGNED_ACCESS
;
1880 /* send memory read request (command 0x1n, n: access size) */
1881 if ((retval
= xscale_send_u32(target
, 0x10 | size
)) != ERROR_OK
)
1884 /* send base address for read request */
1885 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1888 /* send number of requested data words */
1889 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1892 /* receive data from target (count times 32-bit words in host endianness) */
1893 buf32
= malloc(4 * count
);
1894 if ((retval
= xscale_receive(target
, buf32
, count
)) != ERROR_OK
)
1897 /* extract data from host-endian buffer into byte stream */
1898 for (i
= 0; i
< count
; i
++)
1903 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1907 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1911 *buffer
++ = buf32
[i
] & 0xff;
1914 LOG_ERROR("should never get here");
1921 /* examine DCSR, to see if Sticky Abort (SA) got set */
1922 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1924 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1927 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1930 return ERROR_TARGET_DATA_ABORT
;
1936 static int xscale_write_memory(struct target_s
*target
, uint32_t address
,
1937 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1939 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1940 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1943 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1945 if (target
->state
!= TARGET_HALTED
)
1947 LOG_WARNING("target not halted");
1948 return ERROR_TARGET_NOT_HALTED
;
1951 /* sanitize arguments */
1952 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1953 return ERROR_INVALID_ARGUMENTS
;
1955 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1956 return ERROR_TARGET_UNALIGNED_ACCESS
;
1958 /* send memory write request (command 0x2n, n: access size) */
1959 if ((retval
= xscale_send_u32(target
, 0x20 | size
)) != ERROR_OK
)
1962 /* send base address for read request */
1963 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1966 /* send number of requested data words to be written*/
1967 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1970 /* extract data from host-endian buffer into byte stream */
1972 for (i
= 0; i
< count
; i
++)
1977 value
= target_buffer_get_u32(target
, buffer
);
1978 xscale_send_u32(target
, value
);
1982 value
= target_buffer_get_u16(target
, buffer
);
1983 xscale_send_u32(target
, value
);
1988 xscale_send_u32(target
, value
);
1992 LOG_ERROR("should never get here");
1997 if ((retval
= xscale_send(target
, buffer
, count
, size
)) != ERROR_OK
)
2000 /* examine DCSR, to see if Sticky Abort (SA) got set */
2001 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
2003 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2006 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
2009 return ERROR_TARGET_DATA_ABORT
;
2015 static int xscale_bulk_write_memory(target_t
*target
, uint32_t address
,
2016 uint32_t count
, uint8_t *buffer
)
2018 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2021 static uint32_t xscale_get_ttb(target_t
*target
)
2023 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2024 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2027 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2028 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2033 static void xscale_disable_mmu_caches(target_t
*target
, int mmu
,
2034 int d_u_cache
, int i_cache
)
2036 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2037 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2038 uint32_t cp15_control
;
2040 /* read cp15 control register */
2041 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2042 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2045 cp15_control
&= ~0x1U
;
2050 xscale_send_u32(target
, 0x50);
2051 xscale_send_u32(target
, xscale
->cache_clean_address
);
2053 /* invalidate DCache */
2054 xscale_send_u32(target
, 0x51);
2056 cp15_control
&= ~0x4U
;
2061 /* invalidate ICache */
2062 xscale_send_u32(target
, 0x52);
2063 cp15_control
&= ~0x1000U
;
2066 /* write new cp15 control register */
2067 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2069 /* execute cpwait to ensure outstanding operations complete */
2070 xscale_send_u32(target
, 0x53);
2073 static void xscale_enable_mmu_caches(target_t
*target
, int mmu
,
2074 int d_u_cache
, int i_cache
)
2076 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2077 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2078 uint32_t cp15_control
;
2080 /* read cp15 control register */
2081 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2082 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2085 cp15_control
|= 0x1U
;
2088 cp15_control
|= 0x4U
;
2091 cp15_control
|= 0x1000U
;
2093 /* write new cp15 control register */
2094 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2096 /* execute cpwait to ensure outstanding operations complete */
2097 xscale_send_u32(target
, 0x53);
2100 static int xscale_set_breakpoint(struct target_s
*target
,
2101 breakpoint_t
*breakpoint
)
2104 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2105 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2107 if (target
->state
!= TARGET_HALTED
)
2109 LOG_WARNING("target not halted");
2110 return ERROR_TARGET_NOT_HALTED
;
2113 if (breakpoint
->set
)
2115 LOG_WARNING("breakpoint already set");
2119 if (breakpoint
->type
== BKPT_HARD
)
2121 uint32_t value
= breakpoint
->address
| 1;
2122 if (!xscale
->ibcr0_used
)
2124 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2125 xscale
->ibcr0_used
= 1;
2126 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2128 else if (!xscale
->ibcr1_used
)
2130 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2131 xscale
->ibcr1_used
= 1;
2132 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2136 LOG_ERROR("BUG: no hardware comparator available");
2140 else if (breakpoint
->type
== BKPT_SOFT
)
2142 if (breakpoint
->length
== 4)
2144 /* keep the original instruction in target endianness */
2145 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2149 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2150 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2157 /* keep the original instruction in target endianness */
2158 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2162 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2163 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2168 breakpoint
->set
= 1;
2174 static int xscale_add_breakpoint(struct target_s
*target
,
2175 breakpoint_t
*breakpoint
)
2177 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2178 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2180 if (target
->state
!= TARGET_HALTED
)
2182 LOG_WARNING("target not halted");
2183 return ERROR_TARGET_NOT_HALTED
;
2186 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2188 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2189 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2192 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2194 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2195 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2198 if (breakpoint
->type
== BKPT_HARD
)
2200 xscale
->ibcr_available
--;
2206 static int xscale_unset_breakpoint(struct target_s
*target
,
2207 breakpoint_t
*breakpoint
)
2210 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2211 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2213 if (target
->state
!= TARGET_HALTED
)
2215 LOG_WARNING("target not halted");
2216 return ERROR_TARGET_NOT_HALTED
;
2219 if (!breakpoint
->set
)
2221 LOG_WARNING("breakpoint not set");
2225 if (breakpoint
->type
== BKPT_HARD
)
2227 if (breakpoint
->set
== 1)
2229 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2230 xscale
->ibcr0_used
= 0;
2232 else if (breakpoint
->set
== 2)
2234 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2235 xscale
->ibcr1_used
= 0;
2237 breakpoint
->set
= 0;
2241 /* restore original instruction (kept in target endianness) */
2242 if (breakpoint
->length
== 4)
2244 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2251 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2256 breakpoint
->set
= 0;
2262 static int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2264 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2265 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2267 if (target
->state
!= TARGET_HALTED
)
2269 LOG_WARNING("target not halted");
2270 return ERROR_TARGET_NOT_HALTED
;
2273 if (breakpoint
->set
)
2275 xscale_unset_breakpoint(target
, breakpoint
);
2278 if (breakpoint
->type
== BKPT_HARD
)
2279 xscale
->ibcr_available
++;
2284 static int xscale_set_watchpoint(struct target_s
*target
,
2285 watchpoint_t
*watchpoint
)
2287 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2288 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2290 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2291 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2293 if (target
->state
!= TARGET_HALTED
)
2295 LOG_WARNING("target not halted");
2296 return ERROR_TARGET_NOT_HALTED
;
2299 xscale_get_reg(dbcon
);
2301 switch (watchpoint
->rw
)
2313 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2316 if (!xscale
->dbr0_used
)
2318 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2319 dbcon_value
|= enable
;
2320 xscale_set_reg_u32(dbcon
, dbcon_value
);
2321 watchpoint
->set
= 1;
2322 xscale
->dbr0_used
= 1;
2324 else if (!xscale
->dbr1_used
)
2326 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2327 dbcon_value
|= enable
<< 2;
2328 xscale_set_reg_u32(dbcon
, dbcon_value
);
2329 watchpoint
->set
= 2;
2330 xscale
->dbr1_used
= 1;
2334 LOG_ERROR("BUG: no hardware comparator available");
2341 static int xscale_add_watchpoint(struct target_s
*target
,
2342 watchpoint_t
*watchpoint
)
2344 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2345 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2347 if (target
->state
!= TARGET_HALTED
)
2349 LOG_WARNING("target not halted");
2350 return ERROR_TARGET_NOT_HALTED
;
2353 if (xscale
->dbr_available
< 1)
2355 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2358 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2360 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2363 xscale
->dbr_available
--;
2368 static int xscale_unset_watchpoint(struct target_s
*target
,
2369 watchpoint_t
*watchpoint
)
2371 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2372 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2373 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2374 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2376 if (target
->state
!= TARGET_HALTED
)
2378 LOG_WARNING("target not halted");
2379 return ERROR_TARGET_NOT_HALTED
;
2382 if (!watchpoint
->set
)
2384 LOG_WARNING("breakpoint not set");
2388 if (watchpoint
->set
== 1)
2390 dbcon_value
&= ~0x3;
2391 xscale_set_reg_u32(dbcon
, dbcon_value
);
2392 xscale
->dbr0_used
= 0;
2394 else if (watchpoint
->set
== 2)
2396 dbcon_value
&= ~0xc;
2397 xscale_set_reg_u32(dbcon
, dbcon_value
);
2398 xscale
->dbr1_used
= 0;
2400 watchpoint
->set
= 0;
2405 static int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2407 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2408 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2410 if (target
->state
!= TARGET_HALTED
)
2412 LOG_WARNING("target not halted");
2413 return ERROR_TARGET_NOT_HALTED
;
2416 if (watchpoint
->set
)
2418 xscale_unset_watchpoint(target
, watchpoint
);
2421 xscale
->dbr_available
++;
2426 static int xscale_get_reg(reg_t
*reg
)
2428 xscale_reg_t
*arch_info
= reg
->arch_info
;
2429 target_t
*target
= arch_info
->target
;
2430 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2431 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2433 /* DCSR, TX and RX are accessible via JTAG */
2434 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2436 return xscale_read_dcsr(arch_info
->target
);
2438 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2440 /* 1 = consume register content */
2441 return xscale_read_tx(arch_info
->target
, 1);
2443 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2445 /* can't read from RX register (host -> debug handler) */
2448 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2450 /* can't (explicitly) read from TXRXCTRL register */
2453 else /* Other DBG registers have to be transfered by the debug handler */
2455 /* send CP read request (command 0x40) */
2456 xscale_send_u32(target
, 0x40);
2458 /* send CP register number */
2459 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2461 /* read register value */
2462 xscale_read_tx(target
, 1);
2463 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2472 static int xscale_set_reg(reg_t
*reg
, uint8_t* buf
)
2474 xscale_reg_t
*arch_info
= reg
->arch_info
;
2475 target_t
*target
= arch_info
->target
;
2476 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2477 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2478 uint32_t value
= buf_get_u32(buf
, 0, 32);
2480 /* DCSR, TX and RX are accessible via JTAG */
2481 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2483 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2484 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2486 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2488 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2489 return xscale_write_rx(arch_info
->target
);
2491 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2493 /* can't write to TX register (debug-handler -> host) */
2496 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2498 /* can't (explicitly) write to TXRXCTRL register */
2501 else /* Other DBG registers have to be transfered by the debug handler */
2503 /* send CP write request (command 0x41) */
2504 xscale_send_u32(target
, 0x41);
2506 /* send CP register number */
2507 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2509 /* send CP register value */
2510 xscale_send_u32(target
, value
);
2511 buf_set_u32(reg
->value
, 0, 32, value
);
2517 static int xscale_write_dcsr_sw(target_t
*target
, uint32_t value
)
2519 /* get pointers to arch-specific information */
2520 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2521 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2522 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2523 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2525 /* send CP write request (command 0x41) */
2526 xscale_send_u32(target
, 0x41);
2528 /* send CP register number */
2529 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2531 /* send CP register value */
2532 xscale_send_u32(target
, value
);
2533 buf_set_u32(dcsr
->value
, 0, 32, value
);
2538 static int xscale_read_trace(target_t
*target
)
2540 /* get pointers to arch-specific information */
2541 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2542 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2543 xscale_trace_data_t
**trace_data_p
;
2545 /* 258 words from debug handler
2546 * 256 trace buffer entries
2547 * 2 checkpoint addresses
2549 uint32_t trace_buffer
[258];
2550 int is_address
[256];
2553 if (target
->state
!= TARGET_HALTED
)
2555 LOG_WARNING("target must be stopped to read trace data");
2556 return ERROR_TARGET_NOT_HALTED
;
2559 /* send read trace buffer command (command 0x61) */
2560 xscale_send_u32(target
, 0x61);
2562 /* receive trace buffer content */
2563 xscale_receive(target
, trace_buffer
, 258);
2565 /* parse buffer backwards to identify address entries */
2566 for (i
= 255; i
>= 0; i
--)
2569 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2570 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2573 is_address
[--i
] = 1;
2575 is_address
[--i
] = 1;
2577 is_address
[--i
] = 1;
2579 is_address
[--i
] = 1;
2584 /* search first non-zero entry */
2585 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2590 LOG_DEBUG("no trace data collected");
2591 return ERROR_XSCALE_NO_TRACE_DATA
;
2594 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2597 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2598 (*trace_data_p
)->next
= NULL
;
2599 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2600 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2601 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2602 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2603 (*trace_data_p
)->depth
= 256 - j
;
2605 for (i
= j
; i
< 256; i
++)
2607 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2609 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2611 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2617 static int xscale_read_instruction(target_t
*target
,
2618 arm_instruction_t
*instruction
)
2620 /* get pointers to arch-specific information */
2621 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2622 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2629 if (!xscale
->trace
.image
)
2630 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2632 /* search for the section the current instruction belongs to */
2633 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2635 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2636 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2645 /* current instruction couldn't be found in the image */
2646 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2649 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2652 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2653 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2654 4, buf
, &size_read
)) != ERROR_OK
)
2656 LOG_ERROR("error while reading instruction: %i", retval
);
2657 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2659 opcode
= target_buffer_get_u32(target
, buf
);
2660 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2662 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2665 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2666 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2667 2, buf
, &size_read
)) != ERROR_OK
)
2669 LOG_ERROR("error while reading instruction: %i", retval
);
2670 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2672 opcode
= target_buffer_get_u16(target
, buf
);
2673 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2677 LOG_ERROR("BUG: unknown core state encountered");
2684 static int xscale_branch_address(xscale_trace_data_t
*trace_data
,
2685 int i
, uint32_t *target
)
2687 /* if there are less than four entries prior to the indirect branch message
2688 * we can't extract the address */
2694 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2695 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2700 static int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2702 /* get pointers to arch-specific information */
2703 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2704 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2706 uint32_t next_pc
= 0x0;
2707 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2716 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2721 for (i
= 0; i
< trace_data
->depth
; i
++)
2727 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2730 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2732 case 0: /* Exceptions */
2740 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2742 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2743 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2745 case 8: /* Direct Branch */
2748 case 9: /* Indirect Branch */
2750 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2755 case 13: /* Checkpointed Indirect Branch */
2756 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2759 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2760 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2761 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2763 /* explicit fall-through */
2764 case 12: /* Checkpointed Direct Branch */
2769 next_pc
= trace_data
->chkpt0
;
2772 else if (chkpt
== 1)
2775 next_pc
= trace_data
->chkpt0
;
2780 LOG_WARNING("more than two checkpointed branches encountered");
2783 case 15: /* Roll-over */
2786 default: /* Reserved */
2787 command_print(cmd_ctx
, "--- reserved trace message ---");
2788 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2792 if (xscale
->trace
.pc_ok
)
2794 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2795 arm_instruction_t instruction
;
2797 if ((exception
== 6) || (exception
== 7))
2799 /* IRQ or FIQ exception, no instruction executed */
2803 while (executed
-- >= 0)
2805 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2807 /* can't continue tracing with no image available */
2808 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2812 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2814 /* TODO: handle incomplete images */
2818 /* a precise abort on a load to the PC is included in the incremental
2819 * word count, other instructions causing data aborts are not included
2821 if ((executed
== 0) && (exception
== 4)
2822 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2824 if ((instruction
.type
== ARM_LDM
)
2825 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2829 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2830 && (instruction
.info
.load_store
.Rd
!= 15))
2836 /* only the last instruction executed
2837 * (the one that caused the control flow change)
2838 * could be a taken branch
2840 if (((executed
== -1) && (branch
== 1)) &&
2841 (((instruction
.type
== ARM_B
) ||
2842 (instruction
.type
== ARM_BL
) ||
2843 (instruction
.type
== ARM_BLX
)) &&
2844 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2846 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2850 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2852 command_print(cmd_ctx
, "%s", instruction
.text
);
2860 xscale
->trace
.current_pc
= next_pc
;
2861 xscale
->trace
.pc_ok
= 1;
2865 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2867 arm_instruction_t instruction
;
2868 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2870 /* can't continue tracing with no image available */
2871 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2875 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2877 /* TODO: handle incomplete images */
2880 command_print(cmd_ctx
, "%s", instruction
.text
);
2883 trace_data
= trace_data
->next
;
2889 static void xscale_build_reg_cache(target_t
*target
)
2891 /* get pointers to arch-specific information */
2892 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2893 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2895 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2896 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2898 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2900 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2901 armv4_5
->core_cache
= (*cache_p
);
2903 /* register a register arch-type for XScale dbg registers only once */
2904 if (xscale_reg_arch_type
== -1)
2905 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2907 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2908 cache_p
= &(*cache_p
)->next
;
2910 /* fill in values for the xscale reg cache */
2911 (*cache_p
)->name
= "XScale registers";
2912 (*cache_p
)->next
= NULL
;
2913 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2914 (*cache_p
)->num_regs
= num_regs
;
2916 for (i
= 0; i
< num_regs
; i
++)
2918 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2919 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2920 (*cache_p
)->reg_list
[i
].dirty
= 0;
2921 (*cache_p
)->reg_list
[i
].valid
= 0;
2922 (*cache_p
)->reg_list
[i
].size
= 32;
2923 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
2924 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
2925 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2926 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
2927 arch_info
[i
] = xscale_reg_arch_info
[i
];
2928 arch_info
[i
].target
= target
;
2931 xscale
->reg_cache
= (*cache_p
);
2934 static int xscale_init_target(struct command_context_s
*cmd_ctx
,
2935 struct target_s
*target
)
2937 xscale_build_reg_cache(target
);
2941 static int xscale_quit(void)
2943 jtag_add_runtest(100, TAP_RESET
);
2947 static int xscale_init_arch_info(target_t
*target
,
2948 xscale_common_t
*xscale
, jtag_tap_t
*tap
, const char *variant
)
2950 armv4_5_common_t
*armv4_5
;
2951 uint32_t high_reset_branch
, low_reset_branch
;
2954 armv4_5
= &xscale
->armv4_5_common
;
2956 /* store architecture specfic data (none so far) */
2957 xscale
->arch_info
= NULL
;
2958 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
2960 /* we don't really *need* variant info ... */
2964 if (strcmp(variant
, "pxa250") == 0
2965 || strcmp(variant
, "pxa255") == 0
2966 || strcmp(variant
, "pxa26x") == 0)
2968 else if (strcmp(variant
, "pxa27x") == 0
2969 || strcmp(variant
, "ixp42x") == 0
2970 || strcmp(variant
, "ixp45x") == 0
2971 || strcmp(variant
, "ixp46x") == 0)
2974 LOG_WARNING("%s: unrecognized variant %s",
2975 tap
->dotted_name
, variant
);
2977 if (ir_length
&& ir_length
!= tap
->ir_length
) {
2978 LOG_WARNING("%s: IR length for %s is %d; fixing",
2979 tap
->dotted_name
, variant
, ir_length
);
2980 tap
->ir_length
= ir_length
;
2984 /* the debug handler isn't installed (and thus not running) at this time */
2985 xscale
->handler_installed
= 0;
2986 xscale
->handler_running
= 0;
2987 xscale
->handler_address
= 0xfe000800;
2989 /* clear the vectors we keep locally for reference */
2990 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
2991 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
2993 /* no user-specified vectors have been configured yet */
2994 xscale
->static_low_vectors_set
= 0x0;
2995 xscale
->static_high_vectors_set
= 0x0;
2997 /* calculate branches to debug handler */
2998 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
2999 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3001 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3002 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3004 for (i
= 1; i
<= 7; i
++)
3006 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3007 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3010 /* 64kB aligned region used for DCache cleaning */
3011 xscale
->cache_clean_address
= 0xfffe0000;
3013 xscale
->hold_rst
= 0;
3014 xscale
->external_debug_break
= 0;
3016 xscale
->ibcr_available
= 2;
3017 xscale
->ibcr0_used
= 0;
3018 xscale
->ibcr1_used
= 0;
3020 xscale
->dbr_available
= 2;
3021 xscale
->dbr0_used
= 0;
3022 xscale
->dbr1_used
= 0;
3024 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3025 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3027 xscale
->vector_catch
= 0x1;
3029 xscale
->trace
.capture_status
= TRACE_IDLE
;
3030 xscale
->trace
.data
= NULL
;
3031 xscale
->trace
.image
= NULL
;
3032 xscale
->trace
.buffer_enabled
= 0;
3033 xscale
->trace
.buffer_fill
= 0;
3035 /* prepare ARMv4/5 specific information */
3036 armv4_5
->arch_info
= xscale
;
3037 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3038 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3039 armv4_5
->full_context
= xscale_full_context
;
3041 armv4_5_init_arch_info(target
, armv4_5
);
3043 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3044 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3045 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3046 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3047 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3048 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3049 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3050 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3055 static int xscale_target_create(struct target_s
*target
, Jim_Interp
*interp
)
3057 xscale_common_t
*xscale
;
3059 xscale
= calloc(1, sizeof(*xscale
));
3063 return xscale_init_arch_info(target
, xscale
, target
->tap
,
3068 xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
,
3069 char *cmd
, char **args
, int argc
)
3071 target_t
*target
= NULL
;
3072 armv4_5_common_t
*armv4_5
;
3073 xscale_common_t
*xscale
;
3075 uint32_t handler_address
;
3079 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3083 if ((target
= get_target(args
[0])) == NULL
)
3085 LOG_ERROR("target '%s' not defined", args
[0]);
3089 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3094 handler_address
= strtoul(args
[1], NULL
, 0);
3096 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3097 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3099 xscale
->handler_address
= handler_address
;
3103 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3111 xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
,
3112 char *cmd
, char **args
, int argc
)
3114 target_t
*target
= NULL
;
3115 armv4_5_common_t
*armv4_5
;
3116 xscale_common_t
*xscale
;
3118 uint32_t cache_clean_address
;
3122 return ERROR_COMMAND_SYNTAX_ERROR
;
3125 target
= get_target(args
[0]);
3128 LOG_ERROR("target '%s' not defined", args
[0]);
3132 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3137 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3139 if (cache_clean_address
& 0xffff)
3141 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3145 xscale
->cache_clean_address
= cache_clean_address
;
3152 xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
,
3153 char *cmd
, char **args
, int argc
)
3155 target_t
*target
= get_current_target(cmd_ctx
);
3156 armv4_5_common_t
*armv4_5
;
3157 xscale_common_t
*xscale
;
3159 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3164 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3167 static int xscale_virt2phys(struct target_s
*target
,
3168 uint32_t virtual, uint32_t *physical
)
3170 armv4_5_common_t
*armv4_5
;
3171 xscale_common_t
*xscale
;
3178 if ((retval
= xscale_get_arch_pointers(target
, &armv4_5
, &xscale
)) != ERROR_OK
)
3182 uint32_t ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3191 static int xscale_mmu(struct target_s
*target
, int *enabled
)
3193 armv4_5_common_t
*armv4_5
= target
->arch_info
;
3194 xscale_common_t
*xscale
= armv4_5
->arch_info
;
3196 if (target
->state
!= TARGET_HALTED
)
3198 LOG_ERROR("Target not halted");
3199 return ERROR_TARGET_INVALID
;
3201 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3205 static int xscale_handle_mmu_command(command_context_t
*cmd_ctx
,
3206 char *cmd
, char **args
, int argc
)
3208 target_t
*target
= get_current_target(cmd_ctx
);
3209 armv4_5_common_t
*armv4_5
;
3210 xscale_common_t
*xscale
;
3212 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3217 if (target
->state
!= TARGET_HALTED
)
3219 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3225 if (strcmp("enable", args
[0]) == 0)
3227 xscale_enable_mmu_caches(target
, 1, 0, 0);
3228 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3230 else if (strcmp("disable", args
[0]) == 0)
3232 xscale_disable_mmu_caches(target
, 1, 0, 0);
3233 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3237 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3242 static int xscale_handle_idcache_command(command_context_t
*cmd_ctx
,
3243 char *cmd
, char **args
, int argc
)
3245 target_t
*target
= get_current_target(cmd_ctx
);
3246 armv4_5_common_t
*armv4_5
;
3247 xscale_common_t
*xscale
;
3248 int icache
= 0, dcache
= 0;
3250 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3255 if (target
->state
!= TARGET_HALTED
)
3257 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3261 if (strcmp(cmd
, "icache") == 0)
3263 else if (strcmp(cmd
, "dcache") == 0)
3268 if (strcmp("enable", args
[0]) == 0)
3270 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3273 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3275 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3277 else if (strcmp("disable", args
[0]) == 0)
3279 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3282 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3284 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3289 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3292 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3297 static int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
,
3298 char *cmd
, char **args
, int argc
)
3300 target_t
*target
= get_current_target(cmd_ctx
);
3301 armv4_5_common_t
*armv4_5
;
3302 xscale_common_t
*xscale
;
3304 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3311 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3315 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3316 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3317 xscale_write_dcsr(target
, -1, -1);
3320 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3326 static int xscale_handle_vector_table_command(command_context_t
*cmd_ctx
,
3327 char *cmd
, char **args
, int argc
)
3329 target_t
*target
= get_current_target(cmd_ctx
);
3330 armv4_5_common_t
*armv4_5
;
3331 xscale_common_t
*xscale
;
3334 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3339 if (argc
== 0) /* print current settings */
3343 command_print(cmd_ctx
, "active user-set static vectors:");
3344 for (idx
= 1; idx
< 8; idx
++)
3345 if (xscale
->static_low_vectors_set
& (1 << idx
))
3346 command_print(cmd_ctx
, "low %d: 0x%" PRIx32
, idx
, xscale
->static_low_vectors
[idx
]);
3347 for (idx
= 1; idx
< 8; idx
++)
3348 if (xscale
->static_high_vectors_set
& (1 << idx
))
3349 command_print(cmd_ctx
, "high %d: 0x%" PRIx32
, idx
, xscale
->static_high_vectors
[idx
]);
3359 idx
= strtoul(args
[1], NULL
, 0);
3360 vec
= strtoul(args
[2], NULL
, 0);
3362 if (idx
< 1 || idx
>= 8)
3365 if (!err
&& strcmp(args
[0], "low") == 0)
3367 xscale
->static_low_vectors_set
|= (1<<idx
);
3368 xscale
->static_low_vectors
[idx
] = vec
;
3370 else if (!err
&& (strcmp(args
[0], "high") == 0))
3372 xscale
->static_high_vectors_set
|= (1<<idx
);
3373 xscale
->static_high_vectors
[idx
] = vec
;
3380 command_print(cmd_ctx
, "usage: xscale vector_table <high|low> <index> <code>");
3387 xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
,
3388 char *cmd
, char **args
, int argc
)
3390 target_t
*target
= get_current_target(cmd_ctx
);
3391 armv4_5_common_t
*armv4_5
;
3392 xscale_common_t
*xscale
;
3393 uint32_t dcsr_value
;
3395 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3400 if (target
->state
!= TARGET_HALTED
)
3402 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3406 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3408 xscale_trace_data_t
*td
, *next_td
;
3409 xscale
->trace
.buffer_enabled
= 1;
3411 /* free old trace data */
3412 td
= xscale
->trace
.data
;
3422 xscale
->trace
.data
= NULL
;
3424 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3426 xscale
->trace
.buffer_enabled
= 0;
3429 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3432 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3434 xscale
->trace
.buffer_fill
= 1;
3436 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3438 xscale
->trace
.buffer_fill
= -1;
3441 if (xscale
->trace
.buffer_enabled
)
3443 /* if we enable the trace buffer in fill-once
3444 * mode we know the address of the first instruction */
3445 xscale
->trace
.pc_ok
= 1;
3446 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3450 /* otherwise the address is unknown, and we have no known good PC */
3451 xscale
->trace
.pc_ok
= 0;
3454 command_print(cmd_ctx
, "trace buffer %s (%s)",
3455 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3456 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3458 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3459 if (xscale
->trace
.buffer_fill
>= 0)
3460 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3462 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3468 xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
,
3469 char *cmd
, char **args
, int argc
)
3472 armv4_5_common_t
*armv4_5
;
3473 xscale_common_t
*xscale
;
3477 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3481 target
= get_current_target(cmd_ctx
);
3483 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3488 if (xscale
->trace
.image
)
3490 image_close(xscale
->trace
.image
);
3491 free(xscale
->trace
.image
);
3492 command_print(cmd_ctx
, "previously loaded image found and closed");
3495 xscale
->trace
.image
= malloc(sizeof(image_t
));
3496 xscale
->trace
.image
->base_address_set
= 0;
3497 xscale
->trace
.image
->start_address_set
= 0;
3499 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3502 xscale
->trace
.image
->base_address_set
= 1;
3503 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3507 xscale
->trace
.image
->base_address_set
= 0;
3510 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3512 free(xscale
->trace
.image
);
3513 xscale
->trace
.image
= NULL
;
3520 static int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
,
3521 char *cmd
, char **args
, int argc
)
3523 target_t
*target
= get_current_target(cmd_ctx
);
3524 armv4_5_common_t
*armv4_5
;
3525 xscale_common_t
*xscale
;
3526 xscale_trace_data_t
*trace_data
;
3529 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3534 if (target
->state
!= TARGET_HALTED
)
3536 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3542 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3546 trace_data
= xscale
->trace
.data
;
3550 command_print(cmd_ctx
, "no trace data collected");
3554 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3563 fileio_write_u32(&file
, trace_data
->chkpt0
);
3564 fileio_write_u32(&file
, trace_data
->chkpt1
);
3565 fileio_write_u32(&file
, trace_data
->last_instruction
);
3566 fileio_write_u32(&file
, trace_data
->depth
);
3568 for (i
= 0; i
< trace_data
->depth
; i
++)
3569 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3571 trace_data
= trace_data
->next
;
3574 fileio_close(&file
);
3580 xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
,
3581 char *cmd
, char **args
, int argc
)
3583 target_t
*target
= get_current_target(cmd_ctx
);
3584 armv4_5_common_t
*armv4_5
;
3585 xscale_common_t
*xscale
;
3587 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3592 xscale_analyze_trace(target
, cmd_ctx
);
3597 static int xscale_handle_cp15(command_context_t
*cmd_ctx
,
3598 char *cmd
, char **args
, int argc
)
3600 target_t
*target
= get_current_target(cmd_ctx
);
3601 armv4_5_common_t
*armv4_5
;
3602 xscale_common_t
*xscale
;
3604 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3609 if (target
->state
!= TARGET_HALTED
)
3611 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3614 uint32_t reg_no
= 0;
3618 reg_no
= strtoul(args
[0], NULL
, 0);
3619 /*translate from xscale cp15 register no to openocd register*/
3623 reg_no
= XSCALE_MAINID
;
3626 reg_no
= XSCALE_CTRL
;
3629 reg_no
= XSCALE_TTB
;
3632 reg_no
= XSCALE_DAC
;
3635 reg_no
= XSCALE_FSR
;
3638 reg_no
= XSCALE_FAR
;
3641 reg_no
= XSCALE_PID
;
3644 reg_no
= XSCALE_CPACCESS
;
3647 command_print(cmd_ctx
, "invalid register number");
3648 return ERROR_INVALID_ARGUMENTS
;
3650 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3657 /* read cp15 control register */
3658 xscale_get_reg(reg
);
3659 value
= buf_get_u32(reg
->value
, 0, 32);
3660 command_print(cmd_ctx
, "%s (/%i): 0x%" PRIx32
"", reg
->name
, (int)(reg
->size
), value
);
3665 uint32_t value
= strtoul(args
[1], NULL
, 0);
3667 /* send CP write request (command 0x41) */
3668 xscale_send_u32(target
, 0x41);
3670 /* send CP register number */
3671 xscale_send_u32(target
, reg_no
);
3673 /* send CP register value */
3674 xscale_send_u32(target
, value
);
3676 /* execute cpwait to ensure outstanding operations complete */
3677 xscale_send_u32(target
, 0x53);
3681 command_print(cmd_ctx
, "usage: cp15 [register]<, [value]>");
3687 static int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3689 command_t
*xscale_cmd
;
3691 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3693 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3694 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3696 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3697 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3698 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3699 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3701 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_vector_catch_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3702 register_command(cmd_ctx
, xscale_cmd
, "vector_table", xscale_handle_vector_table_command
, COMMAND_EXEC
, "<high|low> <index> <code> set static code for exception handler entry");
3704 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable | disable> ['fill' [n]|'wrap']");
3706 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3707 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3708 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3709 COMMAND_EXEC
, "load image from <file> [base address]");
3711 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3713 armv4_5_register_commands(cmd_ctx
);
3718 target_type_t xscale_target
=
3722 .poll
= xscale_poll
,
3723 .arch_state
= xscale_arch_state
,
3725 .target_request_data
= NULL
,
3727 .halt
= xscale_halt
,
3728 .resume
= xscale_resume
,
3729 .step
= xscale_step
,
3731 .assert_reset
= xscale_assert_reset
,
3732 .deassert_reset
= xscale_deassert_reset
,
3733 .soft_reset_halt
= NULL
,
3735 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
3737 .read_memory
= xscale_read_memory
,
3738 .write_memory
= xscale_write_memory
,
3739 .bulk_write_memory
= xscale_bulk_write_memory
,
3740 .checksum_memory
= arm7_9_checksum_memory
,
3741 .blank_check_memory
= arm7_9_blank_check_memory
,
3743 .run_algorithm
= armv4_5_run_algorithm
,
3745 .add_breakpoint
= xscale_add_breakpoint
,
3746 .remove_breakpoint
= xscale_remove_breakpoint
,
3747 .add_watchpoint
= xscale_add_watchpoint
,
3748 .remove_watchpoint
= xscale_remove_watchpoint
,
3750 .register_commands
= xscale_register_commands
,
3751 .target_create
= xscale_target_create
,
3752 .init_target
= xscale_init_target
,
3753 .quit
= xscale_quit
,
3755 .virt2phys
= xscale_virt2phys
,