src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include <target/target.h>
  30 #include <helper/command.h>
  31
  32
  33 typedef enum armv4_5_mode
  34 {
  35         ARMV4_5_MODE_USR = 16,
  36         ARMV4_5_MODE_FIQ = 17,
  37         ARMV4_5_MODE_IRQ = 18,
  38         ARMV4_5_MODE_SVC = 19,
  39         ARMV4_5_MODE_ABT = 23,
  40         ARM_MODE_MON = 26,
  41         ARMV4_5_MODE_UND = 27,
  42         ARMV4_5_MODE_SYS = 31,
  43         ARMV4_5_MODE_ANY = -1
  44 } armv4_5_mode_t;
  45
  46 const char *arm_mode_name(unsigned psr_mode);
  47 bool is_arm_mode(unsigned psr_mode);
  48
  49 int armv4_5_mode_to_number(enum armv4_5_mode mode);
  50 enum armv4_5_mode armv4_5_number_to_mode(int number);
  51
  52 typedef enum armv4_5_state
  53 {
  54         ARMV4_5_STATE_ARM,
  55         ARMV4_5_STATE_THUMB,
  56         ARMV4_5_STATE_JAZELLE,
  57         ARM_STATE_THUMB_EE,
  58 } armv4_5_state_t;
  59
  60 extern char* armv4_5_state_strings[];
  61
  62 extern const int armv4_5_core_reg_map[8][17];
  63
  64 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  65                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  66
  67 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
  68 enum { ARMV4_5_CPSR = 31, };
  69
  70 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  71
  72 /**
  73  * Represents a generic ARM core, with standard application registers.
  74  *
  75  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  76  * Cortex-M series cores do not support as many core states or shadowed
  77  * registers as traditional ARM cores, and only support Thumb2 instructions.
  78  */
  79 struct arm
  80 {
  81         int common_magic;
  82         struct reg_cache *core_cache;
  83
  84         /** Handle to the CPSR; valid in all core modes. */
  85         struct reg *cpsr;
  86
  87         /** Handle to the SPSR; valid only in core modes with an SPSR. */
  88         struct reg *spsr;
  89
  90         const int *map;
  91
  92         /**
  93          * Indicates what registers are in the ARM state core register set.
  94          * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
  95          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
  96          * more registers are shadowed, for "Secure Monitor" mode.
  97          */
  98         enum armv4_5_mode core_type;
  99
 100         enum armv4_5_mode core_mode;
 101         enum armv4_5_state core_state;
 102
 103         /** Flag reporting unavailability of the BKPT instruction. */
 104         bool is_armv4;
 105
 106         /** Backpointer to the target. */
 107         struct target *target;
 108
 109         /** Handle for the debug module, if one is present. */
 110         struct arm_dpm *dpm;
 111
 112         /** Handle for the Embedded Trace Module, if one is present. */
 113         struct etm_context *etm;
 114
 115         /* FIXME all these methods should take "struct arm *" not target */
 116
 117         int (*full_context)(struct target *target);
 118         int (*read_core_reg)(struct target *target, struct reg *reg,
 119                         int num, enum armv4_5_mode mode);
 120         int (*write_core_reg)(struct target *target, struct reg *reg,
 121                         int num, enum armv4_5_mode mode, uint32_t value);
 122
 123         /** Read coprocessor register.  */
 124         int (*mrc)(struct target *target, int cpnum,
 125                         uint32_t op1, uint32_t op2,
 126                         uint32_t CRn, uint32_t CRm,
 127                         uint32_t *value);
 128
 129         /* Write coprocessor register.  */
 130         int (*mcr)(struct target *target, int cpnum,
 131                         uint32_t op1, uint32_t op2,
 132                         uint32_t CRn, uint32_t CRm,
 133                         uint32_t value);
 134
 135         void *arch_info;
 136 };
 137
 138 #define target_to_armv4_5 target_to_arm
 139
 140 /** Convert target handle to generic ARM target state handle. */
 141 static inline struct arm *target_to_arm(struct target *target)
 142 {
 143         return target->arch_info;
 144 }
 145
 146 static inline bool is_arm(struct arm *arm)
 147 {
 148         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 149 }
 150
 151 struct armv4_5_algorithm
 152 {
 153         int common_magic;
 154
 155         enum armv4_5_mode core_mode;
 156         enum armv4_5_state core_state;
 157 };
 158
 159 struct arm_reg
 160 {
 161         int num;
 162         enum armv4_5_mode mode;
 163         struct target *target;
 164         struct arm *armv4_5_common;
 165         uint32_t value;
 166 };
 167
 168 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 169                 struct arm *armv4_5_common);
 170
 171 int armv4_5_arch_state(struct target *target);
 172 int armv4_5_get_gdb_reg_list(struct target *target,
 173                 struct reg **reg_list[], int *reg_list_size);
 174
 175 extern const struct command_registration arm_command_handlers[];
 176
 177 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 178
 179 int armv4_5_run_algorithm(struct target *target,
 180                 int num_mem_params, struct mem_param *mem_params,
 181                 int num_reg_params, struct reg_param *reg_params,
 182                 uint32_t entry_point, uint32_t exit_point,
 183                 int timeout_ms, void *arch_info);
 184
 185 int arm_checksum_memory(struct target *target,
 186                 uint32_t address, uint32_t count, uint32_t *checksum);
 187 int arm_blank_check_memory(struct target *target,
 188                 uint32_t address, uint32_t count, uint32_t *blank);
 189
 190 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 191 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 192
 193 extern struct reg arm_gdb_dummy_fp_reg;
 194 extern struct reg arm_gdb_dummy_fps_reg;
 195
 196 /* ARM mode instructions
 197  */
 198
 199 /* Store multiple increment after
 200  * Rn: base register
 201  * List: for each bit in list: store register
 202  * S: in priviledged mode: store user-mode registers
 203  * W = 1: update the base register. W = 0: leave the base register untouched
 204  */
 205 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 206
 207 /* Load multiple increment after
 208  * Rn: base register
 209  * List: for each bit in list: store register
 210  * S: in priviledged mode: store user-mode registers
 211  * W = 1: update the base register. W = 0: leave the base register untouched
 212  */
 213 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 214
 215 /* MOV r8, r8 */
 216 #define ARMV4_5_NOP                                     (0xe1a08008)
 217
 218 /* Move PSR to general purpose register
 219  * R = 1: SPSR R = 0: CPSR
 220  * Rn: target register
 221  */
 222 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 223
 224 /* Store register
 225  * Rd: register to store
 226  * Rn: base register
 227  */
 228 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 229
 230 /* Load register
 231  * Rd: register to load
 232  * Rn: base register
 233  */
 234 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 235
 236 /* Move general purpose register to PSR
 237  * R = 1: SPSR R = 0: CPSR
 238  * Field: Field mask
 239  * 1: control field 2: extension field 4: status field 8: flags field
 240  * Rm: source register
 241  */
 242 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 243 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 244
 245 /* Load Register Halfword Immediate Post-Index
 246  * Rd: register to load
 247  * Rn: base register
 248  */
 249 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 250
 251 /* Load Register Byte Immediate Post-Index
 252  * Rd: register to load
 253  * Rn: base register
 254  */
 255 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 256
 257 /* Store register Halfword Immediate Post-Index
 258  * Rd: register to store
 259  * Rn: base register
 260  */
 261 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 262
 263 /* Store register Byte Immediate Post-Index
 264  * Rd: register to store
 265  * Rn: base register
 266  */
 267 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 268
 269 /* Branch (and Link)
 270  * Im: Branch target (left-shifted by 2 bits, added to PC)
 271  * L: 1: branch and link 0: branch only
 272  */
 273 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 274
 275 /* Branch and exchange (ARM state)
 276  * Rm: register holding branch target address
 277  */
 278 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 279
 280 /* Move to ARM register from coprocessor
 281  * CP: Coprocessor number
 282  * op1: Coprocessor opcode
 283  * Rd: destination register
 284  * CRn: first coprocessor operand
 285  * CRm: second coprocessor operand
 286  * op2: Second coprocessor opcode
 287  */
 288 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 289
 290 /* Move to coprocessor from ARM register
 291  * CP: Coprocessor number
 292  * op1: Coprocessor opcode
 293  * Rd: destination register
 294  * CRn: first coprocessor operand
 295  * CRm: second coprocessor operand
 296  * op2: Second coprocessor opcode
 297  */
 298 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 299
 300 /* Breakpoint instruction (ARMv5)
 301  * Im: 16-bit immediate
 302  */
 303 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 304
 305
 306 /* Thumb mode instructions
 307  */
 308
 309 /* Store register (Thumb mode)
 310  * Rd: source register
 311  * Rn: base register
 312  */
 313 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 314
 315 /* Load register (Thumb state)
 316  * Rd: destination register
 317  * Rn: base register
 318  */
 319 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 320
 321 /* Load multiple (Thumb state)
 322  * Rn: base register
 323  * List: for each bit in list: store register
 324  */
 325 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 326
 327 /* Load register with PC relative addressing
 328  * Rd: register to load
 329  */
 330 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 331
 332 /* Move hi register (Thumb mode)
 333  * Rd: destination register
 334  * Rm: source register
 335  */
 336 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 337
 338 /* No operation (Thumb mode)
 339  */
 340 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 341
 342 /* Move immediate to register (Thumb state)
 343  * Rd: destination register
 344  * Im: 8-bit immediate value
 345  */
 346 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 347
 348 /* Branch and Exchange
 349  * Rm: register containing branch target
 350  */
 351 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 352
 353 /* Branch (Thumb state)
 354  * Imm: Branch target
 355  */
 356 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 357
 358 /* Breakpoint instruction (ARMv5) (Thumb state)
 359  * Im: 8-bit immediate
 360  */
 361 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 362
 363 /* build basic mrc/mcr opcode */
 364
 365 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 366 {
 367         uint32_t t = 0;
 368         t|=op1<<21;
 369         t|=op2<<5;
 370         t|=CRn<<16;
 371         t|=CRm<<0;
 372         return t;
 373 }
 374
 375 #endif /* ARMV4_5_H */