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NAND page command refactoring.
[openocd.git] / src / target / arm920t.c
blobe8c1950fa37cf997a767d69c0483cf22e3fa3bdc
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include <helper/time_support.h>
26 #include "target_type.h"
27 #include "register.h"
28
29
30 /*
31 * For information about the ARM920T, see ARM DDI 0151C especially
32 * Chapter 9 about debug support, which shows how to manipulate each
33 * of the different scan chains:
34 *
35 * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
36 * 1 ... debugging; watchpoint and breakpoint status, etc; also
37 * MMU and cache access in conjunction with scan chain 15
38 * 2 ... EmbeddedICE
39 * 3 ... external boundary scan (SoC-specific, unused here)
40 * 4 ... access to cache tag RAM
41 * 6 ... ETM9
42 * 15 ... access coprocessor 15, "physical" or "interpreted" modes
43 * "interpreted" works with a few actual MRC/MCR instructions
44 * "physical" provides register-like behaviors.
45 *
46 * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
47 */
48
49 #if 0
50 #define _DEBUG_INSTRUCTION_EXECUTION_
51 #endif
52
53 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
54
55 static int arm920t_read_cp15_physical(struct target *target,
56 int reg_addr, uint32_t *value)
57 {
58 struct arm920t_common *arm920t = target_to_arm920(target);
59 struct arm_jtag *jtag_info;
60 struct scan_field fields[4];
61 uint8_t access_type_buf = 1;
62 uint8_t reg_addr_buf = reg_addr & 0x3f;
63 uint8_t nr_w_buf = 0;
64
65 jtag_info = &arm920t->arm7_9_common.jtag_info;
66
67 jtag_set_end_state(TAP_IDLE);
68 arm_jtag_scann(jtag_info, 0xf);
69 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
70
71 fields[0].tap = jtag_info->tap;
72 fields[0].num_bits = 1;
73 fields[0].out_value = &access_type_buf;
74 fields[0].in_value = NULL;
75
76 fields[1].tap = jtag_info->tap;
77 fields[1].num_bits = 32;
78 fields[1].out_value = NULL;
79 fields[1].in_value = NULL;
80
81 fields[2].tap = jtag_info->tap;
82 fields[2].num_bits = 6;
83 fields[2].out_value = &reg_addr_buf;
84 fields[2].in_value = NULL;
85
86 fields[3].tap = jtag_info->tap;
87 fields[3].num_bits = 1;
88 fields[3].out_value = &nr_w_buf;
89 fields[3].in_value = NULL;
90
91 jtag_add_dr_scan(4, fields, jtag_get_end_state());
92
93 fields[1].in_value = (uint8_t *)value;
94
95 jtag_add_dr_scan(4, fields, jtag_get_end_state());
96
97 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
98
99 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
100 jtag_execute_queue();
101 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
102 #endif
103
104 return ERROR_OK;
105 }
106
107 static int arm920t_write_cp15_physical(struct target *target,
108 int reg_addr, uint32_t value)
109 {
110 struct arm920t_common *arm920t = target_to_arm920(target);
111 struct arm_jtag *jtag_info;
112 struct scan_field fields[4];
113 uint8_t access_type_buf = 1;
114 uint8_t reg_addr_buf = reg_addr & 0x3f;
115 uint8_t nr_w_buf = 1;
116 uint8_t value_buf[4];
117
118 jtag_info = &arm920t->arm7_9_common.jtag_info;
119
120 buf_set_u32(value_buf, 0, 32, value);
121
122 jtag_set_end_state(TAP_IDLE);
123 arm_jtag_scann(jtag_info, 0xf);
124 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
125
126 fields[0].tap = jtag_info->tap;
127 fields[0].num_bits = 1;
128 fields[0].out_value = &access_type_buf;
129 fields[0].in_value = NULL;
130
131 fields[1].tap = jtag_info->tap;
132 fields[1].num_bits = 32;
133 fields[1].out_value = value_buf;
134 fields[1].in_value = NULL;
135
136 fields[2].tap = jtag_info->tap;
137 fields[2].num_bits = 6;
138 fields[2].out_value = &reg_addr_buf;
139 fields[2].in_value = NULL;
140
141 fields[3].tap = jtag_info->tap;
142 fields[3].num_bits = 1;
143 fields[3].out_value = &nr_w_buf;
144 fields[3].in_value = NULL;
145
146 jtag_add_dr_scan(4, fields, jtag_get_end_state());
147
148 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
149 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
150 #endif
151
152 return ERROR_OK;
153 }
154
155 static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
156 uint32_t arm_opcode)
157 {
158 int retval;
159 struct arm920t_common *arm920t = target_to_arm920(target);
160 struct arm_jtag *jtag_info;
161 struct scan_field fields[4];
162 uint8_t access_type_buf = 0; /* interpreted access */
163 uint8_t reg_addr_buf = 0x0;
164 uint8_t nr_w_buf = 0;
165 uint8_t cp15_opcode_buf[4];
166
167 jtag_info = &arm920t->arm7_9_common.jtag_info;
168
169 jtag_set_end_state(TAP_IDLE);
170 arm_jtag_scann(jtag_info, 0xf);
171 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
172
173 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
174
175 fields[0].tap = jtag_info->tap;
176 fields[0].num_bits = 1;
177 fields[0].out_value = &access_type_buf;
178 fields[0].in_value = NULL;
179
180 fields[1].tap = jtag_info->tap;
181 fields[1].num_bits = 32;
182 fields[1].out_value = cp15_opcode_buf;
183 fields[1].in_value = NULL;
184
185 fields[2].tap = jtag_info->tap;
186 fields[2].num_bits = 6;
187 fields[2].out_value = &reg_addr_buf;
188 fields[2].in_value = NULL;
189
190 fields[3].tap = jtag_info->tap;
191 fields[3].num_bits = 1;
192 fields[3].out_value = &nr_w_buf;
193 fields[3].in_value = NULL;
194
195 jtag_add_dr_scan(4, fields, jtag_get_end_state());
196
197 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
198 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
199 retval = arm7_9_execute_sys_speed(target);
200 if (retval != ERROR_OK)
201 return retval;
202
203 if ((retval = jtag_execute_queue()) != ERROR_OK)
204 {
205 LOG_ERROR("failed executing JTAG queue");
206 return retval;
207 }
208
209 return ERROR_OK;
210 }
211
212 static int arm920t_read_cp15_interpreted(struct target *target,
213 uint32_t cp15_opcode, uint32_t address, uint32_t *value)
214 {
215 struct arm *armv4_5 = target_to_armv4_5(target);
216 uint32_t* regs_p[1];
217 uint32_t regs[2];
218 uint32_t cp15c15 = 0x0;
219 struct reg *r = armv4_5->core_cache->reg_list;
220
221 /* load address into R1 */
222 regs[1] = address;
223 arm9tdmi_write_core_regs(target, 0x2, regs);
224
225 /* read-modify-write CP15 test state register
226 * to enable interpreted access mode */
227 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
228 jtag_execute_queue();
229 cp15c15 |= 1; /* set interpret mode */
230 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
231
232 /* execute CP15 instruction and ARM load (reading from coprocessor) */
233 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
234
235 /* disable interpreted access mode */
236 cp15c15 &= ~1U; /* clear interpret mode */
237 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
238
239 /* retrieve value from R0 */
240 regs_p[0] = value;
241 arm9tdmi_read_core_regs(target, 0x1, regs_p);
242 jtag_execute_queue();
243
244 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
245 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
246 #endif
247
248 if (!is_arm_mode(armv4_5->core_mode))
249 return ERROR_FAIL;
250
251 r[0].dirty = 1;
252 r[1].dirty = 1;
253
254 return ERROR_OK;
255 }
256
257 static
258 int arm920t_write_cp15_interpreted(struct target *target,
259 uint32_t cp15_opcode, uint32_t value, uint32_t address)
260 {
261 uint32_t cp15c15 = 0x0;
262 struct arm *armv4_5 = target_to_armv4_5(target);
263 uint32_t regs[2];
264 struct reg *r = armv4_5->core_cache->reg_list;
265
266 /* load value, address into R0, R1 */
267 regs[0] = value;
268 regs[1] = address;
269 arm9tdmi_write_core_regs(target, 0x3, regs);
270
271 /* read-modify-write CP15 test state register
272 * to enable interpreted access mode */
273 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
274 jtag_execute_queue();
275 cp15c15 |= 1; /* set interpret mode */
276 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
277
278 /* execute CP15 instruction and ARM store (writing to coprocessor) */
279 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
280
281 /* disable interpreted access mode */
282 cp15c15 &= ~1U; /* set interpret mode */
283 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
284
285 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
286 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
287 #endif
288
289 if (!is_arm_mode(armv4_5->core_mode))
290 return ERROR_FAIL;
291
292 r[0].dirty = 1;
293 r[1].dirty = 1;
294
295 return ERROR_OK;
296 }
297
298 // EXPORTED to FA256
299 uint32_t arm920t_get_ttb(struct target *target)
300 {
301 int retval;
302 uint32_t ttb = 0x0;
303
304 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
305 return retval;
306
307 return ttb;
308 }
309
310 // EXPORTED to FA256
311 void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
312 {
313 uint32_t cp15_control;
314
315 /* read cp15 control register */
316 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
317 jtag_execute_queue();
318
319 if (mmu)
320 cp15_control &= ~0x1U;
321
322 if (d_u_cache)
323 cp15_control &= ~0x4U;
324
325 if (i_cache)
326 cp15_control &= ~0x1000U;
327
328 arm920t_write_cp15_physical(target, 0x2, cp15_control);
329 }
330
331 // EXPORTED to FA256
332 void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
333 {
334 uint32_t cp15_control;
335
336 /* read cp15 control register */
337 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
338 jtag_execute_queue();
339
340 if (mmu)
341 cp15_control |= 0x1U;
342
343 if (d_u_cache)
344 cp15_control |= 0x4U;
345
346 if (i_cache)
347 cp15_control |= 0x1000U;
348
349 arm920t_write_cp15_physical(target, 0x2, cp15_control);
350 }
351
352 // EXPORTED to FA256
353 void arm920t_post_debug_entry(struct target *target)
354 {
355 uint32_t cp15c15;
356 struct arm920t_common *arm920t = target_to_arm920(target);
357
358 /* examine cp15 control reg */
359 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
360 jtag_execute_queue();
361 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
362
363 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
364 {
365 uint32_t cache_type_reg;
366 /* identify caches */
367 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
368 jtag_execute_queue();
369 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
370 }
371
372 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
373 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
374 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
375
376 /* save i/d fault status and address register */
377 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
378 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
379 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
380 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
381
382 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
383 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
384
385 if (arm920t->preserve_cache)
386 {
387 /* read-modify-write CP15 test state register
388 * to disable I/D-cache linefills */
389 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
390 jtag_execute_queue();
391 cp15c15 |= 0x600;
392 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
393 }
394 }
395
396 // EXPORTED to FA256
397 void arm920t_pre_restore_context(struct target *target)
398 {
399 uint32_t cp15c15;
400 struct arm920t_common *arm920t = target_to_arm920(target);
401
402 /* restore i/d fault status and address register */
403 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
404 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
405 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
406 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
407
408 /* read-modify-write CP15 test state register
409 * to reenable I/D-cache linefills */
410 if (arm920t->preserve_cache)
411 {
412 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
413 jtag_execute_queue();
414 cp15c15 &= ~0x600U;
415 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
416 }
417 }
418
419 static const char arm920_not[] = "target is not an ARM920";
420
421 static int arm920t_verify_pointer(struct command_context *cmd_ctx,
422 struct arm920t_common *arm920t)
423 {
424 if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
425 command_print(cmd_ctx, arm920_not);
426 return ERROR_TARGET_INVALID;
427 }
428
429 return ERROR_OK;
430 }
431
432 /** Logs summary of ARM920 state for a halted target. */
433 int arm920t_arch_state(struct target *target)
434 {
435 static const char *state[] =
436 {
437 "disabled", "enabled"
438 };
439
440 struct arm920t_common *arm920t = target_to_arm920(target);
441 struct arm *armv4_5;
442
443 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
444 {
445 LOG_ERROR("BUG: %s", arm920_not);
446 return ERROR_TARGET_INVALID;
447 }
448
449 armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
450
451 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
452 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
453 "MMU: %s, D-Cache: %s, I-Cache: %s",
454 armv4_5_state_strings[armv4_5->core_state],
455 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
456 arm_mode_name(armv4_5->core_mode),
457 buf_get_u32(armv4_5->cpsr->value, 0, 32),
458 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
459 state[arm920t->armv4_5_mmu.mmu_enabled],
460 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
461 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
462
463 return ERROR_OK;
464 }
465
466 static int arm920_mmu(struct target *target, int *enabled)
467 {
468 if (target->state != TARGET_HALTED) {
469 LOG_ERROR("%s: target not halted", __func__);
470 return ERROR_TARGET_INVALID;
471 }
472
473 *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
474 return ERROR_OK;
475 }
476
477 static int arm920_virt2phys(struct target *target,
478 uint32_t virt, uint32_t *phys)
479 {
480 /** @todo Implement this! */
481 LOG_ERROR("%s: not implemented", __func__);
482 return ERROR_FAIL;
483 }
484
485 /** Reads a buffer, in the specified word size, with current MMU settings. */
486 int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
487 {
488 int retval;
489
490 retval = arm7_9_read_memory(target, address, size, count, buffer);
491
492 return retval;
493 }
494
495
496 static int arm920t_read_phys_memory(struct target *target,
497 uint32_t address, uint32_t size,
498 uint32_t count, uint8_t *buffer)
499 {
500 struct arm920t_common *arm920t = target_to_arm920(target);
501
502 return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
503 address, size, count, buffer);
504 }
505
506 static int arm920t_write_phys_memory(struct target *target,
507 uint32_t address, uint32_t size,
508 uint32_t count, uint8_t *buffer)
509 {
510 struct arm920t_common *arm920t = target_to_arm920(target);
511
512 return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
513 address, size, count, buffer);
514 }
515
516
517 /** Writes a buffer, in the specified word size, with current MMU settings. */
518 int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
519 {
520 int retval;
521
522 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
523 return retval;
524
525 /* This fn is used to write breakpoints, so we need to make sure
526 * that the data cache is flushed and the instruction cache is
527 * invalidated
528 */
529 if (((size == 4) || (size == 2)) && (count == 1))
530 {
531 struct arm920t_common *arm920t = target_to_arm920(target);
532
533 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
534 {
535 LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
536 /* MCR p15,0,Rd,c7,c10,2 */
537 retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
538 if (retval != ERROR_OK)
539 return retval;
540 }
541
542 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
543 {
544 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
545 retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
546 if (retval != ERROR_OK)
547 return retval;
548 }
549 }
550
551 return retval;
552 }
553
554 // EXPORTED to FA256
555 int arm920t_soft_reset_halt(struct target *target)
556 {
557 int retval = ERROR_OK;
558 struct arm920t_common *arm920t = target_to_arm920(target);
559 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
560 struct arm *armv4_5 = &arm7_9->armv4_5_common;
561 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
562
563 if ((retval = target_halt(target)) != ERROR_OK)
564 {
565 return retval;
566 }
567
568 long long then = timeval_ms();
569 int timeout;
570 while (!(timeout = ((timeval_ms()-then) > 1000)))
571 {
572 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
573 {
574 embeddedice_read_reg(dbg_stat);
575 if ((retval = jtag_execute_queue()) != ERROR_OK)
576 {
577 return retval;
578 }
579 } else
580 {
581 break;
582 }
583 if (debug_level >= 3)
584 {
585 /* do not eat all CPU, time out after 1 se*/
586 alive_sleep(100);
587 } else
588 {
589 keep_alive();
590 }
591 }
592 if (timeout)
593 {
594 LOG_ERROR("Failed to halt CPU after 1 sec");
595 return ERROR_TARGET_TIMEOUT;
596 }
597
598 target->state = TARGET_HALTED;
599
600 /* SVC, ARM state, IRQ and FIQ disabled */
601 uint32_t cpsr;
602
603 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
604 cpsr &= ~0xff;
605 cpsr |= 0xd3;
606 arm_set_cpsr(armv4_5, cpsr);
607 armv4_5->cpsr->dirty = 1;
608
609 /* start fetching from 0x0 */
610 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
611 armv4_5->core_cache->reg_list[15].dirty = 1;
612 armv4_5->core_cache->reg_list[15].valid = 1;
613
614 arm920t_disable_mmu_caches(target, 1, 1, 1);
615 arm920t->armv4_5_mmu.mmu_enabled = 0;
616 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
617 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
618
619 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
620 {
621 return retval;
622 }
623
624 return ERROR_OK;
625 }
626
627 /* FIXME remove forward decls */
628 static int arm920t_mrc(struct target *target, int cpnum,
629 uint32_t op1, uint32_t op2,
630 uint32_t CRn, uint32_t CRm,
631 uint32_t *value);
632 static int arm920t_mcr(struct target *target, int cpnum,
633 uint32_t op1, uint32_t op2,
634 uint32_t CRn, uint32_t CRm,
635 uint32_t value);
636
637 int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
638 {
639 struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
640
641 arm7_9->armv4_5_common.mrc = arm920t_mrc;
642 arm7_9->armv4_5_common.mcr = arm920t_mcr;
643
644 /* initialize arm7/arm9 specific info (including armv4_5) */
645 arm9tdmi_init_arch_info(target, arm7_9, tap);
646
647 arm920t->common_magic = ARM920T_COMMON_MAGIC;
648
649 arm7_9->post_debug_entry = arm920t_post_debug_entry;
650 arm7_9->pre_restore_context = arm920t_pre_restore_context;
651
652 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
653 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
654 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
655 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
656 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
657 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
658 arm920t->armv4_5_mmu.has_tiny_pages = 1;
659 arm920t->armv4_5_mmu.mmu_enabled = 0;
660
661 /* disabling linefills leads to lockups, so keep them enabled for now
662 * this doesn't affect correctness, but might affect timing issues, if
663 * important data is evicted from the cache during the debug session
664 * */
665 arm920t->preserve_cache = 0;
666
667 /* override hw single-step capability from ARM9TDMI */
668 arm7_9->has_single_step = 1;
669
670 return ERROR_OK;
671 }
672
673 static int arm920t_target_create(struct target *target, Jim_Interp *interp)
674 {
675 struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
676
677 return arm920t_init_arch_info(target, arm920t, target->tap);
678 }
679
680 COMMAND_HANDLER(arm920t_handle_read_cache_command)
681 {
682 int retval = ERROR_OK;
683 struct target *target = get_current_target(CMD_CTX);
684 struct arm920t_common *arm920t = target_to_arm920(target);
685 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
686 struct arm *armv4_5 = &arm7_9->armv4_5_common;
687 uint32_t cp15c15;
688 uint32_t cp15_ctrl, cp15_ctrl_saved;
689 uint32_t regs[16];
690 uint32_t *regs_p[16];
691 uint32_t C15_C_D_Ind, C15_C_I_Ind;
692 int i;
693 FILE *output;
694 struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
695 int segment, index;
696 struct reg *r;
697
698 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
699 if (retval != ERROR_OK)
700 return retval;
701
702 if (CMD_ARGC != 1)
703 {
704 command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
705 return ERROR_OK;
706 }
707
708 if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
709 {
710 LOG_DEBUG("error opening cache content file");
711 return ERROR_OK;
712 }
713
714 for (i = 0; i < 16; i++)
715 regs_p[i] = &regs[i];
716
717 /* disable MMU and Caches */
718 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
719 if ((retval = jtag_execute_queue()) != ERROR_OK)
720 {
721 return retval;
722 }
723 cp15_ctrl_saved = cp15_ctrl;
724 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
725 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
726
727 /* read CP15 test state register */
728 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
729 jtag_execute_queue();
730
731 /* read DCache content */
732 fprintf(output, "DCache:\n");
733
734 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
735 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
736 {
737 fprintf(output, "\nsegment: %i\n----------", segment);
738
739 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
740 regs[0] = 0x0 | (segment << 5);
741 arm9tdmi_write_core_regs(target, 0x1, regs);
742
743 /* set interpret mode */
744 cp15c15 |= 0x1;
745 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
746
747 /* D CAM Read, loads current victim into C15.C.D.Ind */
748 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
749
750 /* read current victim */
751 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
752
753 /* clear interpret mode */
754 cp15c15 &= ~0x1;
755 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
756
757 for (index = 0; index < 64; index++)
758 {
759 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
760 regs[0] = 0x0 | (segment << 5) | (index << 26);
761 arm9tdmi_write_core_regs(target, 0x1, regs);
762
763 /* set interpret mode */
764 cp15c15 |= 0x1;
765 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
766
767 /* Write DCache victim */
768 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
769
770 /* Read D RAM */
771 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
772
773 /* Read D CAM */
774 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
775
776 /* clear interpret mode */
777 cp15c15 &= ~0x1;
778 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
779
780 /* read D RAM and CAM content */
781 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
782 if ((retval = jtag_execute_queue()) != ERROR_OK)
783 {
784 return retval;
785 }
786
787 d_cache[segment][index].cam = regs[9];
788
789 /* mask LFSR[6] */
790 regs[9] &= 0xfffffffe;
791 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
792
793 for (i = 1; i < 9; i++)
794 {
795 d_cache[segment][index].data[i] = regs[i];
796 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
797 }
798
799 }
800
801 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
802 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
803 arm9tdmi_write_core_regs(target, 0x1, regs);
804
805 /* set interpret mode */
806 cp15c15 |= 0x1;
807 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
808
809 /* Write DCache victim */
810 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
811
812 /* clear interpret mode */
813 cp15c15 &= ~0x1;
814 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
815 }
816
817 /* read ICache content */
818 fprintf(output, "ICache:\n");
819
820 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
821 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
822 {
823 fprintf(output, "segment: %i\n----------", segment);
824
825 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
826 regs[0] = 0x0 | (segment << 5);
827 arm9tdmi_write_core_regs(target, 0x1, regs);
828
829 /* set interpret mode */
830 cp15c15 |= 0x1;
831 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
832
833 /* I CAM Read, loads current victim into C15.C.I.Ind */
834 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
835
836 /* read current victim */
837 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
838
839 /* clear interpret mode */
840 cp15c15 &= ~0x1;
841 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
842
843 for (index = 0; index < 64; index++)
844 {
845 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
846 regs[0] = 0x0 | (segment << 5) | (index << 26);
847 arm9tdmi_write_core_regs(target, 0x1, regs);
848
849 /* set interpret mode */
850 cp15c15 |= 0x1;
851 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
852
853 /* Write ICache victim */
854 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
855
856 /* Read I RAM */
857 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
858
859 /* Read I CAM */
860 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
861
862 /* clear interpret mode */
863 cp15c15 &= ~0x1;
864 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
865
866 /* read I RAM and CAM content */
867 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
868 if ((retval = jtag_execute_queue()) != ERROR_OK)
869 {
870 return retval;
871 }
872
873 i_cache[segment][index].cam = regs[9];
874
875 /* mask LFSR[6] */
876 regs[9] &= 0xfffffffe;
877 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
878
879 for (i = 1; i < 9; i++)
880 {
881 i_cache[segment][index].data[i] = regs[i];
882 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
883 }
884 }
885
886 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
887 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
888 arm9tdmi_write_core_regs(target, 0x1, regs);
889
890 /* set interpret mode */
891 cp15c15 |= 0x1;
892 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
893
894 /* Write ICache victim */
895 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
896
897 /* clear interpret mode */
898 cp15c15 &= ~0x1;
899 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
900 }
901
902 /* restore CP15 MMU and Cache settings */
903 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
904
905 command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
906
907 fclose(output);
908
909 if (!is_arm_mode(armv4_5->core_mode))
910 return ERROR_FAIL;
911
912 /* force writeback of the valid data */
913 r = armv4_5->core_cache->reg_list;
914 r[0].dirty = r[0].valid;
915 r[1].dirty = r[1].valid;
916 r[2].dirty = r[2].valid;
917 r[3].dirty = r[3].valid;
918 r[4].dirty = r[4].valid;
919 r[5].dirty = r[5].valid;
920 r[6].dirty = r[6].valid;
921 r[7].dirty = r[7].valid;
922
923 r = arm_reg_current(armv4_5, 8);
924 r->dirty = r->valid;
925
926 r = arm_reg_current(armv4_5, 9);
927 r->dirty = r->valid;
928
929 return ERROR_OK;
930 }
931
932 COMMAND_HANDLER(arm920t_handle_read_mmu_command)
933 {
934 int retval = ERROR_OK;
935 struct target *target = get_current_target(CMD_CTX);
936 struct arm920t_common *arm920t = target_to_arm920(target);
937 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
938 struct arm *armv4_5 = &arm7_9->armv4_5_common;
939 uint32_t cp15c15;
940 uint32_t cp15_ctrl, cp15_ctrl_saved;
941 uint32_t regs[16];
942 uint32_t *regs_p[16];
943 int i;
944 FILE *output;
945 uint32_t Dlockdown, Ilockdown;
946 struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
947 int victim;
948 struct reg *r;
949
950 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
951 if (retval != ERROR_OK)
952 return retval;
953
954 if (CMD_ARGC != 1)
955 {
956 command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
957 return ERROR_OK;
958 }
959
960 if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
961 {
962 LOG_DEBUG("error opening mmu content file");
963 return ERROR_OK;
964 }
965
966 for (i = 0; i < 16; i++)
967 regs_p[i] = &regs[i];
968
969 /* disable MMU and Caches */
970 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
971 if ((retval = jtag_execute_queue()) != ERROR_OK)
972 {
973 return retval;
974 }
975 cp15_ctrl_saved = cp15_ctrl;
976 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
977 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
978
979 /* read CP15 test state register */
980 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
981 if ((retval = jtag_execute_queue()) != ERROR_OK)
982 {
983 return retval;
984 }
985
986 /* prepare reading D TLB content
987 * */
988
989 /* set interpret mode */
990 cp15c15 |= 0x1;
991 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
992
993 /* Read D TLB lockdown */
994 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
995
996 /* clear interpret mode */
997 cp15c15 &= ~0x1;
998 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
999
1000 /* read D TLB lockdown stored to r1 */
1001 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1002 if ((retval = jtag_execute_queue()) != ERROR_OK)
1003 {
1004 return retval;
1005 }
1006 Dlockdown = regs[1];
1007
1008 for (victim = 0; victim < 64; victim += 8)
1009 {
1010 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1011 * base remains unchanged, victim goes through entries 0 to 63 */
1012 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1013 arm9tdmi_write_core_regs(target, 0x2, regs);
1014
1015 /* set interpret mode */
1016 cp15c15 |= 0x1;
1017 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1018
1019 /* Write D TLB lockdown */
1020 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1021
1022 /* Read D TLB CAM */
1023 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1024
1025 /* clear interpret mode */
1026 cp15c15 &= ~0x1;
1027 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1028
1029 /* read D TLB CAM content stored to r2-r9 */
1030 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1031 if ((retval = jtag_execute_queue()) != ERROR_OK)
1032 {
1033 return retval;
1034 }
1035
1036 for (i = 0; i < 8; i++)
1037 d_tlb[victim + i].cam = regs[i + 2];
1038 }
1039
1040 for (victim = 0; victim < 64; victim++)
1041 {
1042 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1043 * base remains unchanged, victim goes through entries 0 to 63 */
1044 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1045 arm9tdmi_write_core_regs(target, 0x2, regs);
1046
1047 /* set interpret mode */
1048 cp15c15 |= 0x1;
1049 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1050
1051 /* Write D TLB lockdown */
1052 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1053
1054 /* Read D TLB RAM1 */
1055 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1056
1057 /* Read D TLB RAM2 */
1058 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1059
1060 /* clear interpret mode */
1061 cp15c15 &= ~0x1;
1062 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1063
1064 /* read D TLB RAM content stored to r2 and r3 */
1065 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1066 if ((retval = jtag_execute_queue()) != ERROR_OK)
1067 {
1068 return retval;
1069 }
1070
1071 d_tlb[victim].ram1 = regs[2];
1072 d_tlb[victim].ram2 = regs[3];
1073 }
1074
1075 /* restore D TLB lockdown */
1076 regs[1] = Dlockdown;
1077 arm9tdmi_write_core_regs(target, 0x2, regs);
1078
1079 /* Write D TLB lockdown */
1080 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1081
1082 /* prepare reading I TLB content
1083 * */
1084
1085 /* set interpret mode */
1086 cp15c15 |= 0x1;
1087 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1088
1089 /* Read I TLB lockdown */
1090 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1091
1092 /* clear interpret mode */
1093 cp15c15 &= ~0x1;
1094 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1095
1096 /* read I TLB lockdown stored to r1 */
1097 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1098 if ((retval = jtag_execute_queue()) != ERROR_OK)
1099 {
1100 return retval;
1101 }
1102 Ilockdown = regs[1];
1103
1104 for (victim = 0; victim < 64; victim += 8)
1105 {
1106 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1107 * base remains unchanged, victim goes through entries 0 to 63 */
1108 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1109 arm9tdmi_write_core_regs(target, 0x2, regs);
1110
1111 /* set interpret mode */
1112 cp15c15 |= 0x1;
1113 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1114
1115 /* Write I TLB lockdown */
1116 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1117
1118 /* Read I TLB CAM */
1119 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1120
1121 /* clear interpret mode */
1122 cp15c15 &= ~0x1;
1123 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1124
1125 /* read I TLB CAM content stored to r2-r9 */
1126 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1127 if ((retval = jtag_execute_queue()) != ERROR_OK)
1128 {
1129 return retval;
1130 }
1131
1132 for (i = 0; i < 8; i++)
1133 i_tlb[i + victim].cam = regs[i + 2];
1134 }
1135
1136 for (victim = 0; victim < 64; victim++)
1137 {
1138 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1139 * base remains unchanged, victim goes through entries 0 to 63 */
1140 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1141 arm9tdmi_write_core_regs(target, 0x2, regs);
1142
1143 /* set interpret mode */
1144 cp15c15 |= 0x1;
1145 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1146
1147 /* Write I TLB lockdown */
1148 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1149
1150 /* Read I TLB RAM1 */
1151 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1152
1153 /* Read I TLB RAM2 */
1154 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1155
1156 /* clear interpret mode */
1157 cp15c15 &= ~0x1;
1158 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1159
1160 /* read I TLB RAM content stored to r2 and r3 */
1161 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1162 if ((retval = jtag_execute_queue()) != ERROR_OK)
1163 {
1164 return retval;
1165 }
1166
1167 i_tlb[victim].ram1 = regs[2];
1168 i_tlb[victim].ram2 = regs[3];
1169 }
1170
1171 /* restore I TLB lockdown */
1172 regs[1] = Ilockdown;
1173 arm9tdmi_write_core_regs(target, 0x2, regs);
1174
1175 /* Write I TLB lockdown */
1176 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1177
1178 /* restore CP15 MMU and Cache settings */
1179 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1180
1181 /* output data to file */
1182 fprintf(output, "D TLB content:\n");
1183 for (i = 0; i < 64; i++)
1184 {
1185 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1186 }
1187
1188 fprintf(output, "\n\nI TLB content:\n");
1189 for (i = 0; i < 64; i++)
1190 {
1191 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1192 }
1193
1194 command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
1195
1196 fclose(output);
1197
1198 if (!is_arm_mode(armv4_5->core_mode))
1199 return ERROR_FAIL;
1200
1201 /* force writeback of the valid data */
1202 r = armv4_5->core_cache->reg_list;
1203 r[0].dirty = r[0].valid;
1204 r[1].dirty = r[1].valid;
1205 r[2].dirty = r[2].valid;
1206 r[3].dirty = r[3].valid;
1207 r[4].dirty = r[4].valid;
1208 r[5].dirty = r[5].valid;
1209 r[6].dirty = r[6].valid;
1210 r[7].dirty = r[7].valid;
1211
1212 r = arm_reg_current(armv4_5, 8);
1213 r->dirty = r->valid;
1214
1215 r = arm_reg_current(armv4_5, 9);
1216 r->dirty = r->valid;
1217
1218 return ERROR_OK;
1219 }
1220
1221 COMMAND_HANDLER(arm920t_handle_cp15_command)
1222 {
1223 int retval;
1224 struct target *target = get_current_target(CMD_CTX);
1225 struct arm920t_common *arm920t = target_to_arm920(target);
1226
1227 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1228 if (retval != ERROR_OK)
1229 return retval;
1230
1231 if (target->state != TARGET_HALTED)
1232 {
1233 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1234 return ERROR_OK;
1235 }
1236
1237 /* one or more argument, access a single register (write if second argument is given */
1238 if (CMD_ARGC >= 1)
1239 {
1240 int address;
1241 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
1242
1243 if (CMD_ARGC == 1)
1244 {
1245 uint32_t value;
1246 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1247 {
1248 command_print(CMD_CTX, "couldn't access reg %i", address);
1249 return ERROR_OK;
1250 }
1251 if ((retval = jtag_execute_queue()) != ERROR_OK)
1252 {
1253 return retval;
1254 }
1255
1256 command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1257 }
1258 else if (CMD_ARGC == 2)
1259 {
1260 uint32_t value;
1261 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1262 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1263 {
1264 command_print(CMD_CTX, "couldn't access reg %i", address);
1265 return ERROR_OK;
1266 }
1267 command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1268 }
1269 }
1270
1271 return ERROR_OK;
1272 }
1273
1274 COMMAND_HANDLER(arm920t_handle_cp15i_command)
1275 {
1276 int retval;
1277 struct target *target = get_current_target(CMD_CTX);
1278 struct arm920t_common *arm920t = target_to_arm920(target);
1279
1280 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1281 if (retval != ERROR_OK)
1282 return retval;
1283
1284
1285 if (target->state != TARGET_HALTED)
1286 {
1287 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1288 return ERROR_OK;
1289 }
1290
1291 /* one or more argument, access a single register (write if second argument is given */
1292 if (CMD_ARGC >= 1)
1293 {
1294 uint32_t opcode;
1295 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
1296
1297 if (CMD_ARGC == 1)
1298 {
1299 uint32_t value;
1300 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1301 {
1302 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1303 return ERROR_OK;
1304 }
1305
1306 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1307 }
1308 else if (CMD_ARGC == 2)
1309 {
1310 uint32_t value;
1311 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1312 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1313 {
1314 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1315 return ERROR_OK;
1316 }
1317 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1318 }
1319 else if (CMD_ARGC == 3)
1320 {
1321 uint32_t value;
1322 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1323 uint32_t address;
1324 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
1325 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1326 {
1327 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1328 return ERROR_OK;
1329 }
1330 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1331 }
1332 }
1333 else
1334 {
1335 command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
1336 }
1337
1338 return ERROR_OK;
1339 }
1340
1341 COMMAND_HANDLER(arm920t_handle_cache_info_command)
1342 {
1343 int retval;
1344 struct target *target = get_current_target(CMD_CTX);
1345 struct arm920t_common *arm920t = target_to_arm920(target);
1346
1347 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1348 if (retval != ERROR_OK)
1349 return retval;
1350
1351 return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
1352 }
1353
1354
1355 static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
1356 {
1357 if (cpnum!=15)
1358 {
1359 LOG_ERROR("Only cp15 is supported");
1360 return ERROR_FAIL;
1361 }
1362
1363 return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
1364 }
1365
1366 static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
1367 {
1368 if (cpnum!=15)
1369 {
1370 LOG_ERROR("Only cp15 is supported");
1371 return ERROR_FAIL;
1372 }
1373
1374 return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
1375 }
1376
1377 static const struct command_registration arm920t_exec_command_handlers[] = {
1378 {
1379 .name = "cp15",
1380 .handler = &arm920t_handle_cp15_command,
1381 .mode = COMMAND_EXEC,
1382 .help = "display/modify cp15 register",
1383 .usage = "<num> [value]",
1384 },
1385 {
1386 .name = "cp15i",
1387 .handler = &arm920t_handle_cp15i_command,
1388 .mode = COMMAND_EXEC,
1389 .help = "display/modify cp15 (interpreted access)",
1390 .usage = "<opcode> [value] [address]",
1391 },
1392 {
1393 .name = "cache_info",
1394 .handler = &arm920t_handle_cache_info_command,
1395 .mode = COMMAND_EXEC,
1396 .help = "display information about target caches",
1397 },
1398 {
1399 .name = "read_cache",
1400 .handler = &arm920t_handle_read_cache_command,
1401 .mode = COMMAND_EXEC,
1402 .help = "display I/D cache content",
1403 },
1404 {
1405 .name = "read_mmu",
1406 .handler = &arm920t_handle_read_mmu_command,
1407 .mode = COMMAND_EXEC,
1408 .help = "display I/D mmu content",
1409 },
1410 COMMAND_REGISTRATION_DONE
1411 };
1412 const struct command_registration arm920t_command_handlers[] = {
1413 {
1414 .chain = arm9tdmi_command_handlers,
1415 },
1416 {
1417 .name = "arm920t",
1418 .mode = COMMAND_ANY,
1419 .help = "arm920t command group",
1420 .chain = arm920t_exec_command_handlers,
1421 },
1422 COMMAND_REGISTRATION_DONE
1423 };
1424
1425 /** Holds methods for ARM920 targets. */
1426 struct target_type arm920t_target =
1427 {
1428 .name = "arm920t",
1429
1430 .poll = arm7_9_poll,
1431 .arch_state = arm920t_arch_state,
1432
1433 .target_request_data = arm7_9_target_request_data,
1434
1435 .halt = arm7_9_halt,
1436 .resume = arm7_9_resume,
1437 .step = arm7_9_step,
1438
1439 .assert_reset = arm7_9_assert_reset,
1440 .deassert_reset = arm7_9_deassert_reset,
1441 .soft_reset_halt = arm920t_soft_reset_halt,
1442
1443 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1444
1445 .read_memory = arm920t_read_memory,
1446 .write_memory = arm920t_write_memory,
1447 .read_phys_memory = arm920t_read_phys_memory,
1448 .write_phys_memory = arm920t_write_phys_memory,
1449 .mmu = arm920_mmu,
1450 .virt2phys = arm920_virt2phys,
1451
1452 .bulk_write_memory = arm7_9_bulk_write_memory,
1453
1454 .checksum_memory = arm_checksum_memory,
1455 .blank_check_memory = arm_blank_check_memory,
1456
1457 .run_algorithm = armv4_5_run_algorithm,
1458
1459 .add_breakpoint = arm7_9_add_breakpoint,
1460 .remove_breakpoint = arm7_9_remove_breakpoint,
1461 .add_watchpoint = arm7_9_add_watchpoint,
1462 .remove_watchpoint = arm7_9_remove_watchpoint,
1463
1464 .commands = arm920t_command_handlers,
1465 .target_create = arm920t_target_create,
1466 .init_target = arm9tdmi_init_target,
1467 .examine = arm7_9_examine,
1468 };
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