3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 if { [info exists ENDIAN] } {
15 if { [info exists CPUTAPID] } {
16 set _CPUTAPID $CPUTAPID
18 set _CPUTAPID 0x4f1f0041
24 #use combined on interfaces or targets that can't set TRST/SRST separately
25 reset_config trst_and_srst srst_pulls_trst
29 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
31 #jtag nTRST and nSRST delay
32 adapter_nsrst_delay 500
35 set _TARGETNAME $_CHIPNAME.cpu
36 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
38 $_TARGETNAME configure -event reset-start { adapter_khz 10 }
39 $_TARGETNAME configure -event reset-init {
43 # Because the hardware cannot be interrogated for the protection state
44 # of sectors, initialize all the sectors to be unprotected. The initial
45 # state is reflected by the driver, too.
46 flash protect 0 0 last off
47 flash protect 1 0 last off
49 $_TARGETNAME configure -event gdb-flash-erase-start {
50 flash protect 0 0 7 off
51 flash protect 1 0 1 off
54 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
56 #flash bank <driver> <base> <size> <chip_width> <bus_width>
57 set _FLASHNAME $_CHIPNAME.flash0
58 flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
59 set _FLASHNAME $_CHIPNAME.flash1
60 flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
62 # Serial NOR on SMI CS0.
63 set _FLASHNAME $_CHIPNAME.snor
64 flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME
66 source [find mem_helper.tcl]
69 mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
70 mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
71 mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1