1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/time_support.h>
28 #include "target_type.h"
30 #include "arm_opcodes.h"
34 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
35 * ARM DDI 0229C especially Chapter 9 about debug support.
39 #define _DEBUG_INSTRUCTION_EXECUTION_
42 static int arm720t_scan_cp15(struct target
*target
,
43 uint32_t out
, uint32_t *in
, int instruction
, int clock_arg
)
46 struct arm720t_common
*arm720t
= target_to_arm720(target
);
47 struct arm_jtag
*jtag_info
;
48 struct scan_field fields
[2];
50 uint8_t instruction_buf
= instruction
;
52 jtag_info
= &arm720t
->arm7_9_common
.jtag_info
;
54 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
56 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_DRPAUSE
);
57 if (retval
!= ERROR_OK
)
59 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_DRPAUSE
);
60 if (retval
!= ERROR_OK
)
63 fields
[0].num_bits
= 1;
64 fields
[0].out_value
= &instruction_buf
;
65 fields
[0].in_value
= NULL
;
67 fields
[1].num_bits
= 32;
68 fields
[1].out_value
= out_buf
;
69 fields
[1].in_value
= NULL
;
72 fields
[1].in_value
= (uint8_t *)in
;
73 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
74 jtag_add_callback(arm7flip32
, (jtag_callback_data_t
)in
);
76 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_DRPAUSE
);
79 jtag_add_runtest(0, TAP_DRPAUSE
);
81 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
82 retval
= jtag_execute_queue();
83 if (retval
!= ERROR_OK
)
87 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
89 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock_arg
);
91 LOG_DEBUG("out: %8.8" PRIx32
", instruction: %i, clock: %i", out
, instruction
, clock_arg
);
97 static int arm720t_read_cp15(struct target
*target
, uint32_t opcode
, uint32_t *value
)
99 /* fetch CP15 opcode */
100 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
102 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
103 /* "EXECUTE" stage (1) */
104 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
105 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
106 /* "EXECUTE" stage (2) */
107 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
108 /* "EXECUTE" stage (3), CDATA is read */
109 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
114 static int arm720t_write_cp15(struct target
*target
, uint32_t opcode
, uint32_t value
)
116 /* fetch CP15 opcode */
117 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
119 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
120 /* "EXECUTE" stage (1) */
121 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
122 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
123 /* "EXECUTE" stage (2) */
124 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
125 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
130 static int arm720t_get_ttb(struct target
*target
, uint32_t *result
)
136 retval
= arm720t_read_cp15(target
, 0xee120f10, &ttb
);
137 if (retval
!= ERROR_OK
)
139 retval
= jtag_execute_queue();
140 if (retval
!= ERROR_OK
)
150 static int arm720t_disable_mmu_caches(struct target
*target
,
151 int mmu
, int d_u_cache
, int i_cache
)
153 uint32_t cp15_control
;
156 /* read cp15 control register */
157 retval
= arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
158 if (retval
!= ERROR_OK
)
160 retval
= jtag_execute_queue();
161 if (retval
!= ERROR_OK
)
165 cp15_control
&= ~0x1U
;
167 if (d_u_cache
|| i_cache
)
168 cp15_control
&= ~0x4U
;
170 retval
= arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
174 static int arm720t_enable_mmu_caches(struct target
*target
,
175 int mmu
, int d_u_cache
, int i_cache
)
177 uint32_t cp15_control
;
180 /* read cp15 control register */
181 retval
= arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
182 if (retval
!= ERROR_OK
)
184 retval
= jtag_execute_queue();
185 if (retval
!= ERROR_OK
)
189 cp15_control
|= 0x1U
;
191 if (d_u_cache
|| i_cache
)
192 cp15_control
|= 0x4U
;
194 retval
= arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
198 static int arm720t_post_debug_entry(struct target
*target
)
200 struct arm720t_common
*arm720t
= target_to_arm720(target
);
203 /* examine cp15 control reg */
204 retval
= arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
205 if (retval
!= ERROR_OK
)
207 retval
= jtag_execute_queue();
208 if (retval
!= ERROR_OK
)
210 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm720t
->cp15_control_reg
);
212 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
213 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
214 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
216 /* save i/d fault status and address register */
217 retval
= arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
218 if (retval
!= ERROR_OK
)
220 retval
= arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
221 if (retval
!= ERROR_OK
)
223 retval
= jtag_execute_queue();
227 static void arm720t_pre_restore_context(struct target
*target
)
229 struct arm720t_common
*arm720t
= target_to_arm720(target
);
231 /* restore i/d fault status and address register */
232 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
233 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
236 static int arm720t_verify_pointer(struct command_context
*cmd_ctx
,
237 struct arm720t_common
*arm720t
)
239 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
) {
240 command_print(cmd_ctx
, "target is not an ARM720");
241 return ERROR_TARGET_INVALID
;
246 static int arm720t_arch_state(struct target
*target
)
248 struct arm720t_common
*arm720t
= target_to_arm720(target
);
250 static const char *state
[] = {
251 "disabled", "enabled"
254 arm_arch_state(target
);
255 LOG_USER("MMU: %s, Cache: %s",
256 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
257 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
262 static int arm720_mmu(struct target
*target
, int *enabled
)
264 if (target
->state
!= TARGET_HALTED
) {
265 LOG_ERROR("%s: target not halted", __func__
);
266 return ERROR_TARGET_INVALID
;
269 *enabled
= target_to_arm720(target
)->armv4_5_mmu
.mmu_enabled
;
273 static int arm720_virt2phys(struct target
*target
,
274 uint32_t virtual, uint32_t *physical
)
277 struct arm720t_common
*arm720t
= target_to_arm720(target
);
280 int retval
= armv4_5_mmu_translate_va(target
,
281 &arm720t
->armv4_5_mmu
, virtual, &cb
, &ret
);
282 if (retval
!= ERROR_OK
)
288 static int arm720t_read_memory(struct target
*target
,
289 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
292 struct arm720t_common
*arm720t
= target_to_arm720(target
);
294 /* disable cache, but leave MMU enabled */
295 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
296 retval
= arm720t_disable_mmu_caches(target
, 0, 1, 0);
297 if (retval
!= ERROR_OK
)
300 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
302 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) {
303 retval
= arm720t_enable_mmu_caches(target
, 0, 1, 0);
304 if (retval
!= ERROR_OK
)
311 static int arm720t_read_phys_memory(struct target
*target
,
312 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
314 struct arm720t_common
*arm720t
= target_to_arm720(target
);
316 return armv4_5_mmu_read_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
319 static int arm720t_write_phys_memory(struct target
*target
,
320 uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t *buffer
)
322 struct arm720t_common
*arm720t
= target_to_arm720(target
);
324 return armv4_5_mmu_write_physical(target
, &arm720t
->armv4_5_mmu
, address
, size
, count
, buffer
);
327 static int arm720t_soft_reset_halt(struct target
*target
)
329 int retval
= ERROR_OK
;
330 struct arm720t_common
*arm720t
= target_to_arm720(target
);
331 struct reg
*dbg_stat
= &arm720t
->arm7_9_common
332 .eice_cache
->reg_list
[EICE_DBG_STAT
];
333 struct arm
*arm
= &arm720t
->arm7_9_common
.arm
;
335 retval
= target_halt(target
);
336 if (retval
!= ERROR_OK
)
339 int64_t then
= timeval_ms();
341 while (!(timeout
= ((timeval_ms()-then
) > 1000))) {
342 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0) {
343 embeddedice_read_reg(dbg_stat
);
344 retval
= jtag_execute_queue();
345 if (retval
!= ERROR_OK
)
349 if (debug_level
>= 3)
355 LOG_ERROR("Failed to halt CPU after 1 sec");
356 return ERROR_TARGET_TIMEOUT
;
359 target
->state
= TARGET_HALTED
;
361 /* SVC, ARM state, IRQ and FIQ disabled */
364 cpsr
= buf_get_u32(arm
->cpsr
->value
, 0, 32);
367 arm_set_cpsr(arm
, cpsr
);
368 arm
->cpsr
->dirty
= 1;
370 /* start fetching from 0x0 */
371 buf_set_u32(arm
->pc
->value
, 0, 32, 0x0);
375 retval
= arm720t_disable_mmu_caches(target
, 1, 1, 1);
376 if (retval
!= ERROR_OK
)
378 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
379 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
380 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
382 retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
383 if (retval
!= ERROR_OK
)
389 static int arm720t_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
391 return arm7tdmi_init_target(cmd_ctx
, target
);
394 /* FIXME remove forward decls */
395 static int arm720t_mrc(struct target
*target
, int cpnum
,
396 uint32_t op1
, uint32_t op2
,
397 uint32_t CRn
, uint32_t CRm
,
399 static int arm720t_mcr(struct target
*target
, int cpnum
,
400 uint32_t op1
, uint32_t op2
,
401 uint32_t CRn
, uint32_t CRm
,
404 static int arm720t_init_arch_info(struct target
*target
,
405 struct arm720t_common
*arm720t
, struct jtag_tap
*tap
)
407 struct arm7_9_common
*arm7_9
= &arm720t
->arm7_9_common
;
409 arm7_9
->arm
.mrc
= arm720t_mrc
;
410 arm7_9
->arm
.mcr
= arm720t_mcr
;
412 arm7tdmi_init_arch_info(target
, arm7_9
, tap
);
414 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
416 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
417 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
419 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
420 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
421 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
422 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
423 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
424 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
425 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
426 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
431 static int arm720t_target_create(struct target
*target
, Jim_Interp
*interp
)
433 struct arm720t_common
*arm720t
= calloc(1, sizeof(*arm720t
));
435 arm720t
->arm7_9_common
.arm
.is_armv4
= true;
436 return arm720t_init_arch_info(target
, arm720t
, target
->tap
);
439 COMMAND_HANDLER(arm720t_handle_cp15_command
)
442 struct target
*target
= get_current_target(CMD_CTX
);
443 struct arm720t_common
*arm720t
= target_to_arm720(target
);
445 retval
= arm720t_verify_pointer(CMD_CTX
, arm720t
);
446 if (retval
!= ERROR_OK
)
449 if (target
->state
!= TARGET_HALTED
) {
450 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
454 /* one or more argument, access a single register (write if second argument is given */
457 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], opcode
);
461 retval
= arm720t_read_cp15(target
, opcode
, &value
);
462 if (retval
!= ERROR_OK
) {
463 command_print(CMD_CTX
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
467 retval
= jtag_execute_queue();
468 if (retval
!= ERROR_OK
)
471 command_print(CMD_CTX
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
472 } else if (CMD_ARGC
== 2) {
474 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
476 retval
= arm720t_write_cp15(target
, opcode
, value
);
477 if (retval
!= ERROR_OK
) {
478 command_print(CMD_CTX
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
481 command_print(CMD_CTX
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
488 static int arm720t_mrc(struct target
*target
, int cpnum
,
489 uint32_t op1
, uint32_t op2
,
490 uint32_t CRn
, uint32_t CRm
,
494 LOG_ERROR("Only cp15 is supported");
499 return arm720t_read_cp15(target
,
500 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
505 static int arm720t_mcr(struct target
*target
, int cpnum
,
506 uint32_t op1
, uint32_t op2
,
507 uint32_t CRn
, uint32_t CRm
,
511 LOG_ERROR("Only cp15 is supported");
515 /* write "from" r0 */
516 return arm720t_write_cp15(target
,
517 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
521 static const struct command_registration arm720t_exec_command_handlers
[] = {
524 .handler
= arm720t_handle_cp15_command
,
525 .mode
= COMMAND_EXEC
,
526 /* prefer using less error-prone "arm mcr" or "arm mrc" */
527 .help
= "display/modify cp15 register using ARM opcode"
529 .usage
= "instruction [value]",
531 COMMAND_REGISTRATION_DONE
534 static const struct command_registration arm720t_command_handlers
[] = {
536 .chain
= arm7_9_command_handlers
,
541 .help
= "arm720t command group",
543 .chain
= arm720t_exec_command_handlers
,
545 COMMAND_REGISTRATION_DONE
548 /** Holds methods for ARM720 targets. */
549 struct target_type arm720t_target
= {
553 .arch_state
= arm720t_arch_state
,
556 .resume
= arm7_9_resume
,
559 .assert_reset
= arm7_9_assert_reset
,
560 .deassert_reset
= arm7_9_deassert_reset
,
561 .soft_reset_halt
= arm720t_soft_reset_halt
,
563 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
565 .read_memory
= arm720t_read_memory
,
566 .write_memory
= arm7_9_write_memory_opt
,
567 .read_phys_memory
= arm720t_read_phys_memory
,
568 .write_phys_memory
= arm720t_write_phys_memory
,
570 .virt2phys
= arm720_virt2phys
,
572 .checksum_memory
= arm_checksum_memory
,
573 .blank_check_memory
= arm_blank_check_memory
,
575 .run_algorithm
= armv4_5_run_algorithm
,
577 .add_breakpoint
= arm7_9_add_breakpoint
,
578 .remove_breakpoint
= arm7_9_remove_breakpoint
,
579 .add_watchpoint
= arm7_9_add_watchpoint
,
580 .remove_watchpoint
= arm7_9_remove_watchpoint
,
582 .commands
= arm720t_command_handlers
,
583 .target_create
= arm720t_target_create
,
584 .init_target
= arm720t_init_target
,
585 .examine
= arm7_9_examine
,
586 .check_reset
= arm7_9_check_reset
,